Power gating circuit and chip

Abstract

The utility model provides a power gating circuit and a chip, which belong to the technical field of semiconductor circuits, and comprise a first gating link used for controlling the chip to be pre-electrified; the first gating link comprises a first control signal input end and a plurality of first gating units, power supply pins of the plurality of first gating units are connected in parallel, switching signals of the plurality of first gating units are connected in series, and the switching signals of the first gating units are connected with the first control signal input end; at least one delay unit is connected in series between every two adjacent first gating units, and the delay units are used for controlling the current change rate in the chip power-on process. According to the utility model, the current change rate generated when the first gating unit in the first gating link is opened is reduced through the time delay unit, and the power supply stability of the whole power supply system is improved.

Description

Technical Field

[0001] The utility model belongs to the technical field of semiconductor circuits, and relates to a gate control circuit applied to semiconductors, in particular to a power gate control circuit and a chip. Background Art

[0002] Power gating means that the power supply of a certain area in the chip is turned off, that is, the power supply of the logic circuit in the area is disconnected. The purpose of setting power gating is to selectively shut down the power supply of certain functional modules in the chip while maintaining the power supply of other functional modules. That is, through power gating, the power supply corresponding to the functional modules that do not need power supply in the current working mode can be temporarily cut off to reduce leakage current and power consumption. Therefore, power gating is used in low-power chips to realize the switching of chip power-on and power-off processes.

[0003] In order to ensure the stability of the entire power supply system during the power-on and power-off processes, power gating generally exists in a chain structure to form a gating chain. The speed of the gating units on the gating chain cannot be too fast during the power-on or power-off process, otherwise it will affect the stability of the power supply network. Therefore, during the power-on process of the gating units on the gating chain, the resistance brought to the power supply network by the gating units cannot be too large, otherwise the voltage drop will deteriorate significantly, resulting in insufficient power supply to the corresponding devices and causing chip function problems. On the other hand, the quantitative requirements for dynamic power-on are that the rush current cannot be too large, and the rush current change rate cannot be too large (that is, the rate of change of current over time, di / dt, mA / ns). Otherwise, it will cause large instantaneous fluctuations in the power supply network and affect the adjacent circuits that are working.

[0004] The prior art proposes to reduce the current change rate generated when the gate chain is turned on by changing the length of the gate chain. The increase in the length of the short chain increases the time of all opening, but more gate units turned on bring greater current capacity, and the numerator and denominator of di / dt change in the same direction. At this time, the adjustment of the short chain length may increase or decrease the current change rate. Therefore, by adjusting the length of the gate chain, the current change rate cannot be directly and effectively controlled, and the technical problem of poor stability of the entire power supply system still exists. Utility Model Content

[0005] Based on the above background technology, the prior art cannot directly and effectively control the current change rate by adjusting the length of the gating chain, and there is still a technical problem of poor power supply stability of the entire power supply system. In response to this technical problem, the utility model proposes a power gating circuit and chip.

[0006] The utility model sets a delay unit on the first gated link, and reduces the current change rate generated by the first gated unit in the first gated link through the delay unit, so that the fluctuation influence on the power supply network during the opening of the first gated unit is controlled within the acceptable range of the power supply, and when all the first gated links are opened, the voltage difference on both sides of the first gated unit in the first gated link is relatively smaller. Therefore, the opening time of all the first gated units on the first gated link is extended, and the impact current of the first gated link remains unchanged or even reduced, so that when all the first gated links are opened, the voltage difference on both sides of the first gated unit in the first gated link is relatively reduced, thereby improving the power supply stability of the entire power supply system.

[0007] In order to solve the above technical problems, the technical solution adopted by the utility model is:

[0008] The utility model provides a power gate control circuit, comprising:

[0009] A first gating link, wherein the first gating link is used to control the chip to pre-power on; the first gating link comprises a first control signal input terminal and a plurality of first gating units, power pins of the plurality of first gating units are connected in parallel, switch signals of the plurality of first gating units are connected in series, and the switch signals of the first gating units are connected to the first control signal input terminal, and at least one delay unit is arranged between two adjacent first gating units, and the delay unit is used to control the current change rate during the chip power-on process.

[0010] It is further defined that the power gating circuit also includes a second gating link parallel to the first gating link, the second gating link is used to control the chip to power on; the second gating link includes a second control signal input terminal and a plurality of second gating units, the power pins of the plurality of second gating units are connected in parallel, the switch signals of the plurality of second gating units are connected in series, and the switch signals of the second gating units are connected to the second control signal input terminal;

[0011] The number of first gating units in the first gating link is less than the number of second gating units in the second gating link.

[0012] It is further defined that the first control signal input terminal of the first gating link receives a first control signal to turn on the first gating unit; the second control signal input terminal of the second gating link receives a second control signal to turn on the second gating unit; the first gating link receives the first control signal earlier than the second gating link receives the second control signal.

[0013] It is further defined that, in the first gating link, at least one delay unit is provided between the first control signal input terminal and a first gating unit close to the first control signal input terminal.

[0014] It is further defined that there are multiple delay units arranged between two adjacent first gating units, and the multiple delay units are connected in series;

[0015] And / or, there are multiple delay units arranged between the first control signal input terminal and the first gating unit close to the first control signal input terminal, and the multiple delay units are connected in series.

[0016] It is further defined that, in the first gating link, the number of the delay units is negatively correlated with the current change rate during the pre-power-on process of the first gating link.

[0017] It is further defined that, in the first gating link, the number of the first gating units is negatively correlated with the current change rate during the pre-power-on process of the first gating link, and the number of the first gating units meets a preset condition.

[0018] It is further defined that the calculation formula of the current change rate di / dt of the first gating link is:

[0019]

[0020] Wherein, A0 refers to the fixed current reached when all the first gating control units in the first gating control link are fully turned on, unit: mA; m refers to the number of first gating control units in the first gating control link, unit: piece; T1 refers to the delay time of a first gating control unit in the first gating control link, unit: ns; n refers to the number of delay units in the first gating link, unit: piece; T2 refers to the delay time of a delay unit in the first gating link, unit: ns; the fixed current A0 reached when all the first gating control units in the first gating control link are fully turned on is positively correlated with the number of first gating control units;

[0021] The preset condition for the number of first gating units refers to the number of first gating units corresponding to a current change rate of 20 mA / ns.

[0022] It is further defined that the delay unit is a buffer.

[0023] The utility model provides a chip, and the chip is formed based on the power gating circuit mentioned above.

[0024] Compared with the prior art, the beneficial effects of the utility model are:

[0025] 1. The utility model provides a power gating circuit, including a first gating link, wherein the first gating link includes a first control signal input terminal, a plurality of first gating units, and at least one delay unit arranged between two adjacent first gating units. The utility model arranges a delay unit on the first gating link, and reduces the current change rate generated when the first gating unit in the first gating link is turned on by the delay unit, so that the fluctuation influence on the power supply network during the process of turning on the first gating unit by the first gating unit is controlled within the acceptable range of the power supply, and when all the first gating links are turned on, the voltage difference between the two sides of the first gating unit in the first gating link is relatively smaller, which greatly reduces the current value when the second gating link is turned on, and improves the power supply stability of the entire power supply system.

[0026] 2. The utility model can adapt to the first gating link on the power gating of any length. By increasing or decreasing the number of delay units in the first gating link, the current change rate di / dt of the impact current during the pre-power-on process of the first gating link can be directly and accurately reduced, and the opening process of the first gating link can be delayed, so that the impact current peak value and the current change rate of the impact current of the first gating link are reduced.

[0027] 3. In the present invention, the time when the first gating link receives the first control signal is earlier than the time when the second gating link receives the second control signal. The first gating link is opened first, and after the voltage of the entire power supply system rises to a certain level, the second gating link is opened to reduce the voltage difference when the second gating link is opened, further reduce the current peak, and make the power supply of the power supply system more stable.

[0028] 4. The delay unit of the utility model is arranged between the first control signal input terminal and the first gate control unit close to the first control signal input terminal, which has a better effect on reducing the initial impact current change rate. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] Figure 1 is a schematic diagram of one of the gate control units, which includes four connection ports: Ctr l, Ctr l_o, VDD and VDDS;

[0030] Figure 2 is a schematic diagram of an existing power gating circuit;

[0031] Figure 3 This is a schematic diagram of power gating of the utility model;

[0032] Figure 4 Current changes of the first gating link and the second gating link during the power-on process of the existing power gating circuit;

[0033] Among them, 1-first gating link, 101-first gating unit, 2-second gating link, 201-second gating unit, 3-delay unit. DETAILED DESCRIPTION

[0034] In order to make the technical solution of the utility model clearer, the technical solution of the utility model will be clearly and completely described below in combination with the embodiments and drawings. Obviously, the described embodiments are part of the embodiments of the utility model, not all of the embodiments. Therefore, the following detailed description of the embodiments of the utility model provided in the drawings is not intended to limit the scope of protection claimed, but merely represents the selected embodiments of the utility model. Based on the embodiments in the utility model, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the utility model.

[0035] See also Figure 1 , is a schematic diagram of the structure of a gating unit (first gating unit 101 or second gating unit 201) in the first gating link 1 or the second gating link 2, on which four connection ports are arranged, namely, a Ctr l connection port, a Ctrl_o connection port, a VDD connection port and a VDDS connection port.

[0036] See also Figure 2 , is a schematic diagram of an existing power gating circuit; it includes a second gating link 2 and a first gating link 1 arranged in parallel with the second gating link 2, the first gating link 1 includes a first control signal input terminal, a first control signal output terminal and a plurality of first gating units 101 connected in parallel, the second gating link 2 includes a second control signal input terminal, a second control signal output terminal and a plurality of second gating units 201 connected in parallel, and the number of second gating units 201 on the second gating link 2 is greater than the number of first gating units 101 on the first gating link 1, the first gating link 1 is used to control the pre-power-on (pre-power-on or pre-power-off) of the chip, and the second gating link 2 is used to control the power-on work of the chip (all power-on or all power-off of power gating). In the process of powering on or off the first gating link 1, the switching speed of the first gating unit 101 on the first gating link 1 cannot be too fast. Because in the process of powering on or off the power of the power gating, the resistance brought to the power supply network by the first gating unit 101 and the second gating unit 201 cannot be too large, otherwise the voltage drop deteriorates more, which will cause the device to fail to work normally. Specifically speaking, the quantitative requirements for dynamic power-on are that the impact current cannot be too large, and the current change rate of the impact current cannot be too large. The purpose of setting the first gating link 1 is to avoid the second gating link 2 from having a current peak that is too large during the power-on or power-off process, that is, the current change rate is too large, which affects the stability of the entire circuit.

[0037] Taking the actual power-on process as an example, after the first gated link 1 is turned on for a period of time (for example, 200ns), the second gated link 2 of the power gate is turned on again. At this time, the power supply voltage has basically risen to more than 90% of the standard voltage. At this time, when the second gated link 2 is turned on, there will basically be no current peak. However, the current peak will appear in the process of powering on the first gated link 1, and the peak value of the current change rate di / dt of the impact current will also appear in the process of opening the first gated link 1. See Figure 4 In the figure, segment 001 is the current change during the gradual opening process of the first gated link 1, and the decreasing part of segment 002 is the current change after the first gated link is fully opened; segment 003 is the current change when the second gated link 2 is opened in sequence, and segment 004 is the current change when the current gradually decreases after the second gated link 2 is fully opened. Finally, the voltage difference between the two pins of the power gate approaches 0, and the current stabilizes at a value. Therefore, the current peak will appear in the power-on process of the first gated link 1.

[0038] When the length of the first gating link 1 is increased, wherein increasing the length of the first gating link 1 refers to increasing the number of first gating units 101 on the first gating link 1, the opening time of the first gating link 1 is increased. Since the number of opened first gating units 101 is increased, a larger impact current can pass through. At this time, although the opening time of the first gating link 1 is increased, the impact current is also increased accordingly. Therefore, the current change rate di / dt of the impact current does not necessarily increase or decrease.

[0039] When the length of the first gating link 1 is shortened, wherein shortening the length of the first gating link 1 refers to reducing the number of first gating units 101 on the first gating link 1, the opening time of the first gating link 1 is shortened. Since the number of opened first gating units 101 is reduced, the impact current passing through is also reduced. At this time, although the opening time of the first gating link 1 is shortened, the impact current is also reduced accordingly. Therefore, the current change rate di / dt of the impact current does not necessarily increase or decrease.

[0040] It can be seen from this that adjusting the length of the first gating link 1 by changing the length of the first gating link 1 cannot directly and effectively control the impact current and the current change rate of the impact current.

[0041] Example 1

[0042] See also Figure 3In this embodiment, a power gating circuit includes: a first gating link 1, which is used to control the chip to pre-power on; the first gating link 1 includes a first control signal input terminal, a first control signal output terminal and a plurality of first gating units 101, the power pins of the plurality of first gating units 101 are connected in parallel, the switch signals of the plurality of first gating units 101 are connected in series, and the switch signals of the first gating units 101 are connected to the first control signal input terminal and the first control signal output terminal, and at least one delay unit 3 is arranged between two adjacent first gating units 101, and the delay unit 3 is used to control the current change rate during the chip power-on process.

[0043] Specifically, in the present embodiment, two adjacent first gating units 101 are connected; the power input terminal of each first gating unit 101 (VDD connection port of the first gating unit 101) is connected to the normally open power line VDD, and the power output terminal of each first gating unit 101 (VDDS connection port of the first gating unit 101) is connected to the shutoff power line VDDS; each first gating unit 101 is connected to the normally open power line VDD and the shutoff power line VDDS so that the power pins of multiple first gating units 101 are connected in parallel; and at least one delay unit 3 arranged between two adjacent first gating units 101 is connected in series with the first gating unit 101.

[0044] The delay unit 3 in this embodiment is a buffer or other electronic components that can be used for delay. Preferably, the delay unit 3 in this embodiment is a buffer. It should be noted that the delay unit 3 needs to be kept normally open during the working process.

[0045] In this embodiment, a delay unit 3 is set on the first gating link 1, and the current change rate generated by the first gating unit 101 in the first gating link 1 is reduced by the delay unit 3, so that during the power-on process of the first gating link 1, the voltage difference on both sides of the first gating unit 101 is gradually reduced, and the longer the time, the smaller the voltage difference. Therefore, the opening time of all the first gating units 101 on the first gating link 1 is extended, and the impact current of the first gating link 1 remains unchanged or even reduced, so that when all the first gating links 1 are turned on, the current change rate di / dt of the impact current during the pre-power-on process of the first gating link 1 is reduced, and the voltage difference on both sides of the first gating unit 101 in the first gating link 1 is relatively smaller, thereby improving the power supply stability of the entire power supply system.

[0046] Example 2

[0047] The present embodiment provides a power gating circuit, which, based on the embodiment 1, further includes: a second gating link 2 parallel to the first gating link 1, the second gating link 2 is used to control the chip to power on; the second gating link 2 includes a second control signal input terminal, a second control signal output terminal and a plurality of second gating units 201, the power pins of the plurality of second gating units 201 are connected in parallel, the switch signals of the plurality of second gating units 201 are connected in series, and the switch signals of the second gating units 201 are connected to the second control signal input terminal and the second control signal output terminal.

[0048] The number of the first gating control units 101 in the first gating control link 1 is less than the number of the second gating control units 201 in the second gating control link 2 .

[0049] Specifically, in the present embodiment, two adjacent second gating units 201 are connected; the power input terminal of each second gating unit 201 (VDD connection port of the second gating unit 201) is connected to the normally open power line VDD, and the power output terminal of each second gating unit 201 (VDDS connection port of the second gating unit 201) is connected to the shutoff power line VDDS; each second gating unit 201 is connected to the normally open power line VDD and the shutoff power line VDDS so that the power pins of multiple second gating units 201 are connected in parallel.

[0050] The working principle of this embodiment is: the current change rate di / dt of the impact current in the pre-power-on process of the first gating link 1 is reduced by the delay unit 3 in the first gating link 1, so that the voltage difference on both sides of the first gating unit 101 in the first gating link 1 is relatively smaller, and then the current peak in the first gating link 1 is reduced. When the circuit of the chip is turned on, the first gating link 1 is turned on first, the power supply voltage is increased to more than 90% of the standard voltage, and then the second gating link 2 is turned on, so that the current peak does not appear when the second gating link 2 is turned on; when the circuit of the chip is turned off, the first gating link 1 is turned off first, the power supply voltage is reduced to less than 90% of the standard voltage, and then the second gating link 2 is turned off, so that the current peak does not appear when the second gating link 2 is turned off; avoid the second gating link 2 in the process of powering on or off too large a current peak, that is, too large a current change rate, affecting the power supply stability of the entire circuit system.

[0051] Example 3

[0052] This embodiment is a power gating circuit. On the basis of Embodiment 2, the first control signal input end of the first gating link 1 receives the first control signal to turn on the first gating unit 101; the second control signal input end of the second gating link 2 receives the second control signal to turn on the second gating unit 201; the time when the first gating link 1 receives the first control signal is earlier than the time when the second gating link 2 receives the second control signal. In this embodiment, the first gating link 1 is first opened, and after the voltage of the entire power supply system rises to a certain level (90% of the standard voltage), the second gating link 2 is opened to reduce the voltage difference when the second gating link 2 is opened, and further reduce the current peak of the second gating link 2, so that the power supply of the power supply system is more stable.

[0053] In this embodiment, the first control signal refers to a power signal input to the first gating link 1 ; the second control signal refers to a power signal input to the second gating link 2 .

[0054] Example 4

[0055] This embodiment is a power gating circuit, based on any one of the embodiments 1-3, in the first gating link 1, at least one delay unit 3 is arranged between the first control signal input terminal and the first gating unit 101 close to the first control signal input terminal. That is, the delay unit 3 is arranged close to the first control signal input terminal, and the delay unit 3 is connected in series with the first gating unit 101 and the first control signal input terminal; in actual work, placing the delay unit 3 between the first few first gating units 101 close to the input terminal of the first gating link 1 has a better effect on reducing the initial impact current change rate.

[0056] Example 5

[0057] This embodiment is a power gating circuit. On the basis of the embodiment 4, a plurality of delay units 3 are provided between two adjacent first gating units 101, and the plurality of delay units 3 are connected in series with each other. Specifically, the number of delay units 3 between two adjacent first gating units 101 may be 2, 3, 4 or more, depending on the delay requirement of the first gating link 1 and the length of the first gating link 1.

[0058] And / or there are multiple delay units 3 set between the first control signal input terminal and the first gating unit 101 close to the first control signal input terminal, and the multiple delay units 3 are connected in series with each other; specifically, the number of delay units 3 between the first control signal input terminal and the first gating unit 101 close to the first control signal input terminal can be 2, 3, 4 or more, depending on the delay requirement of the first gating link 1 and the length of the first gating link 1.

[0059] In this embodiment, the number of delay units 3 in the first gating link 1 is negatively correlated with the current change rate during the pre-power-on process of the first gating link 1. That is, the more the number of delay units 3, the smaller the current change rate during the pre-power-on process of the first gating link 1. Since the length of the first gating link 1 is limited, the number of delay units 3 in the first gating link 1 should be reasonable and applicable, that is, the number of delay units 3 in the first gating link 1 should meet the preset conditions.

[0060] Example 6

[0061] This embodiment is a power gating circuit, based on the embodiment 5, wherein the current change rate di / dt of the first gating link 1 is calculated as follows:

[0062]

[0063] In the formula, A0 refers to the fixed current reached when all the first gating units 101 in the first gating link 1 are fully turned on, unit: mA; m refers to the number of first gating units 101 in the first gating link 1, unit: piece; T1 refers to the delay time of one first gating unit 101 in the first gating link 1, unit: ns; n refers to the number of delay units 3 in the first gating link 1, unit: piece; T2 refers to the delay time of one delay unit 3 in the first gating link 1, unit: ns; the fixed current A0 reached when all the first gating units 101 in the first gating link 1 are fully turned on is positively correlated with the number of first gating units 101.

[0064] The preset condition for the number of the first gating units 101 refers to the number of the first gating units 101 corresponding to the current change rate of 20 mA / ns.

[0065] Example 7

[0066] This embodiment provides a chip, which is formed based on the power gating circuit of any one of Embodiments 1 to 6.

[0067] The above description is only the preferred embodiment of the utility model, and is not intended to limit the utility model. For those skilled in the art, the utility model can have various modifications and changes. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the utility model shall be included in the protection scope of the utility model.

Claims

1. A power gating circuit, characterized in that: include: A first gating link (1), wherein the first gating link (1) is used to control a chip to perform pre-power-on; the first gating link (1) comprises a first control signal input terminal and a plurality of first gating units (101), power pins of the plurality of first gating units (101) are connected in parallel, switch signals of the plurality of first gating units (101) are connected in series, and the switch signals of the first gating units (101) are connected to the first control signal input terminal, and at least one delay unit (3) is arranged between two adjacent first gating units (101), and the delay unit (3) is used to control the current change rate during the chip power-on process.

2. The power gating circuit according to claim 1, characterized in that: Also includes: A second gating link (2) parallel to the first gating link (1), the second gating link (2) being used to control the chip to perform power-on operation; the second gating link (2) comprising a second control signal input terminal and a plurality of second gating units (201), the power pins of the plurality of second gating units (201) being connected in parallel, the switch signals of the plurality of second gating units (201) being connected in series, and the switch signals of the second gating units (201) being connected to the second control signal input terminal; The number of first gating units (101) in the first gating link (1) is less than the number of second gating units (201) in the second gating link (2).

3. The power gating circuit according to claim 2, characterized in that: The first control signal input terminal of the first gating link (1) receives a first control signal to turn on the first gating unit (101); the second control signal input terminal of the second gating link (2) receives a second control signal to turn on the second gating unit (201); the first gating link (1) receives the first control signal earlier than the second gating link (2) receives the second control signal.

4. The power gating circuit according to claim 1, characterized in that: In the first gating link (1), at least one delay unit (3) is arranged between the first control signal input terminal and a first gating unit (101) close to the first control signal input terminal.

5. The power gating circuit according to claim 4, characterized in that: There are multiple delay units (3) arranged between two adjacent first gating units (101), and the multiple delay units (3) are connected in series; And / or, there are multiple delay units (3) arranged between the first control signal input terminal and the first gate control unit (101) close to the first control signal input terminal, and the multiple delay units (3) are connected in series.

6. The power gating circuit according to claim 1, characterized in that: In the first gating link (1), the number of the delay units (3) is negatively correlated with the current change rate during the pre-power-on process of the first gating link (1).

7. The power gating circuit according to claim 1, characterized in that: In the first gating link (1), the number of the first gating units (101) is negatively correlated with the current change rate during the pre-power-on process of the first gating link (1), and the number of the first gating units (101) meets a preset condition.

8. The power gating circuit according to claim 7, characterized in that: The calculation formula of the current change rate di / dt of the first gating link (1) is: In the formula, A0 refers to the fixed current reached when all the first gating units (101) in the first gating link (1) are fully turned on, unit: mA; m refers to the number of the first gating units (101) in the first gating link (1), unit: number; T1 refers to the delay time of a first gating unit (101) in the first gating link (1), unit: ns; n refers to the number of delay units (3) in the first gating link (1), unit: number; T2 refers to the delay time of a delay unit (3) in the first gating link (1), unit: ns; the fixed current A0 reached when all the first gating units (101) in the first gating link (1) are fully turned on is positively correlated with the number of the first gating units (101); The preset condition for the number of first gating units (101) refers to the number of first gating units (101) corresponding to a current change rate of 20 mA / ns.

9. The power gating circuit according to claim 1, characterized in that: The delay unit (3) is a buffer.

10. A chip, characterized in that: The chip is formed based on the power gating circuit according to any one of claims 1-9.

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