High-speed signal generation and acquisition module

Abstract

The utility model provides a high-speed signal generation and acquisition module. The high-speed signal generation and acquisition module comprises a power supply module, an FPGA module, a DSP module, an AD / DA module, a clock module, a communication module, a debugging interface and an FMC interface, the FPGA module, the DSP module, the AD / DA module and the clock module are in communication connection; the communication module, the FMC interface and the debugging interface are in external communication connection; the AD / DA module comprises two paths of AD acquisition chips and two paths of DA acquisition chips; the FPGA module is composed of three domestic FPGA chips which are respectively an FPGA (field programmable gate array) A1, an FPGA A2 and an FPGA A3, and the FPGA A1 is respectively connected with the FPGA A2 and the FPGA A3. According to the utility model, in a signal processing part, a localized FPGA and DSP architecture is adopted, and the operational capability of the DSP is applied, so that the real-time processing performance of the module on data is improved.

Description

Technical Field

[0001] The utility model belongs to the technical field of signal processing, and in particular relates to a high-speed signal generation and acquisition module. Background Art

[0002] High-speed acquisition and processing module cards have been widely used in various fields such as medical, military, and communications, mainly for the acquisition and processing of high-frequency signals. With the development of communication technology, the requirements for signal acquisition and processing are becoming higher and higher. Therefore, it is necessary to improve the real-time processing capabilities and high-speed data transmission capabilities of related modules.

[0003] Most of the existing signal processing modules use foreign chips to implement related functions. With the localization and upgrading of domestic chips, the requirements for domestic signal processing modules are increasing. There is an urgent need for a domestic signal processing module based on chip architectures such as FPGA and DSP. Utility Model Content

[0004] The technical problem to be solved by the utility model is that currently most signal processing modules are foreign chips to realize relevant functions, and it is not possible to use domestic FPGA, DSP and other chip architectures to design signal processing modules.

[0005] In order to solve the above technical problems, the technical solution provided by the utility model is: a high-speed signal generation and acquisition module, including a power module, an FPGA module, a DSP module, an AD / DA module, a clock module, a communication module, a debugging interface and an FMC interface; the FPGA module, the DSP module, the AD / DA module and the clock module are communicatively connected; the communication module, the FMC interface and the debugging interface are externally communicatively connected; the AD / DA module is a 2-channel AD acquisition chip and a 2-channel DA acquisition chip; the FPGA module is 3 domestically produced FPGA chips, namely FPGA1, FPGA2 and FPGA3, and FPGA1 is connected to FPGA2 and FPGA3 respectively.

[0006] As an improvement, the AD acquisition chip is a YA14D250 chip; the DA acquisition chip is a GMD9154 chip.

[0007] As an improvement, the FPGA1 and FPGA2 use JFM7VX690T80 chips, and the FPGA3 uses FMQL45T900 chip. The FPGA3 is connected to the FMC interface via LVDS, GPIO and RS422 interfaces.

[0008] As an improvement, the FPGA1 is connected to an AD / DA module for processing the AD acquisition signal and the DA acquisition signal to be transmitted.

[0009] As an improvement, the three FPGA chips are all configured with SPI FLASH chips as configuration chips, the configuration chips of FPGA1 and FGPA2 are EFM25QU256-E8; the configuration chip of FPGA3 is FFM25QL256; the three FPGA chips are also configured with DDR3 cache chips, and the cache chip is HXI15H4G160AF-13K.

[0010] As an improvement, the DSP module is a domestically produced DSP chip, and the DSP chip is FT-M6678N; the DSP module is connected to FPGA1 and FPGA2 through the SRIO interface; the DSP module is connected to FPGA3 through GPIO to achieve relevant data communication.

[0011] As an improvement, the communication module includes two types of optical fiber modules, which are directly connected to FPGA1 and are used to respectively realize data transmission of 10 Gigabit Ethernet protocol and data transmission of SRIO protocol.

[0012] As an improvement, the communication module further includes two 1000M Ethernet modules, which are respectively connected to the FPGA3 and the DSP module and are respectively used to access the FPGA3 and the DSP module through the external RJ45 ports.

[0013] The advantages of the utility model compared with the prior art are:

[0014] (1) Through the circuit configuration on the module, 2-channel AD acquisition and 2-channel DA output are realized. The channel sampling rate of AD can reach 250MHz, and the resolution is ≥14bit; the maximum sampling rate of DA is 2.4GSPS, and the resolution is ≥16bit; it can be optimized for direct frequency conversion transmission applications.

[0015] (2) In the signal processing part, the domestically produced FPGA and DSP architecture are used. While fully utilizing the rich interfaces and parallel data processing capabilities of FPGA, the computing power of DSP is also utilized to improve the module's real-time data processing performance.

[0016] (3) The main components in the design are all domestically produced components, which realizes the domestic design of the module and enhances the independent controllability of this type of circuit module. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Figure 1 The utility model is a circuit block diagram of a high-speed signal generation and acquisition module.

[0018] Figure 2 The utility model is a power rail block diagram of a high-speed signal generation and acquisition module.

[0019] Figure 3 The utility model is a clock tree block diagram of a high-speed signal generation and acquisition module. DETAILED DESCRIPTION

[0020] The following will be combined with the drawings in the embodiments of the utility model to clearly and completely describe the technical solutions in the embodiments of the utility model. Obviously, the described embodiments are only part of the embodiments of the utility model, not all of the embodiments. Based on the embodiments in the utility model, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the utility model.

[0021] Embodiment 1:

[0022] As the instruction manual Figure 1 As shown, a high-speed signal generation and acquisition module is characterized in that it includes a power module, an FPGA module, a DSP module, an AD / DA module, a clock module, a communication module, a debugging interface and an FMC interface, wherein the FPGA module is 3 domestically produced FPGA chips (respectively FPGA1, FPGA2, FPGA3), and 1 domestically produced DSP chip.

[0023] The FPGA chip cooperates with the peripheral clock module, configuration chip and cache chip, and high-speed and low-speed interfaces to form the FPGA module; the DSP chip also cooperates with its peripheral clock, configuration chip, cache chip, and high-speed and low-speed interfaces to form the DSP module, which together provide the domestic high-speed acquisition and processing module with signal acquisition and transmission platform, signal preprocessing and data exchange functions. The domestic high-speed acquisition and processing module realizes Gigabit network data communication through the RJ45 interface, and realizes high-speed data communication (including SRIO communication, LVDS communication) and low-speed data communication (including RS422 communication, GPIO communication) with the main control device through the FMC interface.

[0024] Specifically, FPGA1 is communicated with FPGA2, FPGA3 and DSP chip respectively; FPGA2 is communicated with FPGA3 and DSP chip; FPGA1 is communicated with ADC (AD acquisition chip is referred to as ADC below) and DAC (DA acquisition chip is referred to as DAC below).

[0025] FPGA1 communicates with ADC and DAC to realize high-speed signal acquisition and signal generation and transmission functions. FPGA1 communicates control commands with the ADC chip through the SPI interface and receives collected data through the LVDS interface; FPGA1 communicates control commands with the DAC chip through the SPI interface and sends signal data through the JESD204B interface.

[0026] FPGA1 and FPGA2 are connected through 10 low-speed interfaces GPIO and high-speed interfaces LVDS (48X) and SRIO interface (8X). FPGA1 and FPGA3 are connected through high-speed interfaces LVDS (4X) and SRIO interface (4X). FPGA1 and DSP are connected through high-speed interfaces EMIF32 and SRIO interface (4X).

[0027] When performing the signal acquisition function, FPGA1 configures the ADC by sending control commands, and receives and caches the data collected by the ADC for synchronous processing. According to the requirements of the received main control platform, the data can be sent to FPGA2 for data preprocessing through the high-speed interface with FPGA2, or sent to DSP for data processing through the high-speed interface with DSP.

[0028] FPGA2 can send the pre-processed data to DSP for data processing according to the requirements of the main control platform.

[0029] When performing the signal generation and transmission function, DSP communicates data with FPGA1 and FPGA2, and sends the calculated signal weights to FPGA1 and FPGA2 for them to generate related transmission data. FPGA1 receives the data generated by FPGA2 through the high-speed interface, and after synchronization, sends the data to the DAC chip to achieve the final signal generation.

[0030] FPGA3 is responsible for all hardware program burning and loading control of the module, as well as status monitoring of each module. The main control platform sends the burning files of two FPGAs and one DSP to FPGA3 through the Gigabit network to control the storage Flash on the burning module; after success, the board is reset and restarted.

[0031] The three FPGA chips are all equipped with SPI FLASH chips as configuration chips. The configuration chips of FPGA1 and FGPA2 are EFM25QU256-E8, and the configuration chip of FPGA3 is FFM25QL256. In addition, FPA1, FPGA2 and FPGA3 are all equipped with DDR3 cache chips, and the cache chip is HXI15H4G160AF-13K.

[0032] The DSP configuration chip is EFM25QU256-E8, and the DDR3 chip is HXI15H4G160AF-13K.

[0033] The ADC chip uses YA14D250, with a sampling rate of up to 250MSPS. This dual-channel ADC core adopts a multi-stage, differential pipeline architecture and integrates output error correction logic. Each ADC has a wide-bandwidth input to support various user-selectable input ranges; the integrated reference voltage source simplifies the design; the duty cycle stabilizer can be used to compensate for the fluctuation of the ADC clock duty cycle, giving the converter superior performance.

[0034] The DAC selected is the GMD9154, a quad-channel, 16-bit, high dynamic range digital-to-analog converter (DAC) that provides a maximum sampling rate of 2.4 GSPS and can generate multi-carriers up to the Nyquist frequency in baseband mode.

[0035] The utility model also provides an optical module, which is connected to the FPGA1 to realize the communication of 10 Gigabit network or SRIO and is used for the transmission of original data.

[0036] Two Gigabit network ports are connected to FPGA3 and DSP respectively. They are connected to DSP to load the database and connected to FPGA3 to load and update the program remotely.

[0037] The FMC interface is connected to FPGA2 and FPGA1 respectively to realize data exchange with the main control platform.

[0038] The maximum SRIO optical interface rate can reach 6.25Gbps; the maximum 10 Gigabit Ethernet rate can reach 10.3125Gbps; the maximum SRIO rate between FPGA and FPGA, FPGA and DSP can reach 5Gbps.

[0039] As the instruction manual Figure 2 As shown in the figure, it is a power rail diagram of the domestic high-speed acquisition and processing module provided by the utility model. Each chip in the domestic high-speed acquisition and processing module is powered accordingly as shown in the figure to ensure that the domestic high-speed acquisition and processing module can work normally.

[0040] As the instruction manual Figure 3 The figure shows a clock tree diagram of the domestic high-speed acquisition processing module provided by the utility model. The clock required by each chip in the domestic high-speed acquisition processing module is designed to ensure that the domestic high-speed acquisition processing module can obtain various clocks for normal operation.

[0041] The above describes the utility model and its implementation methods, which are not restrictive. The specific implementation method is only one of the implementation methods of the utility model, and the actual structure is not limited thereto. In short, if ordinary technicians in this field are inspired by it, without departing from the purpose of the invention of the utility model, they can design a structure and embodiment similar to the technical solution without creativity, which should belong to the protection scope of the utility model.

Claims

1. A high-speed signal generation and acquisition module, characterized in that: It includes a power module, an FPGA module, a DSP module, an AD / DA module, a clock module, a communication module, a debugging interface and an FMC interface; the FPGA module, the DSP module, the AD / DA module and the clock module are communicationally connected; the communication module, the FMC interface and the debugging interface are externally communicationally connected; the AD / DA module is a 2-channel AD acquisition chip and a 2-channel DA acquisition chip; the FPGA module is 3 domestically produced FPGA chips, namely FPGA1, FPGA2 and FPGA3, and FPGA1 is connected to FPGA2 and FPGA3 respectively.

2. A high-speed signal generation and acquisition module according to claim 1, characterized in that: The AD acquisition chip is a YA14D250 chip; the DA acquisition chip is a GMD9154 chip.

3. The high-speed signal generation and acquisition module according to claim 1, characterized in that: The FPGA1 and FPGA2 use JFM7VX690T80 chips, and the FPGA3 uses FMQL45T900 chip. The FPGA3 is connected to the FMC interface via LVDS, GPIO and RS422 interfaces.

4. The high-speed signal generation and acquisition module according to claim 1, characterized in that: The FPGA1 is connected to the AD / DA module and is used to process the AD acquisition signal and the DA acquisition signal to be transmitted.

5. The high-speed signal generation and acquisition module according to claim 1, characterized in that: The three FPGA chips are all configured with SPI FLASH chips as configuration chips, the configuration chips of FPGA1 and FGPA2 are EFM25QU256-E8; the configuration chip of FPGA3 is FFM25QL256; the three FPGA chips are also configured with DDR3 cache chips, and the cache chip is HXI15H4G160AF-13K.

6. The high-speed signal generation and acquisition module according to claim 1, characterized in that: The DSP module is a domestically produced DSP chip, and the DSP chip is FT-M6678N; the DSP module is connected to FPGA1 and FPGA2 through the SRIO interface; the DSP module is connected to FPGA3 through GPIO to achieve data communication.

7. The high-speed signal generation and acquisition module according to claim 1, characterized in that: The communication module includes two types of optical fiber modules, which are directly connected to FPGA1 and are used to respectively realize data transmission of 10 Gigabit Ethernet protocol and data transmission of SRIO protocol.

8. The high-speed signal generation and acquisition module according to claim 1, characterized in that: The communication module also includes two 1000M Ethernet modules, which are connected to the FPGA3 and the DSP module respectively, and are used to access the FPGA3 and the DSP module respectively through the external RJ45 ports.

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