Card reader circuit and card reader

Abstract

The utility model provides a card reader circuit and a card reader, and the card reader circuit comprises a frequency division carrier circuit which is used for improving the signal quality of a large-power carrier signal and outputting the carrier signal; the demodulation circuit is used for processing the high-power digital signal into a high-frequency signal and outputting a demodulation signal; the main control circuit is used for outputting a corresponding driving signal according to a carrier signal and a demodulation signal, the first signal end of the main control circuit is connected with the output end of the frequency division carrier circuit, and the second signal end of the main control circuit is connected with the output end of the demodulation circuit; and the driving circuit is used for driving an antenna, and the control end of the driving circuit is connected with the output end of the main control circuit. The card reader circuit provided by the utility model has a relatively long transmission distance so as to meet the card reading requirement of a relatively long distance.

Description

Technical Field

[0001] The present application relates to the technical field of card readers, and in particular to a card reader circuit and a card reader. Background Art

[0002] The card reader is generally composed of a radio frequency signal processing module, a baseband signal processing module, a control unit, and an interface module connected to external devices. The radio frequency signal processing module mainly implements three functions: first, it transmits radio frequency electromagnetic waves of sufficient power through the antenna to excite the electronic tag and provide it with energy; second, it modulates the transmission signal and then converts the modulated signal data into electromagnetic waves and transmits it to the tag; third, it receives and demodulates the radio frequency signal from the electronic tag. In order to process the data flow in both directions to and from the transponder, the radio frequency signal processing module has two different signal channels. The data transmitted to the electronic tag passes through the transmitting circuit branch, and the data from the electronic tag is processed through the receiving circuit branch.

[0003] Nowadays, the market application of animal ear tags has an increasing demand for card reading distance to expand application scenarios. However, the performance of existing products is not ideal. For example, the card reading distance of HDX is only about 20 cm, and the stable card reading distance of FDX-B is only about 25 cm. Under the existing technical conditions, due to the small power and magnetic field, it is impossible to meet the demand for longer distance card reading. Summary of the invention

[0004] The main purpose of the utility model is to provide a card reader circuit, aiming to solve the technical problem that the existing card reader circuit cannot meet the demand for longer distance card reading due to small power and magnetic field.

[0005] To achieve the above object, the utility model proposes a card reader circuit, comprising:

[0006] A frequency-dividing carrier circuit, wherein the frequency-dividing carrier circuit is used to improve the signal quality of a high-power carrier signal and output a carrier signal;

[0007] A demodulation circuit, the demodulation circuit is used to process a high-power digital signal into a high-frequency signal and output a demodulated signal;

[0008] A main control circuit, the main control circuit is used to output a corresponding driving signal according to the carrier signal and the demodulation signal, the first signal terminal of the main control circuit is connected to the output terminal of the frequency-divided carrier circuit, and the second signal terminal of the main control circuit is connected to the output terminal of the demodulation circuit;

[0009] A driving circuit, wherein the driving circuit is used to drive the antenna, and a control end of the driving circuit is connected to an output end of the main control circuit.

[0010] In one embodiment, the driving circuit comprises:

[0011] antenna;

[0012] A first chip, wherein an input terminal of the first chip is connected to an output terminal of the main control circuit;

[0013] A driving bridge, a control end of the driving bridge is connected to an output end of the first chip;

[0014] A filter circuit, wherein an input end of the filter circuit is connected to the first output end of the driving bridge, and an output end of the filter circuit is connected to the antenna.

[0015] In one embodiment, the drive axle comprises:

[0016] A first switch element, wherein a second control terminal of the first switch element is connected to a first output terminal of the first chip, a first resistor is connected between a first conduction terminal and a third conduction terminal of the first switch element, and a second conduction terminal of the first switch element is grounded;

[0017] a second switch element, wherein a second control end of the second switch element is connected to a second output end of the first chip, a second resistor is connected between the first conduction end and the third conduction end of the second switch element, and a second conduction end of the second switch element is grounded;

[0018] a third switch element, wherein a first control end of the third switch element is connected to a first conduction end of the first switch element, a second control end of the third switch element is connected to a third conduction end of the first switch element, a first conduction end of the third switch element is connected to a first end of the antenna, a third conduction end of the third switch element is connected to a first end of the antenna, and a second conduction end of the third switch element is grounded;

[0019] A fourth switch element, wherein the first control end of the fourth switch element is connected to the first conduction end of the second switch element, the second control end of the fourth switch element is connected to the third conduction end of the second switch element, the first conduction end of the fourth switch element is connected to the first end of the antenna, the third conduction end of the fourth switch element is connected to the input end of the filter circuit, and the second conduction end of the fourth switch element is grounded.

[0020] In one embodiment, the frequency division carrier circuit includes:

[0021] A first trigger circuit, wherein the first trigger circuit is used to trigger a clock signal;

[0022] An AND gate circuit, wherein the first input end of the AND gate circuit is connected to the output end of the first trigger circuit, the output end of the AND gate circuit is connected to the third signal end of the main control circuit, and the AND gate circuit is used to output a carrier signal according to a clock signal.

[0023] In one embodiment, the first trigger circuit includes:

[0024] A first trigger chip, wherein at least one capacitor is connected between a power supply and a ground of the first trigger chip;

[0025] A first crystal oscillator, wherein the first end of the first crystal oscillator is connected to the clock input end of the first trigger chip, a third resistor is connected between the second end of the first crystal oscillator and the clock generating end of the first trigger chip, and a fourth resistor is connected between the first end and the second end of the first crystal oscillator.

[0026] In one embodiment, the AND gate circuit includes:

[0027] A second chip, wherein the first input terminal of the second chip is connected to the first trigger terminal of the first trigger chip, the second input terminal of the second chip is connected to the fourth signal terminal of the main control circuit, and a fifth resistor is connected between the output terminal of the second chip and the first signal terminal of the main control circuit.

[0028] In one embodiment, the demodulation circuit includes:

[0029] A demodulation input circuit, wherein the fifth signal terminal of the main control circuit is connected to the input terminal of the demodulation input circuit, and the demodulation input circuit is used to process the high-power digital signal into a high-frequency signal and output a demodulated signal;

[0030] A demodulation output circuit, wherein the second signal terminal of the main control circuit is connected to the output terminal of the demodulation output circuit, the first terminal of the demodulation output circuit is connected to the output terminal of the demodulation input circuit, and the demodulation output circuit is used to output a demodulation signal;

[0031] A demodulation control circuit, wherein the input end of the demodulation control circuit is connected to the output end of the demodulation input circuit, and the output end of the demodulation control circuit is connected to the input end of the demodulation output circuit.

[0032] In one embodiment, the demodulation input circuit comprises:

[0033] A first inductor, wherein a first capacitor is connected between a first end of the first inductor and a fifth signal end of the main control circuit, and a bidirectional diode is connected between a second end of the first inductor and ground;

[0034] a sixth resistor, wherein a second capacitor is connected between a first end of the sixth resistor and a second end of the first inductor;

[0035] A seventh resistor, a third capacitor is connected between the first end of the seventh resistor and the second end of the sixth resistor, and the second end of the seventh resistor is connected to the input end of the demodulation control circuit.

[0036] In one embodiment, the demodulation output circuit includes:

[0037] a fourth capacitor, wherein a second inductor is connected between a first end of the fourth capacitor and an output end of the demodulation control circuit, a fifth capacitor is connected between a first end of the fourth capacitor and an output end of the demodulation control circuit, and a second end of the fourth capacitor is grounded;

[0038] a sixth capacitor, wherein an eighth resistor is connected between a first end of the sixth capacitor and an output end of the demodulation control circuit;

[0039] a fourth chip, wherein a ninth resistor is connected between the in-phase end of the fourth chip and the second end of the sixth capacitor, a twelfth resistor is connected between the in-phase end and the output end of the fourth chip, and a thirteenth resistor is connected between the output end of the fourth chip and the second signal end of the main control circuit;

[0040] a tenth resistor, wherein a second end of the tenth resistor is connected to an inverting end of the fourth chip, and an eleventh resistor is connected between a first end of the tenth resistor and a first end of the ninth resistor;

[0041] A fourteenth resistor, a second end of the fourteenth resistor is connected to the output end of the fourth chip.

[0042] To achieve the above object, the utility model also provides a card reader, including the card reader circuit as described above.

[0043] The embodiment of the utility model improves the signal quality of a high-power carrier signal through a frequency-dividing carrier circuit and outputs a carrier signal, processes the high-power digital signal into a high-frequency signal through a demodulation circuit, and outputs a demodulation signal, then connects the frequency-dividing carrier circuit and the demodulation circuit to a main control circuit respectively to receive the carrier signal and the demodulation signal, and finally connects the main control circuit to a driving circuit to drive an antenna, so that the card reader circuit has a longer transmission distance to meet the card reading requirements at a longer distance. BRIEF DESCRIPTION OF THE DRAWINGS

[0044] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative labor.

[0045] Figure 1 This is a structural schematic diagram of an embodiment of a card reader circuit of the utility model;

[0046] Figure 2 It is a structural schematic diagram of another embodiment of the card reader circuit of the utility model;

[0047] Figure 3 This is a structural schematic diagram of another embodiment of the card reader circuit of the utility model;

[0048] Figure 4 This is a structural schematic diagram of another embodiment of the card reader circuit of the utility model;

[0049] Figure 5 for Figure 3 Schematic diagram in ;

[0050] Figure 6 for Figure 2 Schematic diagram in ;

[0051] Figure 7 for Figure 4 Schematic diagram in .

[0052] Description of Figure Numbers:

[0053]

[0054] The realization of the purpose, functional features and advantages of the utility model will be further explained in conjunction with embodiments and with reference to the accompanying drawings. DETAILED DESCRIPTION

[0055] The following will be combined with the drawings in the embodiments of the utility model to clearly and completely describe the technical solutions in the embodiments of the utility model. Obviously, the described embodiments are only part of the embodiments of the utility model, not all of the embodiments. Based on the embodiments of the utility model, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the utility model.

[0056] It should be noted that all directional indications (such as up, down, left, right, front, back...) in the embodiments of the present invention are only used to explain the relative position relationship, movement status, etc. between the various components under a certain specific posture (as shown in the accompanying drawings). If the specific posture changes, the directional indication will also change accordingly.

[0057] In addition, the descriptions of "first", "second", etc. in the present utility model are only used for descriptive purposes and cannot be understood as indicating or implying their relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first" and "second" may explicitly or implicitly include at least one of the features. In addition, the technical solutions between the various embodiments can be combined with each other, but they must be based on the ability of ordinary technicians in the field to implement them. When the combination of technical solutions is contradictory or cannot be implemented, it should be deemed that such a combination of technical solutions does not exist and is not within the scope of protection required by the present utility model.

[0058] Please refer to Figure 1 As shown, in one embodiment of the present utility model, the card reader circuit includes a frequency division carrier circuit 100, a demodulation circuit 200, a main control circuit 300 and a driving circuit 400, wherein:

[0059] The frequency division carrier circuit 100 is used to improve the signal quality of the high-power carrier signal and output the carrier signal; the demodulation circuit 200 is used to process the high-power digital signal into a high-frequency signal and output the demodulation signal; the main control circuit 300 is used to output the corresponding driving signal according to the carrier signal and the demodulation signal, the first signal end of the main control circuit 300 is connected to the output end of the frequency division carrier circuit 100, and the second signal end of the main control circuit 300 is connected to the output end of the demodulation circuit 200; the driving circuit 400 is used to drive the antenna 440, and the control end of the driving circuit 400 is connected to the output end of the main control circuit 300. The driving circuit 400 is a differential circuit, and the driving circuit 400 is used to drive the antenna 440.

[0060] In this embodiment, the frequency division carrier circuit 100 adopts a high-precision, low-noise design to improve the signal quality of the high-power carrier signal. By performing frequency division processing on the carrier signal, the harmonic distortion of the signal can be reduced, thereby improving the signal quality. At the output end of the frequency division carrier circuit 100, we can also add a filter module to further reduce noise and interference and ensure the stability of the output carrier signal.

[0061] In this embodiment, the demodulation circuit 200 is responsible for processing the high-power digital signal into a high-frequency signal. By demodulating the digital signal, the original signal can be converted into a high-frequency signal, thereby reducing the loss of the signal during transmission. In addition, the demodulation circuit 200 can also effectively eliminate inter-symbol interference and improve the transmission reliability of the signal.

[0062] In this embodiment, the main control circuit 300 is the core part of the whole system, which outputs the corresponding driving signal according to the carrier signal and the demodulation signal. The first signal terminal of the main control circuit 300 is connected to the output terminal of the frequency division carrier circuit 100, and the second signal terminal is connected to the output terminal of the demodulation circuit 200, so as to realize the real-time monitoring and control of the signal.

[0063] In this embodiment, the driving circuit 400 is responsible for driving the antenna 440 to convert the electrical signal into a wireless electromagnetic wave. In this embodiment, the driving circuit 400 adopts a differential circuit design, which can effectively suppress common mode interference and improve the anti-interference ability of the signal. At the same time, the driving circuit 400 can also adjust the transmission power and frequency of the antenna 440 according to the driving signal output by the main control circuit 300 to achieve long-distance transmission of the signal.

[0064] The working principle of the whole system is as follows: first, the frequency-divided carrier circuit 100 outputs a high-quality carrier signal; then, the demodulation circuit 200 processes the digital signal into a high-frequency signal; then, the main control circuit 300 outputs a corresponding drive signal according to the carrier signal and the demodulation signal; finally, the drive circuit 400 drives the antenna 440 to convert the electrical signal into a radio electromagnetic wave to achieve long-distance transmission of the signal.

[0065] Through the above technical solutions, this system can not only improve the signal quality of high-power carrier signals, but also effectively reduce the loss and interference of digital signals during transmission. In addition, the system adopts differential circuit design to further improve the anti-interference ability of the signal. Thus, it provides an efficient and stable high-power wireless transmission solution with broad application prospects.

[0066] The technical solution of the utility model improves the signal quality of a high-power carrier signal through a frequency-dividing carrier circuit 100 and outputs a carrier signal, processes a high-power digital signal into a high-frequency signal through a demodulation circuit 200, and outputs a demodulation signal, then connects the frequency-dividing carrier circuit 100 and the demodulation circuit 200 to a main control circuit 300 respectively to receive the carrier signal and the demodulation signal, and finally connects to a driving circuit 400 through the main control circuit 300 to drive an antenna 440, so that the card reader circuit has a longer transmission distance to meet the card reading requirements at a longer distance.

[0067] Combined with reference Figure 2 and Figure 6 As shown, further, another embodiment of the utility model provides a card reader circuit, based on the above Figure 1 In the embodiment shown, the driving circuit 400 includes a first chip 410, a driving bridge 420, a filtering circuit 430 and an antenna 440, wherein:

[0068] The input end of the first chip 410 is connected to the output end of the main control circuit 300; the control end of the driving bridge 420 is connected to the output end of the first chip 410; the input end of the filter circuit 430 is connected to the first output end of the driving bridge 420, and the output end of the filter circuit 430 is connected to the antenna 440. The first chip is U7, and the specific model is TC4428AEOA713.

[0069] In this embodiment, the first chip 410 is used to drive the driving bridge according to the driving signal. The driving bridge 420 controls the working state of the filtering circuit 430 according to the output signal of the first chip 410, so as to adjust the filtered signal output to the antenna 440. The filtering circuit 430 is used to filter the signal from the driving bridge 420, remove the clutter in the signal, and improve the purity of the signal. The filtered signal will be sent out through the antenna 440 to realize communication with external devices. In this embodiment, the specific model of the first chip U7 is TC4428AEOA713, which has the characteristics of high performance and low power consumption and can meet the requirements of this system.

[0070] The system architecture design of this embodiment makes the workflow of the entire communication system clear and concise, and reduces the complexity of the system. At the same time, the use of a high-performance first chip 410 and a filter circuit 430 ensures the efficient operation of the system and the stability of the signal. In addition, this embodiment can also be adjusted according to actual needs. For example, other types of first chips and filter circuits can be used to meet application requirements in different scenarios. At the same time, the drive bridge 420 can also be optimized to improve the overall performance of the system. Specifically, the present application mainly uses a circuit structure combined with existing software technology to control the antenna circuit, and achieves a stable and reliable communication effect by reasonably configuring each component.

[0071] In this embodiment, the driving bridge 420 includes a first switch element U3, a second switch element U5, a third switch element U4 and a fourth switch element U6, wherein:

[0072] The second control end of the first switch element U3 is connected to the first output end of the first chip 410, a first resistor R2 is connected between the first conduction end and the third conduction end of the first switch element U3, and the second conduction end of the first switch element U3 is grounded; the second control end of the second switch element U5 is connected to the second output end of the first chip 410, a second resistor R5 is connected between the first conduction end and the third conduction end of the second switch element U5, and the second conduction end of the second switch element U5 is grounded; the first control end of the third switch element U4 is connected to the first conduction end of the first switch element U3, and the second control end of the third switch element U4 is connected to the third conduction end of the first switch element U3. The first conduction end of the third switch element U4 is connected to the first end of the antenna 440, the third conduction end of the third switch element U4 is connected to the first end of the antenna 440, and the second conduction end of the third switch element U4 is grounded; the first control end of the fourth switch element U6 is connected to the first conduction end of the second switch element U5, the second control end of the fourth switch element U6 is connected to the third conduction end of the second switch element U5, the first conduction end of the fourth switch element U6 is connected to the first end of the antenna 440, the third conduction end of the fourth switch element U6 is connected to the input end of the filter circuit 430, and the second conduction end of the fourth switch element U6 is grounded.

[0073] In this embodiment, the input signal can be filtered by the filter circuit 430 to ensure the signal quality of the card reader. The antenna 440 also includes a second end, which is connected to the third conductive end of the third switch element U4. In this way, the connection control of the antenna 440 can be achieved by controlling the switching state of the third switch element U4, thereby achieving wireless communication control of the card reader.

[0074] In this embodiment, the signal processing and wireless communication control of the card reader circuit can be realized through the above circuit design and switch control. In addition, the different working modes of the card reader circuit can be controlled by adjusting the switch states of the first switch element U3, the second switch element U5, the third switch element U4 and the fourth switch element U6 to meet the needs of various usage scenarios with high performance and stability.

[0075] In addition, this embodiment also adopts an optimized circuit design to improve the overall performance of the system. Specifically, the first chip 410 and the filter circuit 430 in this embodiment use high-performance devices to ensure the efficient operation of the system and the stability of the signal. At the same time, by reasonably configuring each component, the workflow of the entire communication system is made clearer and more concise, reducing the complexity of the system.

[0076] In this embodiment, the connection between the first chip 410 and the filter circuit 430 enables the system to automatically adjust the working state according to the driving signal, further improving the adaptability of the system. In addition, by using the first chip U7 (specific model TC4428AEOA713), precise control of the drive bridge 420 can be achieved, thereby ensuring the filtering processing effect of the signal and improving the communication quality.

[0077] The design of the antenna 440 of this embodiment can achieve a stable wireless communication effect. By controlling the switching states of the first switch element U3, the second switch element U5, the third switch element U4 and the fourth switch element U6, the connection control of the antenna 440 can be flexibly achieved to meet the application requirements in different scenarios. At the same time, by optimizing the circuit design of the drive bridge 420, the performance and stability of the system can be further improved.

[0078] In summary, this embodiment provides a communication system based on the first chip 410 and the filter circuit 430, which realizes the signal processing of the card reader circuit and the control of wireless communication through reasonable circuit design and switch control. This system has the characteristics of high performance, low power consumption, good stability, etc., and can be widely used in various communication scenarios.

[0079] In addition, this embodiment can be further optimized, for example, the circuit parameters can be adjusted according to actual needs to achieve better performance; other components can also be optimized to improve the overall performance of the system. In short, this embodiment provides a design idea for a communication system, which can be adjusted and optimized according to actual needs and has high practical value.

[0080] By appropriately modifying this embodiment, the needs of different application scenarios can be met. This embodiment is only exemplary and is not limited to specific hardware and software configurations. On the contrary, those of ordinary skill in the art can make various appropriate modifications and adjustments to it without affecting system performance. Therefore, this embodiment should be understood to include but not limited to the specific implementation methods described.

[0081] Combined with reference Figure 3 and Figure 5 As shown, further, another embodiment of the utility model provides a card reader circuit, based on the above Figure 1 In the embodiment shown, the frequency-divided carrier circuit 100 includes a first trigger circuit 110 and an AND gate circuit 120, wherein:

[0082] The first trigger circuit 110 is used to trigger the clock signal; the first input end of the AND gate circuit 120 is connected to the output end of the first trigger circuit 110, the output end of the AND gate circuit 120 is connected to the third signal end of the main control circuit 300, and the AND gate circuit 120 is used to output a carrier signal according to the clock signal.

[0083] Please refer to Figure 5 As shown, in this embodiment, the first trigger circuit 110 includes a first trigger chip U11 and a first crystal oscillator Y1, wherein:

[0084] At least one capacitor is connected between the power supply and ground of the first trigger chip U11; the first end of the first crystal oscillator Y1 is connected to the clock input end of the first trigger chip U11, a third resistor R28 is connected between the second end of the first crystal oscillator Y1 and the clock generation end of the first trigger chip U11, and a fourth resistor R29 is connected between the first end and the second end of the first crystal oscillator Y1.

[0085] Please refer to Figure 5 As shown, in this embodiment, the AND gate circuit 120 includes a second chip U13, wherein:

[0086] The first input terminal of the second chip U13 is connected to the first trigger terminal of the first trigger chip U11, the second input terminal of the second chip U13 is connected to the fourth signal terminal of the main control circuit 300, and a fifth resistor R31 is connected between the output terminal of the second chip U13 and the first signal terminal of the main control circuit 300. Specifically, a current-limiting resistor R30 is connected between the first input terminal of the second chip U13 and the first trigger terminal of the first chip 410.

[0087] In this embodiment, the trigger signal is outputted by the first trigger chip U11, and the carrier signal is outputted by the AND gate circuit 120 according to the enable signal outputted by the main control circuit 300. Such a design makes the whole system work more stable and reliable, and improves the response speed and accuracy of the system.

[0088] Combined with reference Figure 4 As shown, further, the utility model also provides a card reader circuit according to another embodiment. Figure 1 In the embodiment shown, the demodulation circuit 200 includes a demodulation input circuit 210, a demodulation control circuit 220, and a demodulation output circuit 230, wherein:

[0089] The fifth signal terminal of the main control circuit 300 is connected to the input terminal of the demodulation input circuit 210, and the demodulation input circuit 210 is used to process the high-power digital signal into a high-frequency signal and output a demodulated signal; the input terminal of the demodulation control circuit 220 is connected to the output terminal of the demodulation input circuit 210, and the output terminal of the demodulation control circuit 220 is connected to the input terminal of the demodulation output circuit 230; the second signal terminal of the main control circuit 300 is connected to the output terminal of the demodulation output circuit 230, and the first terminal of the demodulation output circuit 230 is connected to the output terminal of the demodulation input circuit 210, and the demodulation output circuit 230 is used to output a demodulated signal.

[0090] Please refer to Figure 7 As shown, in this embodiment, the demodulation input circuit 210 includes a first inductor L1, a sixth resistor R44 and a seventh resistor R46, wherein:

[0091] A first capacitor C51 is connected between the first end of the first inductor L1 and the fifth signal end of the main control circuit 300, and a bidirectional diode D12 is connected between the second end of the first inductor L1 and the ground; a second capacitor is connected between the first end of the sixth resistor R44 and the second end of the first inductor L1; a third capacitor C52 is connected between the first end of the seventh resistor R46 and the second end of the sixth resistor R44, and the second end of the seventh resistor R46 is connected to the input end of the demodulation control circuit 220.

[0092] Please refer to Figure 7 As shown, in this embodiment, the demodulation output circuit 230 includes a fourth capacitor C50, a sixth capacitor C69, a fourth chip U12, a tenth resistor R49 and a fourteenth resistor, wherein:

[0093] A second inductor L4 is connected between the first end of the fourth capacitor C50 and the output end of the demodulation control circuit 220, a fifth capacitor C49 is connected between the first end of the fourth capacitor C50 and the output end of the demodulation control circuit 220, and the second end of the fourth capacitor C50 is grounded; an eighth resistor R52 is connected between the first end of the sixth capacitor C69 and the output end of the demodulation control circuit 220; a ninth resistor R53 is connected between the in-phase end of the fourth chip U12 and the second end of the sixth capacitor C69, a twelfth resistor R55 is connected between the in-phase end and the output end of the fourth chip U12, and a thirteenth resistor R54 is connected between the output end of the fourth chip U12 and the second signal end of the main control circuit 300; the second end of the tenth resistor R49 is connected to the inverting end of the fourth chip U12, and an eleventh resistor R51 is connected between the first end of the tenth resistor R49 and the first end of the ninth resistor R53; the second end of the fourteenth resistor R54 is connected to the output end of the fourth chip U12.

[0094] In this embodiment, by processing a high-power digital signal into a high-frequency signal and outputting a demodulated signal, the demodulation of the digital signal is achieved. The demodulation circuit has the advantages of simple structure, stable performance, high reliability, etc. Through the design of the above demodulation circuit, the present embodiment can efficiently demodulate a high-power digital signal into a high-frequency signal. The demodulation circuit uses a small number of components, such as inductors, capacitors, resistors, and chips, etc., to achieve demodulation of the digital signal, reducing the complexity of the entire system. The demodulation circuit 200 of this embodiment has high reliability, adaptability, and high-frequency performance while ensuring stable performance.

[0095] The utility model also proposes a card reader, which includes a card reader circuit. The specific structure of the card reader circuit refers to the above embodiments. Since the card reader adopts all the technical solutions of all the above embodiments, it at least has all the beneficial effects brought by the technical solutions of the above embodiments, which will not be described one by one here.

[0096] The above is an implementation method provided in combination with specific content, and it is not considered that the specific implementation of this application is limited to these descriptions. Any similarity or similarity with the method, structure, etc. of this application, or any technical deduction or replacement made on the premise of the concept of this application, shall be deemed to be within the scope of protection of this application.

Claims

1. A card reader circuit, characterized in that: include: A frequency-dividing carrier circuit, wherein the frequency-dividing carrier circuit is used to improve the signal quality of a high-power carrier signal and output a carrier signal; A demodulation circuit, the demodulation circuit is used to process a high-power digital signal into a high-frequency signal and output a demodulated signal; A main control circuit, the main control circuit is used to output a corresponding driving signal according to the carrier signal and the demodulation signal, the first signal terminal of the main control circuit is connected to the output terminal of the frequency-divided carrier circuit, and the second signal terminal of the main control circuit is connected to the output terminal of the demodulation circuit; A driving circuit, wherein the driving circuit is used to drive the antenna, and a control end of the driving circuit is connected to an output end of the main control circuit.

2. The card reader circuit according to claim 1, characterized in that: The driving circuit comprises: antenna; A first chip, wherein an input terminal of the first chip is connected to an output terminal of the main control circuit; A driving bridge, a control end of the driving bridge is connected to an output end of the first chip; A filter circuit, wherein an input end of the filter circuit is connected to the first output end of the driving bridge, and an output end of the filter circuit is connected to the second end of the antenna.

3. The card reader circuit according to claim 2, characterized in that: The drive axle comprises: A first switch element, wherein a second control terminal of the first switch element is connected to a first output terminal of the first chip, a first resistor is connected between a first conduction terminal and a third conduction terminal of the first switch element, and a second conduction terminal of the first switch element is grounded; a second switch element, wherein a second control end of the second switch element is connected to a second output end of the first chip, a second resistor is connected between the first conduction end and the third conduction end of the second switch element, and a second conduction end of the second switch element is grounded; a third switch element, wherein a first control end of the third switch element is connected to a first conduction end of the first switch element, a second control end of the third switch element is connected to a third conduction end of the first switch element, a first conduction end of the third switch element is connected to a first end of the antenna, a third conduction end of the third switch element is connected to a first end of the antenna, and a second conduction end of the third switch element is grounded; A fourth switch element, wherein the first control end of the fourth switch element is connected to the first conduction end of the second switch element, the second control end of the fourth switch element is connected to the third conduction end of the second switch element, the first conduction end of the fourth switch element is connected to the first end of the antenna, the third conduction end of the fourth switch element is connected to the input end of the filter circuit, and the second conduction end of the fourth switch element is grounded.

4. The card reader circuit according to claim 3, characterized in that: The frequency division carrier circuit comprises: A first trigger circuit, wherein the first trigger circuit is used to trigger a clock signal; An AND gate circuit, wherein the first input end of the AND gate circuit is connected to the output end of the first trigger circuit, the output end of the AND gate circuit is connected to the third signal end of the main control circuit, and the AND gate circuit is used to output a carrier signal according to a clock signal.

5. The card reader circuit according to claim 4, characterized in that: The first trigger circuit comprises: A first trigger chip, wherein at least one capacitor is connected between a power supply and a ground of the first trigger chip; A first crystal oscillator, wherein the first end of the first crystal oscillator is connected to the clock input end of the first trigger chip, a third resistor is connected between the second end of the first crystal oscillator and the clock generating end of the first chip, and a fourth resistor is connected between the first end and the second end of the first crystal oscillator.

6. The card reader circuit according to claim 5, characterized in that: The AND gate circuit comprises: A second chip, wherein the first input terminal of the second chip is connected to the first trigger terminal of the first trigger chip, the second input terminal of the second chip is connected to the fourth signal terminal of the main control circuit, and a fifth resistor is connected between the output terminal of the second chip and the first signal terminal of the main control circuit.

7. The card reader circuit according to claim 1, characterized in that: The demodulation circuit includes: A demodulation input circuit, wherein the fifth signal terminal of the main control circuit is connected to the input terminal of the demodulation input circuit, and the demodulation input circuit is used to process the high-power digital signal into a high-frequency signal and output a demodulated signal; A demodulation output circuit, wherein the second signal terminal of the main control circuit is connected to the output terminal of the demodulation output circuit, the first terminal of the demodulation output circuit is connected to the output terminal of the demodulation input circuit, and the demodulation output circuit is used to output a demodulation signal; A demodulation control circuit, wherein the input end of the demodulation control circuit is connected to the output end of the demodulation input circuit, and the output end of the demodulation control circuit is connected to the input end of the demodulation output circuit.

8. The card reader circuit according to claim 7, characterized in that: The demodulation input circuit comprises: a first inductor, wherein a first capacitor is connected between a first end of the first inductor and a fifth signal end of the main control circuit, and a bidirectional diode is connected between a second end of the first inductor and ground; a sixth resistor, wherein a second capacitor is connected between a first end of the sixth resistor and a second end of the first inductor; A seventh resistor, a third capacitor is connected between a first end of the seventh resistor and a second end of the sixth resistor, and a second end of the seventh resistor is connected to an input end of the demodulation control circuit.

9. The card reader circuit according to claim 8, characterized in that: The demodulation output circuit comprises: a fourth capacitor, wherein a second inductor is connected between a first end of the fourth capacitor and an output end of the demodulation control circuit, a fifth capacitor is connected between a first end of the fourth capacitor and an output end of the demodulation control circuit, and a second end of the fourth capacitor is grounded; a sixth capacitor, wherein an eighth resistor is connected between a first end of the sixth capacitor and an output end of the demodulation control circuit; a fourth chip, wherein a ninth resistor is connected between the in-phase end of the fourth chip and the second end of the sixth capacitor, a twelfth resistor is connected between the in-phase end and the output end of the fourth chip, and a thirteenth resistor is connected between the output end of the fourth chip and the second signal end of the main control circuit; a tenth resistor, wherein a second end of the tenth resistor is connected to an inverting end of the fourth chip, and an eleventh resistor is connected between a first end of the tenth resistor and a first end of the ninth resistor; A fourteenth resistor, a second end of the fourteenth resistor is connected to the output end of the fourth chip.

10. A card reader, characterized in that: The method comprises a card reader circuit as claimed in any one of claims 1 to 9.

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