Ghosting eliminating circuit and display device
By designing the afterimage cancellation circuit, using the switch tube and control unit to manage the input voltage and deficit control signal, the problem of the afterimage and XON functions incorrectly turned on when the TFT-LCD is turned off, and a stable power-down state and system stability improvement is achieved .
Patent Information
- Application Number
- CN202420548694.1
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-03-20
- Publication Date
- 2025-02-25
- Estimated Expiration
- 2034-03-20
AI Technical Summary
When the TFT-LCD is turned off, the afterimage phenomenon caused by charge accumulation, and the existing XON function is easily turned on by mistake when the input voltage is unstable, resulting in black screen and abnormal display.
A afterimage cancellation circuit is designed, including a first switch tube and a control unit, which turns on/off the input voltage by receiving the decompression control signal and forms a drain path of the return current to maintain the input voltage and decompression control signal at the Stable power-down state when shutting down.
It effectively prevents the wrong triggering of the XON function, improves the shutdown afterimage problem, and improves the stability of the system. The components on the power chip are not increased, and the cost is not increased.
Smart Images
Figure CN222530009U_ABST
Abstract
Description
Technical Field
[0001] The utility model relates to the technical field of display, and in particular to an afterimage elimination circuit and a display device. Background Art
[0002] Thin-film transistor liquid crystal displays (TFT-LCDs) have the advantages of small size, low power consumption, and no radiation, and have been widely used in various display terminals, such as mobile phones, tablets, and televisions.
[0003] When the TFT-LCD is in the normal lighting state, each pixel inside its display panel is filled with a certain amount of charge. At the moment of shutdown, as the accumulated charge inside the display panel slowly disappears, the human eye will observe the afterimage phenomenon. In order to solve the problem of afterimage when the TFT-LCD is turned off, the TFT-LCD usually uses the XON function (often called the DISCH function in the array substrate gate drive (GOA) product). That is, when the input voltage VIN of the power chip (Power IC), that is, the normal working voltage, is detected to be shut down to a certain value, the XON function is turned on and the XON signal is output to the gate drive circuit module (such as the GOA circuit module), so that all signals of the gate drive circuit module (for example, STV, CLK, GCL, VGL signals of GOA, etc.) are pulled to a high level, and all TFTs inside the display panel are turned on at the same time, so that the charge in the pixels inside the display panel is neutralized, eliminating the afterimage phenomenon when the power is turned off.
[0004] However, when using the XON function, if the input voltage VIN of the Power IC is not clean enough and has ripples, or if the current of a high PPI or high-load product is too large under a heavy-load screen, the input voltage VIN of the Power IC will be reduced. When it drops to the threshold voltage that can enable the XON function, the XON function will be mistakenly enabled, and all signals of the gate drive circuit module will be pulled high, resulting in a black screen for the TFT-LCD. In addition, due to the mistaken activation of the XON function, all TFTs will be turned on at the same time, which will increase the workload of the entire display panel (increase the current), increase the load of the working voltage, and cause overcurrent protection of some working voltages, which may easily lead to adverse phenomena such as liquid crystal polarization and display abnormality. Utility Model Content
[0005] In order to solve the above technical problems, the utility model provides an afterimage elimination circuit and a display device, which can improve the XON false triggering phenomenon when shutting down, and effectively improve the shutdown afterimage problem.
[0006] On the one hand, the utility model provides a residual image elimination circuit, which includes:
[0007] The first switch tube is connected between the input voltage port and the main circuit of the power module, and receives a shadow elimination control signal to open / close the path for the input voltage to access the main circuit;
[0008] A first control unit is connected to at least one branch connected to the input voltage, receives a gate start voltage to control the first control unit to connect to the main circuit of the power module, and forms a first discharge path for the return current between the analog power input port and the input voltage port;
[0009] And / or a second control unit, connected between the analog power input port and the main circuit of the power module, receives the gate start voltage to control the second control unit to connect to the main circuit of the power module, and forms a second discharge path for the return current between the analog power input port and the input voltage port to maintain the input voltage and the shadow elimination control signal in a stable power-off state when shutting down.
[0010] In some embodiments, the first control unit comprises:
[0011] A second switch tube and a first capacitor network, wherein the first end of the second switch tube is connected to the branch where the input voltage is located, the control end is connected to the gate turn-on voltage, and the first capacitor network is connected between the second end of the second switch tube and the ground, forming a first discharge path for the return current during the conduction phase of the second switch tube.
[0012] In some embodiments, the first capacitor network comprises:
[0013] A plurality of first capacitors are connected in parallel between the second end of the second switch tube and the ground.
[0014] In some embodiments, the second control unit comprises:
[0015] A third switch tube and a second capacitor network, wherein the first end of the third switch tube is connected to the branch where the analog power supply is located, the control end is connected to the gate turn-on voltage, and the second capacitor network is connected between the second end of the third switch tube and the ground, forming a second discharge path for the return current during the conduction phase of the third switch tube.
[0016] In some embodiments, the second capacitor network includes:
[0017] A plurality of second capacitors are connected in parallel between the second end of the third switch tube and the ground.
[0018] In some embodiments, the first switch tube is turned on when the display device is turned on, and is turned off when the display device is turned off.
[0019] In some embodiments, any one of the first switch tube, the second switch tube and the third switch tube is any one selected from a metal oxide semiconductor field effect transistor, a back cathode field effect transistor, and a bipolar transistor.
[0020] In some embodiments, any one of the first switch tube, the second switch tube and the third switch tube is an N-type metal oxide semiconductor field effect transistor.
[0021] In some embodiments, a parasitic diode in a switch tube adjacent to an analog power input port in a main circuit of the power module is arranged with a side close to the analog power input port as a cathode.
[0022] On the other hand, the utility model provides a display device, comprising:
[0023] Display array;
[0024] A gate driving circuit, wherein the gate driving circuit provides a gate driving signal to the display array through an output terminal thereof;
[0025] A source driving circuit, wherein the source driving circuit provides a source data signal to the display array through an output terminal thereof;
[0026] A timing control circuit, wherein the timing control circuit provides timing signals to the gate driving circuit and the source driving circuit respectively through its output terminals;
[0027] As described above, the afterimage elimination circuit cuts off the connection path of the input voltage when the display device is turned off, and forms a discharge path for the return current between the analog power input port and the input voltage port to maintain the input voltage and the afterimage elimination control signal in a stable power-off state when the display device is turned off.
[0028] The beneficial effects of the utility model are as follows: the afterimage elimination circuit and display device provided by the utility model, wherein the afterimage elimination circuit comprises: a first switch tube, connected between the input voltage port and the main circuit of the power module, receiving the elimination control signal to open / close the path of the input voltage accessing the main circuit; a first control unit, connected to at least one branch connected to the input voltage, receiving the gate start voltage to control the first control unit to access the main circuit of the power module, forming a first discharge path of the return current between the analog power input port and the input voltage port; and / or a second control unit, connected between the analog power input port and the main circuit of the power module, receiving the gate start voltage to control the second control unit to access the main circuit of the power module, forming a second discharge path of the return current between the analog power input port and the input voltage port, so as to maintain the input voltage and the elimination control signal in a stable power-off state when shutting down. Thus, by adding a load to the analog power branch and adding a capacitor network between the input voltage branches to form a return path, the return current when the analog power supply AVDD is shut down is effectively absorbed, the false triggering of XON is prevented, and the shutdown afterimage problem is effectively improved.
[0029] In addition, by forcing the parasitic diode of the switch tube on the branch connected to the analog power input port inside the power chip to face right, the reflux current is prevented from returning to the main circuit after power failure, effectively improving the rebound of the input voltage and XON after shutdown, thereby improving the stability of the system. At the same time, no additional components are added to the power chip, and the cost is not increased. BRIEF DESCRIPTION OF THE DRAWINGS
[0030] The above and other objects, features and advantages of the present invention will become more apparent through the following description of the embodiments of the present invention with reference to the accompanying drawings.
[0031] Figure 1 A schematic diagram showing the structure of a display device in the prior art is shown;
[0032] Figure 2 Show Figure 1 A timing diagram showing some signals when the display device is turned off;
[0033] Figure 3 A schematic diagram showing the structure of an afterimage elimination circuit provided by an embodiment of the present disclosure is shown;
[0034] Figure 4 Show Figure 3 A timing diagram of some signals of the afterimage elimination circuit when the display device is turned off;
[0035] Figure 5a and Figure 5b Schematic diagrams of circuit principles of the AVDD branch in the prior art and the embodiment of the present disclosure when the power is turned off are respectively shown;
[0036] Figure 6a and Figure 6b Shown separately Figure 5a and Figure 5b Timing diagram of the input voltage VIN in the circuit during shutdown. DETAILED DESCRIPTION
[0037] In order to facilitate the understanding of the present invention, the present invention will be described more comprehensively with reference to the relevant drawings. The drawings provide preferred embodiments of the present invention. However, the present invention can be implemented in different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the understanding of the disclosure of the present invention more thorough and comprehensive.
[0038] It should be understood that in the following description, a "circuit" may include a single or multiple combined hardware circuits, programmable circuits, state machine circuits, and / or elements capable of storing instructions executed by programmable circuits. When an element or circuit is said to be "connected to" another element or an element or circuit is said to be "connected between" two nodes, it may be directly coupled or connected to another element or there may be an intermediate element, and the connection between the elements may be physical, logical, or a combination thereof. Conversely, when an element is said to be "directly coupled to" or "directly connected to" another element, it means that there is no intermediate element between the two.
[0039] At the same time, certain words are used in the specification and claims of the utility model to refer to specific components. It should be understood by those skilled in the art that hardware manufacturers may use different terms to refer to the same component. The specification and claims of the utility model do not use the difference in name as a way to distinguish components, but use the difference in function of the components as the criterion for distinction.
[0040] In the utility model, the switch tube is selected from a bipolar transistor or a field effect transistor. The first end and the second end of the switch tube are respectively a high potential end and a low potential end, and the control end is used to receive a driving signal to control the on and off of the switch tube. The first end, the second end and the control end of a P-type metal oxide semiconductor field effect transistor (MOSFET) are respectively a source, a drain and a gate, and the first end, the second end and the control end of an N-type MOSFET are respectively a drain, a source and a gate.
[0041] Below, the utility model is described in detail with reference to the accompanying drawings.
[0042] Figure 1 A schematic structural diagram of a display device in the prior art is shown.
[0043] like Figure 1 As shown, the display device 100 may include a display array 110 , a gate driving circuit 120 , a source driving circuit 130 , a timing control circuit 140 , and an afterimage elimination circuit 150 .
[0044] The display array 110 is composed of a plurality of pixel units defined by the intersection of a plurality of scan lines and a plurality of data lines. Generally speaking, a pixel unit mainly includes a thin film transistor, a storage capacitor and a liquid crystal capacitor.
[0045] The output terminal of the gate driving circuit 120 is coupled to a plurality of scan lines to provide gate driving signals G1 to Gn for turning on or off a plurality of thin film transistors connected to the corresponding scan lines.
[0046] The source driving circuit 130 is connected to a plurality of data lines, and provides grayscale display voltages S1 to Sn to corresponding pixel units when a plurality of thin film transistors are turned on, so that each pixel unit stores an image signal to display an image.
[0047] The timing control circuit 140 receives display data from the front end via a data interface, generates timing signals and gate control signals according to the display data, and is connected to the gate drive circuit 120 and the source drive circuit 130 to provide various timing signals to the gate drive circuit 120 and the source drive circuit 130.
[0048] The afterimage elimination circuit 150 is connected to the timing control circuit 140 and is used to generate the afterimage control signal XON. When the display device 100 is turned off, the timing control circuit 140 generates the clock signal CLK according to the effective afterimage control signal XON, and controls the gate drive circuit 120 to output high-level gate drive signals G1 to Gn to turn on the thin film transistors in the display array 110, accelerate the release of the stored charge, and thus eliminate the shutdown afterimage. The levels of the clock signal CLK and the gate drive signals G1 to Gn follow the voltage value of the gate-on voltage VGH.
[0049] Figure 2 Shows Figure 1 The timing diagram of some signals when the device is shut down is shown in FIG. Figure 2 From top to bottom are the voltage waveform of the input voltage VIN, the voltage waveform of the image elimination control signal XON and the voltage waveform of the clock signal CLK. In order to avoid the false triggering of the shutdown image elimination function, a lower trigger voltage is set.
[0050] At time T0, the display device 100 is turned off, and the input voltage VIN and the image elimination control signal XON drop from a high level to a low level. Since the trigger voltage of the shutdown image elimination function set at this time is relatively low, it is not until time t1 that the level of the image elimination control signal XON drops to the trigger voltage. The level of the clock signal CLK follows the gate turn-on voltage VGH, turning on the thin film transistors in the display array 110 and releasing the stored voltage to eliminate the shutdown image elimination phenomenon.
[0051] However, due to the low trigger voltage, when the level of the shadow control signal XON drops to the trigger voltage, the load of the branch where AVDD is located suddenly becomes lighter. At this time, AVDD will discharge to VIN through the conduction path of the parasitic diode. Figure 5a As shown, it will carry a high input voltage VIN for a short period of time, and then continue to discharge until the end, as shown in Figure 2 As shown, the input voltage VIN will rebound to above 2.0V during the time period t1 to t2 of the shutdown phase, causing XON to be falsely triggered, resulting in the shutdown afterimage problem.
[0052] If a higher trigger voltage is set, although the charge can be fully released when shutting down to effectively eliminate the shutdown afterimage phenomenon, the display device 100 is prone to cause the input voltage VIN to decrease due to the probability of large current when working, thereby erroneously triggering the shutdown afterimage elimination function.
[0053] In order to solve the above problems, the present invention provides a residual image elimination circuit. Figure 3 shown.
[0054] Figure 3 FIG. 1 is a schematic diagram showing a structure of an afterimage elimination circuit provided by an embodiment of the present disclosure, Figure 4 Show Figure 3 Timing diagram of some signals of the afterimage elimination circuit when the display device is turned off. It should be understood that Figure 3 Only a part of the main circuit (power chip or DC-DC power module) of the afterimage elimination circuit proposed in the display device of the utility model to solve the above-mentioned technical problems is shown, and all branch circuits involving the power supply voltage are not fully shown. A person skilled in the art can understand its function in combination with the complete circuit principle of the display device of the disclosed prior art, and can adapt to the circuit principles of different types of display devices to perform operations of deletion, modification, addition, and merging of circuit modules, which are not limited here.
[0055] refer to Figure 3 The afterimage elimination circuit 200 provided by the embodiment of the utility model comprises:
[0056] The first switch tube Q1 is connected between the input voltage port VIN33 (a branch of the input voltage VIN) and the main circuit of the power module, and receives the shadow elimination control signal XON to open / close the path for the input voltage VIN to access the main circuit;
[0057] The first control unit 210 is connected to at least one branch circuit (such as Figure 3 The first control unit 210 receives a gate-on voltage VGLH (for example, the gate-on voltage is VGH when in a high potential signal state and VGL when in a low potential state) to control the on-time of the first control unit 210 connected to the main circuit of the power module, thereby forming a first discharge path for the return current between the analog power input port AVDD and the input voltage port VIN33;
[0058] and / or a second control unit 220, connected between the analog power input port AVDD and the main circuit of the power module, receives the gate-on voltage VGLH to control the on-time of the second control unit 220 connected to the main circuit of the power module, and forms a second discharge path of the return current between the analog power input port AVDD and the input voltage port VIN33,
[0059] Thus, the afterimage elimination circuit 200 can be used to cut off the connection path of the input voltage VIN when the display device is turned off, and form a discharge path for the return current between the analog power input port AVDD and the input voltage port VIN33, so as to maintain the input voltage VIN and the afterimage elimination control signal XON in a stable power-off state when the display device is turned off, such as Figure 4 shown.
[0060] In some embodiments, the first control unit 210 includes: a second switch tube Q2 and a first capacitor network, such as Figure 3 As shown, the first end of the second switch tube Q2 is connected to the branch where the input voltage VIN is located, the control end is connected to the gate start voltage VGLH, and the first capacitor network is connected between the second end of the second switch tube Q2 and the ground, and is used to form a first discharge path for the return current during the conduction phase of the second switch tube Q2.
[0061] In some embodiments, the first capacitor network comprises:
[0062] A plurality of first capacitors, such as C21 and C22, are connected in parallel between the second end of the second switch tube Q2 and the ground.
[0063] In some embodiments, the second control unit 220 includes: a third switch tube Q3 and a second capacitor network, Figure 3The first end of the third switch tube Q3 is connected to the branch where the analog power supply is located, the control end is connected to the gate start voltage VGLH, and the second capacitor network is connected between the second end of the third switch tube Q3 and the ground, and is used to form a second discharge path for the return current during the conduction phase of the third switch tube Q3.
[0064] In some embodiments, the second capacitor network includes:
[0065] A plurality of second capacitors, such as C31, C32 and C33, are connected in parallel between the second end of the third switch tube Q3 and the ground.
[0066] In some embodiments, the first switch tube Q1 is turned on when the display device is turned on, and is turned off when the display device is turned off.
[0067] In some embodiments, any one of the first switch tube Q1, the second switch tube Q2 and the third switch tube Q3 is selected from any one of a metal oxide semiconductor field effect transistor (MOSFET), a back cathode field effect transistor (IGBT), and a bipolar junction transistor (BJT).
[0068] Specifically in this embodiment, any one of the first switch tube Q1, the second switch tube Q2 and the third switch tube Q3 is an N-type metal oxide semiconductor field effect transistor (NMOS tube).
[0069] In this embodiment, a capacitor network is added between the analog power supply branch and the input voltage VIN branch (VIN33) to form a discharge path for the return current, thereby effectively absorbing the return current when the analog power supply AVDD is shut down, preventing the false triggering of the image elimination control signal XON, and effectively improving the shutdown afterimage problem.
[0070] Furthermore, in some embodiments, Figure 5b As shown, the parasitic diode in the switch tube adjacent to the analog power input port AVDD in the main circuit of the power module is set with its side close to the analog power input port AVDD as the cathode, so as to avoid Figure 5a In the prior art shown in FIG. 1 , the AVDD load is reduced when the power is turned off, and the reflux current returns to the main circuit to recharge VIN until it rebounds, which effectively improves the Figure 6a The rebound problem of input voltage VIN and XON after shutdown in the prior art is solved, and the stability of the system is improved. The improvement effect is as follows Figure 6b As shown, after the display device is turned off after the improvement, the input voltage VIN is powered off normally without abnormal rise. At the same time, no additional components are added to the power chip, and the cost is not increased.
[0071] Based on the same inventive concept, on the other hand, the embodiment of the utility model also provides a display device, combined with Figure 1 It is understood that the display device may include, for example:
[0072] Display array;
[0073] A gate driving circuit, wherein the gate driving circuit provides a gate driving signal to the display array through an output terminal thereof;
[0074] A source driving circuit, wherein the source driving circuit provides a source data signal to the display array through an output terminal thereof;
[0075] A timing control circuit, wherein the timing control circuit provides timing signals to the gate driving circuit and the source driving circuit respectively through its output terminals;
[0076] As described above, the afterimage elimination circuit 200 cuts off the connection path of the input voltage VIN when the display device is turned off, and forms a discharge path for the return current between the analog power input port AVDD to the input voltage VIN port VIN33, so as to maintain the input voltage VIN and the afterimage elimination control signal XON in a stable power-off state when the display device is turned off.
[0077] In summary, the embodiment of the utility model provides an afterimage elimination circuit 200 and a display device using the afterimage elimination circuit 200, wherein the afterimage elimination circuit 200 includes: a first switch tube Q1, receiving an afterimage elimination control signal XON to open / close the path for the input voltage VIN to access the main circuit; a first control unit 210, receiving a gate-on voltage VGLH to control the first control unit 210 to access the main circuit of the power module, forming a first discharge path for the return current between the analog power input port and the input voltage port; and / or a second control unit 220, receiving the gate-on voltage VGLH to control the second control unit 220 to access the main circuit of the power module, forming a second discharge path for the return current between the analog power input port and the input voltage port, so that the afterimage elimination circuit 200 can cut off the connection path of the input voltage VIN when the display device is turned off, and form a discharge path for the return current between the analog power input port AVDD and the input voltage VIN port VIN33, so as to maintain the input voltage VIN and the afterimage elimination control signal XON in a stable power-off state when the power is turned off. Therefore, a return current path is formed by adding a load to the analog power supply branch and adding a capacitor network between the input voltage VIN branch, and the capacitor is added to the AVDD branch and the VIN33 branch. When the power is turned on, the second switch tube Q2 and the third switch tube Q3 will not be turned on to charge the capacitor, and the power will be turned on normally; when the power is turned off, since XON is turned on, VGL is pulled to the VGH voltage, the second switch tube Q2 and the third switch tube Q3 are turned on, and the capacitor network will be charged first to form a discharge path for the return current. In this way, the time of connecting to the main circuit is controlled by the NMOS tube, which effectively absorbs the return current when the analog power supply AVDD is turned off, prevents the false triggering of XON, and effectively improves the shutdown afterimage problem.
[0078] In addition, by forcing the parasitic diode of the switch tube on the branch connected to the analog power input port AVDD inside the power chip to face right, the reflux current is prevented from returning to the main circuit after power failure, effectively improving the rebound of the input voltage VIN and XON after shutdown, thereby improving the stability of the system. At the same time, no additional components are added to the power chip, and the cost is not increased.
[0079] It should be noted that in the description of the present invention, it is necessary to understand that the terms "upper", "lower", "inner" and the like indicating directions or positional relationships are only for the convenience of describing the present invention and simplifying the description, and do not indicate or imply that the components or elements referred to must have a specific direction, be constructed and operated in a specific direction, and therefore cannot be understood as a limitation on the present invention.
[0080] In addition, in this article, relational terms such as first and second are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply that there is any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that the process, method, article or equipment including a series of elements includes not only those elements, but also includes other elements not explicitly listed, or also includes elements inherent to such process, method, article or equipment. In the absence of more restrictions, the elements limited by the statement "comprise one..." do not exclude the existence of other identical elements in the process, method, article or equipment including the elements.
[0081] Finally, it should be noted that: Obviously, the above embodiments are only examples for clearly explaining the present invention, and are not intended to limit the implementation methods. For ordinary technicians in the relevant field, other different forms of changes or modifications can be made based on the above description. It is not necessary and impossible to list all the implementation methods here. The obvious changes or modifications derived from this are still within the scope of protection of the present invention.
Claims
1. A residual image elimination circuit, characterized in that: include: The first switch tube is connected between the input voltage port and the main circuit of the power module, and receives a shadow elimination control signal to open / close the path for the input voltage to access the main circuit; A first control unit is connected to at least one branch connected to the input voltage, receives a gate start voltage to control the first control unit to connect to the main circuit of the power module, and forms a first discharge path for the return current between the analog power input port and the input voltage port; And / or a second control unit, connected between the analog power input port and the main circuit of the power module, receives the gate start voltage to control the second control unit to connect to the main circuit of the power module, forming a second discharge path for the return current between the analog power input port and the input voltage port.
2. The afterimage elimination circuit according to claim 1, wherein: The first control unit comprises: A second switch tube and a first capacitor network, wherein the first end of the second switch tube is connected to the branch where the input voltage is located, the control end is connected to the gate turn-on voltage, and the first capacitor network is connected between the second end of the second switch tube and the ground, forming a first discharge path for the return current during the conduction phase of the second switch tube.
3. The afterimage elimination circuit according to claim 2, wherein: The first capacitor network comprises: A plurality of first capacitors are connected in parallel between the second end of the second switch tube and the ground.
4. The afterimage elimination circuit according to claim 3, wherein: The second control unit comprises: A third switch tube and a second capacitor network, wherein the first end of the third switch tube is connected to the branch where the analog power supply is located, the control end is connected to the gate turn-on voltage, and the second capacitor network is connected between the second end of the third switch tube and the ground, forming a second discharge path for the return current during the conduction phase of the third switch tube.
5. The afterimage elimination circuit according to claim 4, wherein: The second capacitor network comprises: A plurality of second capacitors are connected in parallel between the second end of the third switch tube and the ground.
6. The afterimage elimination circuit according to claim 1, wherein: The first switch tube is turned on when the display device is turned on, and is turned off when the display device is turned off.
7. The afterimage elimination circuit according to claim 4, wherein: Any one of the first switch tube, the second switch tube and the third switch tube is any one selected from a metal oxide semiconductor field effect transistor, a back cathode field effect transistor and a bipolar transistor.
8. The afterimage elimination circuit according to claim 7, wherein: Any one of the first switch tube, the second switch tube and the third switch tube is an N-type metal oxide semiconductor field effect tube.
9. The afterimage elimination circuit according to claim 5, wherein: The parasitic diode in the switch tube adjacent to the analog power input port in the main circuit of the power module is set with its side close to the analog power input port as the cathode.
10. A display device, characterized in that: include: Display array; A gate driving circuit, wherein the gate driving circuit provides a gate driving signal to the display array through an output terminal thereof; A source driving circuit, wherein the source driving circuit provides a source data signal to the display array through an output terminal thereof; A timing control circuit, wherein the timing control circuit provides timing signals to the gate driving circuit and the source driving circuit respectively through its output terminals; The afterimage elimination circuit as described in any one of claims 1 to 9 cuts off the connection path of the input voltage when the display device is turned off, and forms a discharge path for the return current between the analog power input port and the input voltage port.