Asymmetric protection circuit for positive and negative power supplies of digital power amplifier

Abstract

The utility model provides an asymmetric protection circuit for positive and negative power supplies of a digital power amplifier, which comprises a resistance voltage division circuit, a voltage comparison circuit, a voltage clamping circuit, a monostable trigger circuit and a triode switching circuit, the resistance voltage division circuit generates positive and negative set voltages, and the positive and negative set voltages, the neutral-point voltages of the positive and negative power supplies, + 15V, R5, R9 and GND form a loop; a positive reference voltage is provided for a pin 11 of the U17; the GND, the R21, the R28 and the-15V form a loop and provide negative reference voltage for the fourth pin of the U17, and the voltage comparison circuit is composed of an LM339PWR and used for comparing the set voltage with the neutral-point voltage of the positive power supply and the negative power supply. According to the asymmetric protection circuit for the positive and negative power supplies of the digital power amplifier, the protection circuit is added on the power amplifier, and whether the positive and negative power supplies of the power amplifier are symmetric can be detected in real time. When positive and negative power supply deviation of the power amplifier is large, the protection circuit works and the power amplifier is closed. Therefore, related personnel can perform maintenance and search for problems, and further damage to the power amplifier is avoided.

Description

Technical Field

[0001] The utility model relates to the technical field of circuits, in particular to a positive and negative power asymmetry protection circuit for a digital power amplifier. Background Art

[0002] When using power amplifier products, people tend to have more stringent requirements for sound quality, and the THD of professional power amplifiers should be below 1%. We know that good quality power amplifiers are generally powered by dual power supplies, but due to various reasons, sometimes the positive and negative power supplies may be asymmetrical, causing the sound of the amplifier to fluctuate, the distortion to increase, and in severe cases, it may even damage components and affect product quality.

[0003] In order to overcome the shortcomings of the existing technology, a protection circuit is added to the power amplifier to detect whether the positive and negative power supplies of the power amplifier are symmetrical in real time. When the positive and negative power supply deviation of the power amplifier is large, the protection circuit works and shuts down the power amplifier. In this way, relevant personnel can conduct maintenance and find problems to avoid further damage to the power amplifier.

[0004] Therefore, it is necessary to provide a digital power amplifier positive and negative power asymmetry protection circuit to solve the above technical problems. Utility Model Content

[0005] In order to solve the above technical problems, the utility model provides a digital power amplifier positive and negative power asymmetry protection circuit. A protection circuit is added to the power amplifier to detect whether the positive and negative power of the power amplifier are symmetrical in real time. When the positive and negative power deviation of the power amplifier is large, the protection circuit works and shuts down the power amplifier. In this way, relevant personnel can perform maintenance and find problems to avoid further damage to the power amplifier.

[0006] The utility model provides a digital power amplifier positive and negative power asymmetry protection circuit, which is composed of a resistor voltage divider circuit, a voltage comparison circuit, a voltage clamp circuit, a monostable trigger circuit, and a triode switch circuit, wherein:

[0007] The resistor voltage divider circuit generates positive and negative set voltages and positive and negative power supply midpoint voltages. +15V, R5, R9, and GND form a loop to provide a positive reference voltage for pin 11 of U17; GND, R21, R28, and -15V form a loop to provide a negative reference voltage for pin 4 of U17. +VCC is the positive power supply of the power amplifier, and -VEE is the negative power supply of the power amplifier. +VCC, R11, R18, and -VEE form a loop to provide the midpoint voltage of the positive and negative power supplies of the power amplifier and are connected to pins 5 and 10 of U17.

[0008] Furthermore, the voltage comparison circuit is composed of LM339PWR, which is used to compare the set voltage with the midpoint voltage of the positive and negative power supplies. When the difference between +VCC and -VEE is small, the output of the comparator U17 is open, and the protection circuit does not work; when the difference between +VCC and -VEE is large, the midpoint voltage of the positive and negative power supplies is greater than the set positive and negative reference voltages, and the comparator U17 outputs the set positive and negative reference voltages.

[0009] Further, the voltage clamp circuit is composed of diodes D9 and D7, which clamps the output of LM339PWR to a low level input to the 555 timer;

[0010] Furthermore, the monostable trigger circuit is composed of a 555 timer, and when the 2nd pin is at a low level, the 3rd pin outputs a high level, and can detect in real time;

[0011] Furthermore, in the transistor switch circuit, when the base of Q5 is at a high level, Q5 is turned on, causing SD to become low. When SD is at a low level, the 7-pin CSD of the power amplifier chip U1 is also pulled low, and the power amplifier is turned off.

[0012] Compared with the related art, the digital power amplifier positive and negative power asymmetry protection circuit provided by the utility model has the following beneficial effects:

[0013] 1. When the positive and negative power supplies of a dual-power amplifier differ greatly, the total harmonic distortion will increase. This circuit can detect whether the positive and negative power supplies are symmetrical in real time, so that this problem can be discovered and found in time;

[0014] 2. When the positive and negative power supplies of a dual-power amplifier differ greatly, the amplifier may be further damaged. This circuit can avoid this problem and protect the amplifier. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] Figure 1 A protection circuit diagram of a digital power amplifier positive and negative power asymmetry protection circuit provided by the utility model;

[0016] Figure 2 A power amplifier circuit diagram of a digital power amplifier positive and negative power asymmetry protection circuit provided by the utility model;

[0017] Figure 3 The utility model provides a working flow chart of a digital power amplifier positive and negative power asymmetry protection circuit. DETAILED DESCRIPTION

[0018] The utility model is further described below in conjunction with the accompanying drawings and implementation modes.

[0019] In this application, reference is made to Figure 1-Figure 3As shown, a digital power amplifier positive and negative power asymmetry protection circuit is characterized in that the protection circuit is composed of a resistor voltage divider circuit, a voltage comparison circuit, a voltage clamping circuit, a monostable trigger circuit, and a transistor switch circuit, wherein: the resistor voltage divider circuit generates positive and negative set voltages and the positive and negative power midpoint voltages, +15V, R5, R9, and GND form a loop to provide a positive reference voltage for pin 11 of U17; GND, R21, R28, and -15V form a loop to provide a negative reference voltage for pin 4 of U17, +VCC is the positive power supply of the power amplifier, -VEE is the negative power supply of the power amplifier, +VCC, R11, R18, and -VEE form a loop to provide the midpoint voltage of the positive and negative power supplies of the power amplifier and connect to pins 5 and 10 of U17; the voltage comparison circuit is composed of LM339PWR, which is used to compare the set voltage with the midpoint voltage of the positive and negative power supplies. When the difference between +VCC and -VEE is small, the output of comparator U17 is open and the protection circuit does not work; when the difference between +VCC and -VEE is large, the midpoint voltage of the positive and negative power supplies is greater than the set positive and negative reference voltages, and comparator U17 outputs the set positive and negative reference voltages; the voltage clamping circuit is composed of diodes D9 and D7, which clamps the output of LM339PWR to a low level and inputs the 555 timer. The monostable trigger circuit is composed of a 555 timer. When pin 2 is low, pin 3 outputs a high level and can detect in real time. In the transistor switch circuit, when the base of Q5 is high, Q5 is turned on, making SD low. When SD is low, pin 7 CSD of the power amplifier chip U1 is also pulled low, and the power amplifier is turned off.

[0020] As the first embodiment of the utility model: +15V, R5, R9, GND form a loop to provide a positive reference voltage for pin 11 of U17; GND, R21, R28, -15V form a loop to provide a negative reference voltage for pin 4 of U17. +VCC is the positive power supply of the power amplifier, -VEE is the negative power supply of the power amplifier, +VCC, R11, R18, -VEE form a loop to provide the midpoint voltage of the positive and negative power supplies of the power amplifier and connect to pins 5 and 10 of U17. When the difference between +VCC and -VEE is small, the output of comparator U17 is open and the protection circuit does not work; when the difference between +VCC and -VEE is large, the midpoint voltage of the positive and negative power supplies is greater than the set positive and negative reference voltages, and comparator U17 outputs the set positive and negative reference voltages, which are clamped by diodes D9 and D7, so that pin 2 of the 555 timing chip is low. The timing circuit is a monostable trigger, which is triggered at a low level, and pin 3 outputs a high level, Q5 is turned on, and SD becomes a low level. SD is low level, and the 7-pin CSD of the power amplifier chip U1 is also pulled low, and the power amplifier is turned off;

[0021] As the first embodiment of the utility model: the internal circuit of the 555 chip U2 (NE555DR) is as follows Figure 1As shown, three 5K resistors divide the 5.1V DC power supply, of which 2 / 3 (about 3.4V) is supplied to the non-inverting end of comparator CMP1, and 1 / 3 (about 1.7V) is supplied to the inverting end of comparator CMP2. The inverting end of comparator CMP1 is grounded through capacitor C14. When the circuit is just powered on, since the voltage across capacitor C14 cannot change suddenly, the voltage at the inverting end of CMP1 is lower than that at the non-inverting end, so comparator CMP1 outputs a high level H. For comparator CMP2, the default level of the non-inverting end is a high level H (because U2 is triggered by a negative pulse), which is higher than the inverting end voltage of 1.7V. Therefore, the output of comparator CMP2 is also a high level H. Since R=H and S=H of the trigger FF, the output of the trigger is a high level H. After passing through an inverter (U5) NOT, the output is a low level L. Transistor Q5 fails to conduct, and the power amplifier outputs normally;

[0022] On the other hand, the high level H output by the trigger FF turns on the transistor Q9. At this time, the 7th pin of U2 is pulled to the low level L (equivalent to the capacitor C14 being in the discharge state). This pin is also at the same potential as the inverting terminal of the comparator CMP1, maintaining the output of the comparator CMP1 at H.

[0023] When pin 2 is at a low level, the voltage at the in-phase terminal of the comparator CMP2 is lower than the voltage at the inverting terminal and the output is a low level. Since R = H, S = L, the trigger FF outputs a low level. After passing through an inverter (U5) NOT, the output is a high level. The transistor Q5 is turned on and SD is a low level. When SD is a low level, the 7-pin CSD of the power amplifier chip U1 is also pulled low and the power amplifier is turned off.

[0024] On the other hand, the trigger FF outputs a low level L to turn off the transistor Q9. At this time, the DC 5.1V power supply charges the capacitor C14 through the resistor R16, and the potential of the 6th pin of U2 begins to rise. When it rises to a value greater than 3.4V at the positive input terminal, CMP1 outputs a low level L. Since R=L, S=L, the trigger FF outputs a high level H. After passing through an inverter (U5) NOT, the output is a low level L. The transistor Q5 fails to conduct, and the power amplifier outputs normally.

[0025] After the power amplifier outputs normally, a new round of detection begins, and this cycle repeats, thus achieving real-time detection.

[0026] In the description of the present invention, it should be noted that the terms "center", "up", "down", "left", "right", "vertical", "horizontal", "inside" and "outside" etc. indicating directions or positional relationships are based on the directions or positional relationships shown in the accompanying drawings. They are only for the convenience of describing the present invention and simplifying the description. They do not indicate or imply that the device or element referred to must have a specific direction, be constructed and operated in a specific direction. Therefore, they cannot be understood as limitations on the present invention.

[0027] The above are only embodiments of the present invention, and are not intended to limit the patent scope of the present invention. Any equivalent structure or equivalent process transformation made using the contents of the specification and drawings of the present invention, or directly or indirectly applied in other related technical fields, are also included in the patent protection scope of the present invention.

Claims

1. A digital power amplifier positive and negative power asymmetry protection circuit, characterized in that: The protection circuit is composed of a resistor voltage divider circuit, a voltage comparison circuit, a voltage clamp circuit, a monostable trigger circuit, and a triode switch circuit, wherein: The resistor voltage divider circuit generates positive and negative set voltages and positive and negative power supply midpoint voltages. +15V, R5, R9, and GND form a loop to provide a positive reference voltage for pin 11 of U17; GND, R21, R28, and -15V form a loop to provide a negative reference voltage for pin 4 of U17. +VCC is the positive power supply of the power amplifier, and -VEE is the negative power supply of the power amplifier. +VCC, R11, R18, and -VEE form a loop to provide the midpoint voltage of the positive and negative power supplies of the power amplifier and are connected to pins 5 and 10 of U17.

2. A digital power amplifier positive and negative power asymmetry protection circuit according to claim 1, characterized in that: The voltage comparison circuit is composed of LM339PWR, which is used to compare the set voltage with the midpoint voltage of the positive and negative power supplies. When the difference between +VCC and -VEE is small, the comparator U17 output is open and the protection circuit does not work; when the difference between +VCC and -VEE is large, the midpoint voltage of the positive and negative power supplies is greater than the set positive and negative reference voltages, and the comparator U17 outputs the set positive and negative reference voltages.

3. A digital power amplifier positive and negative power asymmetry protection circuit according to claim 1, characterized in that: The voltage clamp circuit is composed of diodes D9 and D7, which clamps the output of the LM339PWR to a low level input to the 555 timer.

4. A digital power amplifier positive and negative power asymmetry protection circuit according to claim 1, characterized in that: The monostable trigger circuit is composed of a 555 timer. When the 2nd foot is at a low level, the 3rd foot outputs a high level and can detect in real time.

5. The digital power amplifier positive and negative power asymmetry protection circuit according to claim 1, characterized in that: In the transistor switch circuit, when the base of Q5 is at a high level, Q5 is turned on, causing SD to become low. When SD is at a low level, the 7-pin CSD of the power amplifier chip U1 is also pulled low, and the power amplifier is turned off.

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