Integrated circuit

Abstract

The disclosure provides an integrated circuit. The integrated circuit includes first and second timed forwarding switches each implemented using a strong transistor in at least one strong active region structure. The integrated circuit also includes a first clocked inverter and a second clocked inverter each implemented using a weak transistor in at least one weak active region structure. The integrated circuit further includes a first inverter cross-coupled with the first time-controlled inverter and a second inverter cross-coupled with the second time-controlled inverter. The output of the first time control forwarding switch is conductively connected with the output of the first time control inverter, and the output of the second time control forwarding switch is conductively connected with the output of the second time control inverter.

Description

Technical Field

[0001] The present disclosure relates to an integrated circuit. Background Art

[0002] The recent trend of integrated circuit (IC) miniaturization has resulted in smaller devices that consume less power but provide more functionality at higher speeds. The miniaturization process has also resulted in more stringent design and manufacturing specifications and reliability challenges. Various electronic design automation (EDA) tools generate standard cell layout designs for integrated circuits and optimize and verify the standard cell layout designs while ensuring that the standard cell layout design and manufacturing specifications are met. Utility Model Content

[0003] In one embodiment of the present disclosure, an integrated circuit includes a first clocked forwarding switch, a second clocked forwarding switch, a first clocked inverter, a second clocked inverter, a strong active region structure, a weak active region structure, a first inverter, and a second inverter. The first clocked forwarding switch and the second clocked forwarding switch are each implemented using a strong transistor. The first clocked inverter and the second clocked inverter are each implemented using a weak transistor. The output of the first clocked forwarding switch is conductively connected to the output of the first clocked inverter. The output of the second clocked forwarding switch is conductively connected to the output of the second clocked inverter. The strong active region structure extends in a first direction. Each of the strong active region structures has a portion of a strong transistor. The weak active region structure extends in the first direction. Each of the weak active region structures has a portion of a weak transistor. The first inverter has an input conductively connected to the output of the first clocked inverter and has an output conductively connected to the input of the first clocked inverter. The second inverter has an input conductively connected to the output of the second clocked inverter and has an output conductively connected to the input of the second clocked inverter.

[0004] In one embodiment of the present disclosure, an integrated circuit includes a first clocked forwarding switch, a second clocked forwarding switch, a first clocked inverter, a second clocked inverter, a strong active region structure, a weak active region structure, a first connecting conductor, a second connecting conductor, a first inverter, and a second inverter. The first clocked forwarding switch and the second clocked forwarding switch are each implemented using a strong transistor. The first clocked inverter and the second clocked inverter are each implemented using a weak transistor. The strong active region structure extends in a first direction and has a strong transistor in the strong active region structure. The weak active region structure extends in the first direction and has a weak transistor in the weak active region structure. The average gate width of the strong transistor with a p-channel is greater than the average gate width of the weak transistor with a p-channel. The average gate width of the strong transistor with an n-channel is greater than the average gate width of the weak transistor with an n-channel. The first connecting conductor extends in a second direction perpendicular to the first direction. The first connecting conductor conductively connects the output of the first clocked forwarding switch to the output of the first clocked inverter. The second connecting conductor extends in the second direction. The second connecting conductor conductively connects the output of the second clocked forwarding switch to the output of the second clocked inverter. The first inverter is coupled between the input of the first clocked inverter and the first connecting conductor. The first inverter has an input conductively connected to the first connecting conductor. The second inverter is coupled between the input of the second clocked inverter and the second connecting conductor. The second inverter has an input conductively connected to the second connecting conductor. BRIEF DESCRIPTION OF THE DRAWINGS

[0005] The various aspects of the present disclosure will be best understood by reading the following detailed description in conjunction with the accompanying drawings. It should be noted that, in accordance with standard practice in the industry, various features are not drawn to scale. In fact, the size of various features may be arbitrarily increased or reduced for clarity of discussion.

[0006] Figure 1A1 to Figure 1C1 is a block diagram of integrated circuits 100A-100C having master-slave flip-flops and associated support circuits according to some embodiments.

[0007] Figure 1A2 to Figure 1C2 is a circuit diagram of an integrated circuit 100A-100C having a master-slave flip-flop and associated support circuits according to some embodiments.

[0008] Figure 2 According to some embodiments Figure 1A1 to Figure 1C1 and Figure 1A2 to Figure 1C2 FIG. 1 is a plan view of integrated circuits 100A to 100C in FIG.

[0009] FIG. 3A to FIG. 3D According to some embodiments Figure 2 Schematic diagram of cross-sectional views of an integrated circuit in various cutting planes.

[0010] FIG. 4A to FIG. 4D According to some embodiments Figure 2 Schematic diagram of cross-sectional views of an integrated circuit in various cutting planes.

[0011] FIG. 5A to FIG. 5D According to some embodiments Figure 2 Schematic diagram of cross-sectional views of an integrated circuit in various cutting planes.

[0012] Figure 6 According to some embodiments Figure 1A1 to Figure 1C1 and Figure 1A2 to Figure 1C2 FIG. 1 is a plan view of integrated circuits 100A to 100C in FIG.

[0013] Figure 7 According to some embodiments Figure 1A1 to Figure 1C1 and Figure 1A2 to Figure 1C2 FIG. 1 is a plan view of integrated circuits 100A to 100C in FIG.

[0014] Figure 8 is a flow chart of a method of fabricating an integrated circuit according to some embodiments.

[0015] Fig. 9 is a block diagram of an electronic design automation (EDA) system according to some embodiments.

[0016] Fig.10 is a block diagram of an integrated circuit (IC) manufacturing system and an IC manufacturing flow associated therewith, according to some embodiments.

[0017] Description of Reference Numerals

[0018] 100A, 100B, 100C: Integrated circuits

[0019] 101: Input Devices

[0020] 102, 110G, 110I, 110J: Inverter

[0021] 103: First time-controlled forward switch / first time-controlled forward switch

[0022] 104: Master latch

[0023] 105: Second time-controlled forwarding switch

[0024] 106: Slave latch

[0025] 109: Output driver

[0026] 110D, 110E: Gated Inverter

[0027] 110Dn, 110En: Part 2

[0028] 110Dp, 110Ep: Part 1

[0029] 110F1, 110H1: Transmission gate

[0030] 110F2, 110H2: Time-controlled inverter

[0031] 201, 202, 208, 209: Boundary

[0032] 220N: Strong NMOS active region structure / strong active region structure

[0033] 220N[1], 220N[2]: Strong NMOS active region structure / NMOS active region structure

[0034] 220P: Strong PMOS active area structure / strong active area structure

[0035] 220P[1], 220P[2], 220Pm: Strong PMOS active region structure

[0036] 230N: Weak NMOS active region structure / weak active region structure

[0037] 230P: Weak PMOS active region structure / weak active region structure

[0038] 250, 260: Connecting conductor

[0039] 272F1, 272F1[1], 272F1[2], 272F2, 272H1, 272H1[1], 272H1[2], 272H2, 274F1, 274F1[1], 274F1[2], 274F2, 274H1, 274H1[1], 274H1[2], 274H2: Gate conductor

[0040] 272F1m, 274H1m: Merged gate conductor

[0041] 350MD, 360MD, dTnF1, dTnF2, dTnH1, dTnH2, dTpF1, dTpF2, dTpH1, dTpH2: Terminal conductor

[0042] 450M0, 460M0, 550M1, 560M1: vertical conductive line

[0043] 800: Methods

[0044] 810, 820, 830, 840, 850, 860: Operation

[0045] 900: Electronic Design Automation (EDA) Systems / Systems

[0046] 902: Hardware processor / processor

[0047] 904: Non-transitory computer-readable storage media / computer-readable storage media / computer-readable media / storage media / memory

[0048] 906: Instructions / computer program code

[0049] 907: Standard Cell Library

[0050] 908: Bus

[0051] 909: Layout

[0052] 910: I / O interface

[0053] 912: Network interface

[0054] 914: Network

[0055] 942: User Interface

[0056] 1000: Integrated Circuit (IC) Manufacturing System / Manufacturing System / System

[0057] 1020: Design Division

[0058] 1022: IC design layout / design layout

[0059] 1030: Veil Division

[0060] 1032: Data Preparation

[0061] 1044: Mask production

[0062] 1045: Shroud

[0063] 1050: IC manufacturing plant / IC production plant

[0064] 1052: Production Tools

[0065] 1053: Semiconductor wafer

[0066] 1060: IC device

[0067] A-A', B-B', C-C', D-D': Cutting planes

[0068] CD, CP, clkb, clkbb, SE, seb: signal

[0069] D: Data signal / layout area

[0070] M0, M1: Metal layer

[0071] F1: First time-controlled forward switch / first time-controlled forward switch / layout area

[0072] F2: First time-controlled inverter / Second time-controlled forwarding switch / Layout area

[0073] H1: Second time-controlled forward switch / second time-controlled forward switch

[0074] H2: Second clocked inverter / layout area

[0075] ILD0, ILD1: interlayer dielectric

[0076] E, J: Layout area

[0077] m50nF1, m50nF2, m50pF1, m50pF2, m60nH1, m60nH2, m60pH1, m60pH2: Metal stubs

[0078] ml_ax: Input Node

[0079] ml_b, sl_bx: output nodes

[0080] Q: Output

[0081] SI: Scanning signal

[0082] sl_b: node

[0083] TnF1, TnH1: Strong transistors

[0084] TnF2, TnH2, TpF2, TpH2: Weak transistors

[0085] TpF1, TpH1: Strong transistor / transistor

[0086] VD: Through-hole connector

[0087] X, Y, Z: direction DETAILED DESCRIPTION

[0088] The following disclosure provides many different embodiments or examples for implementing the different features of the provided target. The following describes specific examples of components, values, operations, materials, arrangements or similar elements to simplify the disclosure. Of course, these are only examples and are not intended to be limiting. It is expected that there are other components, values, operations, materials, arrangements or similar elements. For example, the following description may include an embodiment in which the first feature and the second feature are formed to be in direct contact, and may also include an embodiment in which additional features may be formed between the first feature and the second feature so that the first feature and the second feature may not be in direct contact. In addition, the disclosure may reuse reference numbers and / or letters in various examples. This repetition is for the purpose of brevity and clarity, rather than the relationship between the various embodiments and / or configurations discussed by itself.

[0089] Additionally, for ease of description, spatially relative terms such as "beneath," "below," "lower," "above," "upper," etc. may be used herein to describe the relationship of one component or feature to another (other) component or feature as shown in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein should be interpreted accordingly.

[0090] In some embodiments, a master-slave flip-flop includes a first latch having a first inverter cross-coupled with a first clocked inverter and a second latch having a second inverter cross-coupled with a second clocked inverter. The first clocked inverter and the second clocked inverter are implemented using weak transistors. The master-slave flip-flop also includes a first clocked forwarding switch and a second clocked forwarding switch, each of which is implemented using a strong transistor. The output of the first clocked forwarding switch is conductively connected to the input of the first inverter. The output of the second clocked forwarding switch is conductively connected to the input of the second inverter.

[0091] In some embodiments, the first time-controlled forwarding switch is a transmission gate coupled between the output of the input device and the input of the first inverter. In some embodiments, the second time-controlled forwarding switch is a transmission gate coupled between the output of the first inverter and the input of the second inverter. In some embodiments, the second time-controlled forwarding switch is a third time-controlled inverter coupled between the input of the first inverter and the input of the second inverter.

[0092] The average gate width of a strong transistor with a p-channel is greater than the average gate width of a weak transistor with a p-channel. The average gate width of a strong transistor with an n-channel is greater than the average gate width of a weak transistor with an n-channel. The strong transistor is implemented using a strong active region structure, while the weak transistor is implemented using a weak active region structure. Specifically, a strong P-type metal oxide semiconductor (P type metal oxide semiconductor, PMOS) transistor is implemented using a strong PMOS active region structure, while a weak PMOS transistor is implemented using a weak PMOS active region structure. A strong N-type metal oxide semiconductor (Ntype metal oxide semiconductor, NMOS) transistor is implemented using a strong NMOS active region structure, while a weak NMOS transistor is implemented using a weak NMOS active region structure.

[0093] In some embodiments, the strong PMOS active region structure has more fins than the weak PMOS active region structure, and the strong NMOS active region structure has more fins than the weak NMOS active region structure. In some embodiments, the strong PMOS active region structure has more nano-sheets than the weak PMOS active region structure, and the strong NMOS active region structure has more nano-sheets than the weak NMOS active region structure. In some embodiments, the strong PMOS active region structure has more nano-wires than the weak PMOS active region structure, and the strong NMOS active region structure has more nano-wires than the weak NMOS active region structure.

[0094] The master-slave flip-flop in the present disclosure includes both a strong transistor and a weak transistor, thereby reducing the resistance-capacitance (RC) delay in the forward signal path of the master-slave flip-flop, while reducing the driving strength of the first clocked inverter and the second clocked inverter in the reverse signal path. The master-slave flip-flop in the present disclosure has an improved switching speed compared to an alternative design in which transistors with the same type of channel (i.e., p-channel or n-channel) have a uniform gate width.

[0095] Figure 1A1 to Figure 1C1 is a block diagram of integrated circuits 100A-100C having master-slave flip-flops and associated support circuits according to some embodiments. Figure 1A2 to Figure 1C21 is a circuit diagram of an integrated circuit 100A to 100C having a master-slave flip-flop and associated support circuits according to some embodiments. The master-slave flip-flop is formed by an input device 101, a first clocked forwarding switch 103, a master latch 104, a second clocked forwarding switch 105, a slave latch 106, and an output driver 109. The first clocked forwarding switch 103 is configured to receive an input signal from the input device 101. The master latch 104 is coupled between the first clocked forwarding switch 103 and the second clocked forwarding switch 105. The slave latch 106 is coupled between the second clocked forwarding switch 105 and the output driver 109. The associated support circuits include inverters 110A to 110C configured to generate an inverted clock signal CPB and a common clock signal CPBB.

[0096] exist Figure 1A1 and Figure 1A2 In the embodiment, the first clock-controlled forwarding switch 103 is implemented as a transmission gate 110F1, and the second clock-controlled forwarding switch 105 is implemented as a gate-controlled inverter 105H1. Figure 1B1 to Figure 1C1 and Figure 1B2 to Figure 1C2 In the embodiment, the first clocked forwarding switch 103 is implemented as a transmission gate 110F1, and the second clocked forwarding switch 105 is implemented as a transmission gate 110H1.

[0097] exist Figure 1A1 to Figure 1C1 and Figure 1A2 to Figure 1C2 In FIG. 1 , the master latch 104 is implemented using an inverter 110G and a clocked inverter 110F2 that are cross-coupled to each other, and the slave latch 106 is implemented using an inverter 110I and a clocked inverter 110H2 that are cross-coupled to each other. Fig.1C1 and Fig.1C2 In FIG. 1 , the inverter 110G in the master latch 104 is a resettable inverter, and the clocked inverter 110H2 in the slave latch 106 is a resettable clocked inverter.

[0098] exist Figure 1A1 to Figure 1C1 and Figure 1A2 to Figure 1C2 In some embodiments, the input device 101 includes a gated inverter 110D and a gated inverter 110E. The gated inverter 110D is configured to receive a data signal D, and the gated inverter 110E is configured to receive a scan signal SI. Each of the gated inverter 110D and the gated inverter 110E includes a first portion having a PMOS transistor (labeled as 110Dp and 110Ep, respectively) and a second portion having an NMOS transistor (labeled as 110Dn and 110En, respectively). In some embodiments, the input device 101 includes the gated inverter 110D but does not include the gated inverter 110E.

[0099] exist Figure 1A1 to Figure 1C1 and Figure 1A2 to Figure 1C2In the embodiment, the transmission gate 110F1 is configured to receive the inverted clock signal CPB and the in-phase clock signal CPBB. When the inverted clock signal CPB is at logic low (logic LOW) (and the in-phase clock signal CPBB is at logic high), the data signal D from the gated inverter 110D and the scan signal SI from the gated inverter 110E are not transmitted to the input node ml_ax of the master latch 104. When the inverted clock signal CPB is at logic high (and the in-phase clock signal CPBB is at logic low), the inverted signal of the data signal D or the scan signal SI is transmitted to the input node ml_ax of the master latch 104.

[0100] exist Figure 1A1 to Figure 1C1 and Figure 1A2 to Figure 1C2 , the master latch 104 includes an inverter 110G and a time-controlled inverter 110F2 driven by clock signals CPB and CPBB. The output of the inverter 110G is connected to the input of the time-controlled inverter 110F2, and the output of the time-controlled inverter 110F2 is connected to the input of the inverter 110G. When the clock signal CPB is at a logic high (and the clock signal CPBB is at a logic low), the master latch 104 is in an unlatched state, and the signal at the output node ml_b of the master latch 104 is an inverted signal of the signal at the input node ml_ax of the master latch 104. Therefore, the signal at the output node ml_b becomes an inverted signal of the selected input signal (which is the data signal D received from the input device 101 or the scan signal SI received from the input device 101). At the same time, the second time-controlled forwarding switch 105 is set to a non-connected state by the clock signals CPB and CPBB, and the input node sl_a of the slave latch 106 is decoupled from the master latch 104. Thereafter, when the inverted clock signal CPB changes to a logic low (and the in-phase clock signal CPBB changes to a logic high), the master latch 104 changes to a latched state, and during the time period when the clock signal CPB is at a logic low (and the clock signal CPBB is at a logic high), the signal in the master latch 104 remains unchanged. When the clock signal CPB changes to a logic low, the latched signal value at the output node ml_b is the signal value of the selected input signal (received from the input device 101) at the first falling edge of the clock signal CPB.

[0101] When the clock signal CPB changes to a logic low (and the clock signal CPBB changes to a logic high), the second time-controlled forwarding switch 105 is changed to a connection state by the clock signals CPB and CPBB, and the latch signal in the master latch 104 is transmitted from the input node ml_ax to the input node sl_a of the slave latch 106 (such as Figure 1A1 and Figure 1A2 ), or transmitted from the output node ml_b to the input node sl_a of the slave latch 106 (as shown in Figure 1B1 to Figure 1C1 and Figure 1B2 to Figure 1C2 shown).

[0102] exist Figure 1A1 to Figure 1C1 and Figure 1A2 to Figure 1C2 , the slave latch 106 includes an inverter 110I and a time-controlled inverter 110H2 driven by clock signals CPB and CPBB. The output of the inverter 110I is connected to the input of the time-controlled inverter 110H2, and the output of the time-controlled inverter 110H2 is connected to the input of the inverter 110I. When the clock signal CPB is at a logic low (and the signal CPBB is at a logic high), the slave latch 106 is in an unlatched state, and the signal at the output node sl_bx of the slave latch 106 is an inverted signal of the signal at the input node sl_a of the slave latch 106. Therefore, the inverted signal of the latch signal at the output node ml_b of the master latch 104 is transmitted to the output node sl_bx of the slave latch 106. Thereafter, when the clock signal CPB changes to a logic high (and the signal CPBB changes to a logic low), the slave latch 106 changes to a latched state, the signal at the output node sl_bx of the slave latch 106 remains unchanged, and the latched signal value at the output node sl_bx after the current rising edge of the clock signal CPB is the value of the inverted signal of the latched signal at the output node ml_b latched after the previous falling edge (first falling edge) of the clock signal CPB.

[0103] During the time period when the clock signal CPB is at logic high after the current rising edge of the clock signal CPB, the signal value Q at the output Q of the output driver 109 (which is implemented as an inverter 110J) is n+1 Equal to the signal value of the selected input signal (received from the input device 101) at the previous falling edge (first falling edge) of the clock signal CPB.

[0104] exist Figure 1A1 to Figure 1C1 and Figure 1A2 to Figure 1C2 In some embodiments, at least the first clocked forwarding switch 103 and the second clocked forwarding switch 105 are implemented using strong transistors, while the clocked inverter 110F2 and the clocked inverter 110H2 are implemented using weak transistors. A CMOS inverter implemented using strong transistors has a greater driving strength than a CMOS inverter implemented using weak transistors. A CMOS buffer implemented using strong transistors has a greater driving strength than a CMOS buffer implemented using weak transistors. In some embodiments, the input device 101 and / or the output driver 109 are also implemented using strong transistors. In some embodiments, at least one of the inverter 110G of the master latch 104 and the inverter 110I of the slave latch 106 is also implemented using strong transistors.

[0105] Figure 2According to some embodiments Figure 1A1 to Figure 1C1 and Figure 1A2 to Figure 1C2 FIG. 1 is a plan view of the integrated circuits 100A to 100C in FIG. Figure 2 In the embodiment, the input device 101, the first clocked forwarding switch 103, the second clocked forwarding switch 105 and the output driver 109 are implemented in the layout areas "D", "F1", "F2" and "J" respectively. The clocked inverter 110F2 and the clocked inverter 110H2 are implemented in the layout areas "F2" and "H2" respectively.

[0106] Figure 2 The integrated circuit in the embodiment includes a strong PMOS active region structure 220P extending in the X direction, a strong NMOS active region structure 220N extending in the X direction, a weak PMOS active region structure 230P extending in the X direction, and a weak NMOS active region structure 230N extending in the X direction. Each of the input device 101, the first clocked forwarding switch 103, the second clocked forwarding switch 105, and the output driver 109 (respectively located in the layout areas "D", "F1", "F2", and "J") is composed of a p-channel strong transistor in the strong PMOS active region structure 220P and an n-channel strong transistor in the strong NMOS active region structure 220N. Each of the clocked inverter 110F2 and the clocked inverter 110H2 (respectively located in the layout areas "F2" and "H2") is composed of a p-channel weak transistor in the weak PMOS active region structure 230P and an n-channel weak transistor in the weak NMOS active region structure 230N. Each of the input device 101, the first clocked forwarding switch 103, the second clocked forwarding switch 105, and the output driver 109 is implemented as a first type of device, and each of the clocked inverter 110F2 and the clocked inverter 110H2 is implemented as a second type of device. In some alternative embodiments, at least one of the input device 101 and the output driver 109 is not implemented as a first type of device.

[0107] exist Figure 2 In the circuit cells shown, the average gate width of strong transistors with p-channels in the first type of devices is greater than the average gate width of weak transistors with p-channels in the second type of devices, and the average gate width of strong transistors with n-channels in the first type of devices is greater than the average gate width of weak transistors with n-channels in the second type of devices.

[0108] In some embodiments, when the active region structure is formed of a fin-shaped structure, the transistors fabricated in the strong PMOS active region structure 220P and the weak PMOS active region structure 230P are respectively strong p-channel fin field effect transistors (FinFETs) and weak p-channel FinFETs, and the transistors fabricated in the strong NMOS active region structure 220N and the weak NMOS active region structure 230N are respectively strong n-channel FinFETs and weak n-channel FinFETs. The number of fins in the strong PMOS active region structure 220P having a strong p-channel transistor is greater than the number of fins in the weak PMOS active region structure 230P having a weak p-channel transistor, and the number of fins in the strong NMOS active region structure 220N having a strong n-channel transistor is greater than the number of fins in the weak NMOS active region structure 230N having a weak n-channel transistor. In one embodiment, each of the strong PMOS active region structure 220P and the strong NMOS active region structure 220N has three fins, while each of the weak PMOS active region structure 230P and the weak NMOS active region structure 230N has two fins.

[0109] In some embodiments, when the active region structure is formed of a nanosheet structure, the transistors fabricated in the active region structure are nanosheet transistors. The number of nanosheets in the strong PMOS active region structure 220P having a p-channel strong transistor is greater than the number of nanosheets in the weak PMOS active region structure 230P having a p-channel weak transistor, and the number of nanosheets in the strong NMOS active region structure 220N having an n-channel strong transistor is greater than the number of nanosheets in the weak NMOS active region structure 230N having an n-channel weak transistor.

[0110] In one exemplary implementation, each of the strong PMOS active region structure 220P and the strong NMOS active region structure 220N has two nanosheets having a width of 32 nm along the Y direction, while each of the weak PMOS active region structure 230P and the weak NMOS active region structure 230N has a single nanosheet having a width of 32 nm along the Y direction.

[0111] In another exemplary implementation, each of the strong PMOS active region structure 220P and the strong NMOS active region structure 220N has two nanosheets having a width of 32 nm along the Y direction, while each of the weak PMOS active region structure 230P and the weak NMOS active region structure 230N has a single nanosheet having a width less than 32 nm (e.g., 26 nm or 19 nm) along the Y direction.

[0112] In yet another exemplary implementation, each of the strong PMOS active region structure 220P, the strong NMOS active region structure 220N, the weak PMOS active region structure 230P, and the weak NMOS active region structure 230N has two nanosheets. The width of the nanosheet in the strong PMOS active region structure 220P (e.g., 42 nm) is greater than the width of the nanosheet in the weak PMOS active region structure 230P (e.g., 32 nm), and the width of the nanosheet in the strong NMOS active region structure 220N (e.g., 30 nm) is greater than the width of the nanosheet in the weak NMOS active region structure 230N (e.g., 16 nm).

[0113] In some embodiments, when the active region structure is formed of a nanowire structure, the transistors fabricated in the active region structure are nanowire transistors. The number of nanowires in the strong PMOS active region structure 220P having a p-channel strong transistor is greater than the number of nanowires in the weak PMOS active region structure 230P having a p-channel weak transistor, and the number of nanowires in the strong NMOS active region structure 220N having an n-channel strong transistor is greater than the number of nanowires in the weak NMOS active region structure 230N having an n-channel weak transistor.

[0114] In some embodiments, each of the active region structures is characterized by a structural width measured along the Y direction perpendicular to the X direction. The structural width of the strong PMOS active region structure 220P having a p-channel strong transistor is greater than the structural width of the weak PMOS active region structure 230P having a p-channel weak transistor, and the structural width of the strong NMOS active region structure 220N having an n-channel strong transistor is greater than the structural width of the weak NMOS active region structure 230N having an n-channel weak transistor. As a specific example, in some embodiments, when the number of fins in the strong PMOS active region structure 220P is greater than the number of fins in the weak PMOS active region structure 230P, the structural width of the strong PMOS active region structure 220P is also greater than the structural width of the weak PMOS active region structure 230P; when the number of fins in the strong NMOS active region structure 220N is greater than the number of fins in the weak NMOS active region structure 230N, the structural width of the strong NMOS active region structure 220N is also greater than the structural width of the weak NMOS active region structure 230N.

[0115] exist Figure 2In order to drive the first clocked forwarding switch 103 (e.g., transmission gate 110F1), the same-phase clock signal CPBB is applied to the gate conductor 272F1 intersecting the strong PMOS active region structure 220P, and the reverse-phase clock signal CPB is applied to the gate conductor 274F1 intersecting the strong NMOS active region structure 220N. To drive the clocked inverter 110F2, the same-phase clock signal CPBB is applied to the gate conductor 272F2 intersecting the weak NMOS active region structure 230N, and the reverse-phase clock signal CPB is applied to the gate conductor 274F2 intersecting the weak PMOS active region structure 230P. The output of the first clocked forwarding switch 103 (e.g., transmission gate 110F1) is conductively connected to the output of the clocked inverter 110F2 via the connecting conductor 250 extending in the Y direction.

[0116] exist Figure 2 In order to drive the second clock-controlled forwarding switch 105 (e.g., gated inverter 105H1 or transmission gate 110H1), the same-phase clock signal CPBB is applied to the gate conductor 272H1 intersecting the strong NMOS active region structure 220N, and the reverse-phase clock signal CPB is applied to the gate conductor 274H1 intersecting the strong PMOS active region structure 220P. To drive the clock-controlled inverter 110H2, the same-phase clock signal CPBB is applied to the gate conductor 272H2 intersecting the weak PMOS active region structure 230P, and the reverse-phase clock signal CPB is applied to the gate conductor 274H2 intersecting the weak NMOS active region structure 230N. The output of the second clock-controlled forwarding switch 105 (e.g., gated inverter 105H1 or transmission gate 110H1) is conductively connected to the output of the clock-controlled inverter 110H2 via the connecting conductor 260 extending in the Y direction.

[0117] FIG. 3A to FIG. 3D , FIG. 4A to FIG. 4D and FIG. 5A to FIG. 5D According to some embodiments Figure 2 Schematic diagram of cross-sectional views of an integrated circuit in various cutting planes. In the cross-sectional view of the cutting plane A-A', as shown in FIG. Figure 3A , Figure 4A and Figure 5A As shown, the gate conductors 272F1 and 274H1 intersect the strong PMOS active region structure 220P at the p-channel regions of the strong transistors TpF1 and TpH1, respectively. Figure 3B , Figure 4B and Figure 5B As shown, each of the gate conductors 274F1 and 272H1 intersects the strong NMOS active region structure 220N at the n-channel region of the strong transistors TnF1 and TnH1, respectively. Figures 3C to 5C As shown, the gate conductors 272F2 and 274H2 intersect the weak NMOS active region structure 230N at the n-channel regions of the weak transistors TnF2 and TnH2, respectively. Figures 3D to 5D As shown, each of gate conductors 274F2 and 272H2 intersects weak PMOS active region structure 230P at the p-channel regions of weak transistors TpF2 and TpH2, respectively.

[0118] In some embodiments, FIG. 3A to FIG. 3D As shown, the connection conductor 250 and the connection conductor 260 are implemented as terminal conductors 350MD and 360MD, respectively. The terminal conductor 350MD intersects the strong active region structures 220P and 220N at the drain regions of the strong transistors TpF1 and TnF1, respectively. The terminal conductor 350MD also intersects the weak active region structures 230N and 230P at the drain regions of the weak transistors TnF2 and TpF2, respectively. The terminal conductor 360MD intersects the strong active region structures 220P and 220N at the drain regions of the strong transistors TpH1 and TnH1, respectively. The terminal conductor 360MD also intersects the weak active region structures 230N and 230P at the drain regions of the weak transistors TnH2 and TpH2, respectively. The terminal conductors 350MD and 360MD are covered with an interlayer dielectric ILD0, and a first metal layer (eg, metal layer M0) having conductive lines is deposited on the interlayer dielectric ILD0. The interlayer dielectric ILD0 also covers various gate conductors.

[0119] In some embodiments, FIG. 4A to FIG. 4D As shown, the connection conductor 250 and the connection conductor 260 are implemented as vertical conductive lines 450M0 and 460M0 extending along the Y direction in a first metal layer (e.g., metal layer M0) deposited on an interlayer dielectric ILD0 (which covers various gate conductors and terminal conductors). FIG. 5A to FIG. 5D As shown, the connection conductors 250 and 260 are implemented as vertical conductive lines 550M1 and 560M1 extending along the Y direction in a second metal layer (eg, metal layer M1 ) deposited on an interlayer dielectric ILD1 (which covers various conductive lines in the first metal layer).

[0120] exist Figure 4A and Figure 5A In FIG. 1 , the terminal conductors dTpF1 and dTpH1 intersect the strong PMOS active region structure 220P at the drain regions of the transistors TpF1 and TpH1, respectively. Figure 4B and Figure 5BIn FIG. 1 , the terminal conductors dTnF1 and dTnH1 intersect the strong NMOS active region structure 220N at the drain regions of the strong transistors TnF1 and TnH1 , respectively. Figure 4C and Figure 5C In FIG. 1 , the terminal conductors dTnF2 and dTnH2 intersect the weak NMOS active region structure 230N at the drain regions of the weak transistors TnF2 and TnH2, respectively. Figure 4D and Figure 5D , the terminal conductors dTpF2 and dTpH2 intersect the weak PMOS active region structure 230P at the drain regions of the weak transistors TpF2 and TpH2, respectively.

[0121] exist FIG. 4A to FIG. 4D , vertical conductive lines 450M0 and 460M0 extending in the Y direction are located in a first metal layer (e.g., metal layer M0). Vertical conductive line 450M0 is conductively connected to terminal conductors dTpF1, dTnF1, dTnF2, and dTpF2 using via connectors VD passing through interlayer dielectric ILD0. Vertical conductive line 460M0 is conductively connected to terminal conductors dTpH1, dTnH1, dTnH2, and dTpH2 using via connectors VD passing through interlayer dielectric ILD0.

[0122] exist FIG. 5A to FIG. 5D , vertical conductive lines 550M1 and 560M1 extending in the Y direction are located in the second metal layer (e.g., metal layer M1). The vertical conductive line 550M1 is continuously connected to the terminal conductors dTpF1, dTnF1, dTnF2, and dTpF2 via a first set of metal stubs in the first metal layer (e.g., metal layer M0), and the vertical conductive line 560M1 is conductively connected to the terminal conductors dTpH1, dTnH1, dTnH2, and dTpH2 via a second set of metal stubs in the first metal layer (e.g., metal layer M0).

[0123] Specifically, the vertical conductive line 550M1 is conductively connected to the metal short lines m50pF1, m50nF1, m50nF2 and m50pF2 using a through-hole connector V0 passing through the interlayer dielectric ILD1, and each of the metal short lines m50pF1, m50nF1, m50nF2 and m50pF2 is correspondingly conductively connected to one of the terminal conductors dTpF1, dTnF1, dTnF2 and dTpF2 using a through-hole connector VD passing through the interlayer dielectric ILD0. Similarly, the vertical conductive line 560M1 is conductively connected to the metal stubs m60pH1, m60nH1, m60nH2 and m60pH2 using a through-hole connector V0 passing through the interlayer dielectric ILD1, and each of the metal stubs m60pH1, m60nH1, m60nH2 and m60pH2 is correspondingly conductively connected to one of the terminal conductors dTpH1, dTnH1, dTnH2 and dTpH2 using a through-hole connector VD passing through the interlayer dielectric ILD0.

[0124] exist Figure 2 In the illustrated embodiment, the first type of device (e.g., the first clocked forwarding switch 103 and the second clocked forwarding switch 105) is composed of a p-channel strong transistor and an n-channel strong transistor. The p-channel strong transistor is fabricated in a strong PMOS active region structure 220P, and the n-channel strong transistor is fabricated in a strong NMOS active region structure 220N. In some alternative embodiments, the p-channel strong transistor used to construct the first type of device is fabricated in at least two strong PMOS active region structures. In some alternative embodiments, the n-channel strong transistor used to construct the first type of device is fabricated in at least two strong NMOS active region structures.

[0125] Figure 6 According to some embodiments Figure 1A1 to Figure 1C1 and Figure 1A2 to Figure 1C2 FIG. 1 is a plan view of integrated circuits 100A to 100C in FIG. Figure 6The integrated circuit includes two strong PMOS active region structures 220P[1] to 220P[2] extending in the X direction, two strong NMOS active region structures 220N[1] to 220N[2] extending in the X direction, a weak PMOS active region structure 230P extending in the X direction, and a weak NMOS active region structure 230N extending in the X direction. Each of the input device 101, the first clocked forwarding switch 103, the second clocked forwarding switch 105, and the output driver 109 (respectively located in the layout areas "D", "F1", "F2", and "J") is composed of p-channel strong transistors in the strong PMOS active region structures 220P[1] to 220P[2] and n-channel strong transistors in the NMOS active region structures 220N[1] to 220N[2]. Each of the clocked inverter 110F2 and the clocked inverter 110H2 (located in the layout areas “ F2 ” and “ H2 ”, respectively) is composed of a p-channel weak transistor in the weak PMOS active region structure 230P and an n-channel weak transistor in the weak NMOS active region structure 230N.

[0126] exist Figure 6 , gate conductors 272F1[1] and 272F1[2] intersect strong PMOS active region structures 220P[1] and 220P[2] at the channel region of the p-channel strong transistor, and gate conductors 274F1[1] and 274F1[2] intersect strong NMOS active region structures 220N[1] and 220N[2] at the channel region of the n-channel strong transistor, respectively. Gate conductors 272F2[1] and 272F2[2] intersect strong NMOS active region structures 220N[1] and 220N[2] at the channel region of the n-channel strong transistor, and gate conductors 274F2[1] and 274F2[2] intersect strong PMOS active region structures 220P[1] and 220P[2] at the channel region of the p-channel strong transistor, respectively.

[0127] exist Figure 6 In order to drive the first clocked forwarding switch 103 (e.g., transmission gate 110F1), the same-phase clock signal CPBB is applied to gate conductors 272F1[1] to 272F1[2], and the opposite-phase clock signal CPB is applied to gate conductors 274F1[1] to 274F1[2]. In order to drive the second clocked forwarding switch 105 (e.g., gated inverter 105H1 or transmission gate 110H1), the same-phase clock signal CPBB is applied to gate conductors 272H1[1] to 272H1[2], and the opposite-phase clock signal CPB is applied to gate conductors 274H1[1] to 274H1[2].

[0128] exist Figure 6In order to drive the timing inverter 110F2 and the timing inverter 110H2, Figure 2 The same method as in the above is used to apply the same phase clock signal CPBB and the opposite phase clock signal CPB to each gate conductor. Figure 6 and Figure 2 In both, the output of the first clocked forwarding switch 103 is conductively connected to the output of the clocked inverter 110F2 via the connecting conductor 250 , and the output of the second clocked forwarding switch 105 is conductively connected to the output of the clocked inverter 110H2 via the connecting conductor 260 .

[0129] exist Figure 6 In the embodiment, two strong transistors having gate conductors 272F1[1] to 272F1[2] are connected in parallel with each other, and two strong transistors having gate conductors 274F1[1] to 274F1[2] are connected in parallel with each other. The two strong transistors having gate conductors 272F1[1] to 272F1[2] replace Figure 2 The strong transistor TpF1 having gate conductor 272F1 in the embodiment of the present invention and the two strong transistors having gate conductors 274F1[1] to 274F1[2] replace Figure 2 The strong transistor TnF1 with 274F1 will increase Figure 6 Here, increasing the driving strength of the first time-controlled forward switch 103 will increase the driving strength of the first time-controlled forward switch 103 according to Figure 6 The switching speed of the master and slave flip-flops implemented by the floor design.

[0130] Similarly, in Figure 6 In the embodiment, two strong transistors having gate conductors 272H1[1] to 272H1[2] are connected in parallel with each other, and two strong transistors having gate conductors 274H1[1] to 274H1[2] are connected in parallel with each other. The two strong transistors having gate conductors 272H1[1] to 272H1[2] replace Figure 2 The strong transistor TnH1 having gate conductor 272H1 and the two strong transistors having gate conductors 272H1[1] to 274H1[2] replace Figure 2 The strong transistor TpH1 having gate conductor 274H1 in the embodiment of FIG. Figure 6 Here, increasing the driving strength of the second time-controlled forwarding switch 105 will increase the driving strength of the second time-controlled forwarding switch 105 according to Figure 6 The switching speed of the master and slave flip-flops implemented by the planar design.

[0131] In addition, due to the two strong PMOS active region structures 220P[1]-220P[2] and the two strong NMOS active region structures 220N[1]-220N[2], stronger transistors are available for constructing the input device 101 and the output driver 109 (which are located in the layout areas "D" and "J" respectively) to increase the drive strength of the input device 101 and the drive strength of the output driver 109. Increasing the drive strength at the output of the input device 101 will improve the output of the input device 101. Figure 6 Graphic design implemented by Figure 1A1 to Figure 1C1 and Figure 1A2 to Figure 1C2 Increasing the drive strength at the output of the output driver 109 will reduce the RC delay at the output of the output driver 109.

[0132] In some alternative embodiments, according to Figure 6 An integrated circuit implemented by a planar design of the present invention is modified to incorporate some of the strong active region structures. Figure 7 According to some embodiments Figure 1A1 to Figure 1C1 and Figure 1A2 to Figure 1C2 FIG. 1 is a plan view of integrated circuits 100A to 100C in FIG. Figure 7 The strong PMOS active region structure 220Pm is composed of a combined Figure 6 In addition, gate conductors 272F1[1] and 272F1[2] are replaced by merged gate conductor 272F1m, and gate conductors 274H1[1] and 274H1[2] are replaced by merged gate conductor 274H1m.

[0133] exist Figure 6 In the embodiment, the strong PMOS active region structures 220P[1] and 220P[2] are adjacent to each other, and the strong PMOS active region structures 220P[1] and 220P[2] are positioned between the two strong NMOS active region structures 220N[1] and 220N[2]. In some alternative embodiments (not shown), the strong NMOS active region structures 220N[1] and 220N[2] are adjacent to each other, and the strong NMOS active region structures 220N[1] and 220N[2] are positioned between the two strong PMOS active region structures 220P[1] and 220P[2]. In some alternative embodiments (not shown), the strong NMOS active region structures 220N[1] and 220N[2] are merged into one strong NMOS active region structure 220Nm, and the one strong NMOS active region structure 220Nm is positioned between the two strong PMOS active region structures 220P[1] and 220P[2].

[0134] Figure 8is a flow chart of a method 800 of fabricating an integrated circuit according to some embodiments. Figure 8 The order in which the operations of method 800 are shown is for illustration only; the operations of method 800 may be performed in the same order as described above. Figure 8 It should be understood that the sequence may be different from the sequence shown in FIG. Figure 8 Additional operations may be performed before, during, and / or after the method 800 depicted in the drawings, and some other processes may be only briefly described herein.

[0135] In operation 810 of method 800, a strong first type active region structure and a weak first type active region structure extending in the X direction are fabricated. In operation 820 of method 800, a strong second type active region structure and a weak second type active region structure extending in the X direction are fabricated. Figure 2 and FIG. 3A to FIG. 3D In the exemplary embodiment shown, a strong PMOS active region structure 220P and a weak PMOS active region structure 230P are fabricated in operation 810 (or alternatively in operation 820), and a strong NMOS active region structure 220N and a weak NMOS active region structure 230N are fabricated in operation 820 (or alternatively in operation 810). After operations 810 and 820, the fabrication process proceeds to operations 830 and 840.

[0136] In operation 830 of method 800, a first clocked forwarding switch and a second clocked forwarding switch are formed using strong first type transistors in a strong first type active region structure and strong second type transistors in a strong second type active region structure. Figure 2 and FIG. 3A to FIG. 3D In the exemplary embodiment shown, the first time-controlled forwarding switch F1 and the second time-controlled forwarding switch F2 are formed using strong PMOS transistors in the strong PMOS active region structure 220P and strong NMOS transistors in the strong NMOS active region structure 220N. In operation 840 of method 800, the first time-controlled inverter and the second time-controlled inverter are formed using weak first-type transistors in the weak first-type active region structure and weak second-type transistors in the weak second-type active region structure. Figure 2 and FIG. 3A to FIG. 3D In the exemplary embodiment shown, the clocked inverter 110F2 and the clocked inverter 110H2 are formed using weak PMOS transistors in the weak PMOS active region structure 230P and weak NMOS transistors in the weak NMOS active region structure 230N. After operations 830 and 840, the fabrication process proceeds to operations 850 and 860.

[0137] In operation 850 of method 800, the output of the first clocked forwarding switch is connected to the output of the first clocked inverter. In operation 860 of method 800, the output of the second clocked forwarding switch is connected to the output of the second clocked inverter. Figure 2 and FIG. 3A to FIG. 3D In the first exemplary embodiment shown, when the terminal conductor 350MD is made to intersect the strong active region structure (i.e., 220P and 220N) and the weak active region structure (i.e., 230P and 230N), the output of the first clocked forward switch F1 is connected to the output of the first clocked inverter F2. When the terminal conductor 360MD is made to intersect the strong active region structure (i.e., 220P and 220N) and the weak active region structure (i.e., 230P and 230N), the output of the second clocked forward switch H1 is connected to the output of the second clocked inverter H2.

[0138] In such Figure 2 and FIG. 4A to FIG. 4D In another exemplary embodiment shown, when the vertical conductive line 450M0 is made in operation 860, the vertical conductive line 450M0 is made to be connected to each of the terminal conductors dTpF1, dTnF1, dTnF2, and dTpF2 using a through-hole connection, thereby connecting the output of the first clocked forwarding switch F1 to the output of the first clocked inverter F2. When the vertical conductive line 460M0 is made, the vertical conductive line 460M0 is connected to each of the terminal conductors dTpH1, dTnH1, dTnH2, and dTpH2 using a through-hole connection VD, thereby connecting the output of the second clocked forwarding switch H1 to the output of the second clocked inverter H2.

[0139] Fig. 9 is a block diagram of an electronic design automation (EDA) system 900 according to some embodiments.

[0140] In some embodiments, the EDA system 900 includes an automatic placement and routing (APR) system. According to some embodiments, the method of designing a layout diagram representing a wiring arrangement according to one or more embodiments described herein can be implemented, for example, using the EDA system 900.

[0141] In some embodiments, the EDA system 900 is a general-purpose computing device including a hardware processor 902 and a non-transitory computer-readable storage medium 904. The storage medium 904 is encoded with (i.e., stores) computer program code 906 (i.e., an executable instruction set), etc. The execution of the instructions 906 by the hardware processor 902 represents an EDA tool that (at least partially) implements a part or all of the method described herein (hereinafter, the proposed process and / or method) according to one or more embodiments.

[0142] The processor 902 is electrically coupled to the computer readable storage medium 904 via a bus 908. The processor 902 is also electrically coupled to an I / O interface 910 by the bus 908. A network interface 912 is also electrically connected to the processor 902 via the bus 908. The network interface 912 is connected to a network 914 so that the processor 902 and the computer readable storage medium 904 can be connected to external components via the network 914. The processor 902 is configured to execute computer program code 906 encoded in the computer readable storage medium 904 so that the system 900 can be used to implement part or all of the proposed process and / or method. In one or more embodiments, the processor 902 is a central processing unit (CPU), a multiprocessor, a distributed processing system, an application specific integrated circuit (ASIC), and / or a suitable processing unit.

[0143] In one or more embodiments, the computer-readable storage medium 904 is an electronic, magnetic, optical, electromagnetic, infrared, and / or semiconductor system (or device or apparatus). For example, the computer-readable storage medium 904 includes semiconductor or solid-state memory, magnetic tape, removable computer disk, random access memory (RAM), read-only memory (ROM), hard disk, and / or optical disk. In one or more embodiments using optical disks, the computer-readable storage medium 904 includes compact disk-read only memory (CD-ROM), compact disk-read / write (CD-R / W), and / or digital video disc (DVD).

[0144] In one or more embodiments, the storage medium 904 stores computer program code 906, which is configured to enable the system 900 (where such execution represents (at least in part) an EDA tool) to be used to implement part or all of the proposed process and / or method. In one or more embodiments, the storage medium 904 also stores information that facilitates the implementation of part or all of the proposed process and / or method. In one or more embodiments, the storage medium 904 stores a standard cell library 907 including such standard cells disclosed herein. In one or more embodiments, the storage medium 904 stores one or more layout drawings 909 corresponding to one or more layouts disclosed herein.

[0145] The EDA system 900 includes an I / O interface 910. The I / O interface 910 is coupled to an external circuit system. In one or more embodiments, the I / O interface 910 includes a keyboard, a keypad, a mouse, a trackball, a trackpad, a touch screen, and / or cursor arrow keys for transmitting information and commands to the processor 902.

[0146] The EDA system 900 also includes a network interface 912 coupled to the processor 902. The network interface 912 enables the system 900 to communicate with a network 914 connected to one or more other computer systems. The network interface 912 includes a wireless network interface, such as BLUETOOTH, wireless fidelity (WIFI), Worldwide Interoperability for Microwave Access (WIMAX), General Packet Radio Service (GPRS), or wideband code division multiple access (WCDMA); or a wired network interface, such as Ethernet (ETHERNET), universal serial bus (USB), or Institute of Electrical and Electronic Engineers-1364 (IEEE-1364). In one or more embodiments, part or all of the proposed process and / or method is implemented in two or more systems 900.

[0147] The system 900 is configured to receive information via an I / O interface 910. The information received via the I / O interface 910 includes one or more of instructions, data, design rules, standard cell libraries, and / or other parameters processed by the processor 902. The information is delivered to the processor 902 via a bus 908. The EDA system 900 is configured to receive information related to a user interface (UI) via the I / O interface 910. The information is stored in a computer-readable medium 904 as a UI 942.

[0148] In some embodiments, part or all of the proposed processes and / or methods are implemented as a stand-alone software application executed by a processor. In some embodiments, part or all of the proposed processes and / or methods are implemented as a software application that is part of an additional software application. In some embodiments, part or all of the proposed processes and / or methods are implemented as a plug-in to a software application. In some embodiments, at least one of the proposed processes and / or methods is implemented in the form of a software application that is part of an EDA tool. In some embodiments, part or all of the proposed processes and / or methods are implemented in the form of a software application used by the EDA system 900. In some embodiments, a tool (e.g., a software application available from Cadence Design Systems, Inc.) is used to implement the proposed processes and / or methods. or another suitable layout generation tool) to generate a layout diagram including standard cells.

[0149] In some embodiments, the process is implemented in the functional form of a program stored in a non-transitory computer-readable recording medium. Examples of non-transitory computer-readable recording media include, but are not limited to, external / removable and / or internal / built-in storage units or memory units, such as one or more of optical disks (e.g., DVDs), magnetic disks (e.g., hard disks), semiconductor memories (e.g., ROM, RAM), memory cards, and the like.

[0150] Fig.10 1 is a block diagram of an integrated circuit (IC) manufacturing system 1000 and an IC manufacturing process associated therewith according to some embodiments. In some embodiments, based on the layout diagram, the manufacturing system 1000 is used to fabricate at least one of the following: (A) one or more semiconductor masks; or (B) at least one component in a layer of a semiconductor integrated circuit.

[0151] exist Fig.10In the embodiment of the present invention, the IC manufacturing system 1000 includes entities that interact with each other in the design, development and manufacturing cycle and / or services related to manufacturing IC devices 1060, such as a design division 1020, a mask division 1030 and an IC manufacturing plant / fab 1050. The entities in the system 1000 are connected by a communication network. In some embodiments, the communication network is a single network. In some embodiments, the communication network is a variety of different networks, such as an intranet and the Internet. The communication network includes wired and / or wireless communication channels. Each entity interacts with one or more of the other entities and provides services to one or more of the other entities and / or receives services from one or more of the other entities. In some embodiments, a single larger company owns two or more of the design division 1020, the mask division 1030 and the IC manufacturing plant 1050. In some embodiments, two or more of the design division 1020, the mask division 1030, and the IC fabrication facility 1050 are co-located in a common facility and use common resources.

[0152] The design division (or design team) 1020 generates an IC design layout 1022. The IC design layout 1022 includes various geometric patterns designed for the IC device 1060. The geometric patterns correspond to patterns of metal layers, oxide layers, or semiconductor layers that constitute various components of the IC device 1060 to be manufactured. The various layers are combined to form various IC features. For example, a portion of the IC design layout 1022 includes various IC features to be formed in a semiconductor substrate (e.g., a silicon wafer) (e.g., active regions, gate electrodes, source and drain electrodes, metal wires or vias of interlayer interconnects, and openings for bonding pads) and various material layers disposed on the semiconductor substrate. The design division 1020 implements an appropriate design program to form the IC design layout 1022. The design program includes one or more of a logical design, a physical design, or placement and routing. The IC design layout 1022 exists in one or more data files with information of geometric patterns. For example, the IC design layout 1022 can be expressed in a GDSII file format or a DFII file format.

[0153] The mask division 1030 includes data preparation 1032 and mask production 1044. The mask division 1030 uses the IC design layout 1022 to manufacture one or more masks 1045 according to the IC design layout 1022 for use in manufacturing various layers of the IC device 1060. The mask division 1030 performs mask data preparation 1032, wherein the IC design layout 1022 is converted into a representative data file (RDF). The mask data preparation 1032 provides the RDF to the mask production 1044. The mask production 1044 includes a mask writer. The mask writer converts the RDF into an image on a substrate, such as a mask (reticle) 1045 or a semiconductor wafer 1053. The mask data preparation 1032 manipulates the design layout 1022 to comply with specific characteristics of the mask writer and / or requirements of the IC manufacturing plant 1050. In Fig.10 In FIG. 1 , mask data preparation 1032 and mask production 1044 are shown as separate components. In some embodiments, mask data preparation 1032 and mask production 1044 may be collectively referred to as mask data preparation.

[0154] In some embodiments, mask data preparation 1032 includes optical proximity correction (OPC), which uses lithography enhancement techniques to compensate for image errors, such as those that may be caused by diffraction, interference, other process effects, and the like. OPC adjusts IC design layout 1022. In some embodiments, mask data preparation 1032 further includes resolution enhancement techniques (RET), such as off-axis illumination, sub-resolution assist features, phase-shifting masks, other suitable techniques, and the like, or combinations thereof. In some embodiments, inverse lithography technology (ILT) is also utilized, which treats OPC as an inverse imaging problem.

[0155] In some embodiments, mask data preparation 1032 includes a mask rule checker (MRC) that uses a set of mask creation rules containing certain geometric and / or connectivity constraints to check the IC design layout 1022 that has been subjected to the OPC process to ensure sufficient margins to account for variability in semiconductor manufacturing processes, etc. In some embodiments, the MRC modifies the IC design layout 1022 to compensate for the effects of lithography during mask fabrication 1044, which may cancel a portion of the modifications performed by the OPC to satisfy the mask creation rules.

[0156] In some embodiments, mask data preparation 1032 includes lithography process checking (LPC), which simulates the process to be performed by IC fabrication plant 1050 to fabricate IC device 1060. LPC simulates this process based on IC design layout 1022 to create a simulated finished device, such as IC device 1060. Process parameters in LPC simulations may include parameters associated with various processes of an IC manufacturing cycle, parameters associated with tools used to fabricate ICs, and / or other aspects of the manufacturing process. LPC takes into account various factors, such as aerial image contrast, depth of focus (DOF), mask error enhancement factor (MEEF), other suitable factors, and the like, or combinations thereof. In some embodiments, after a simulated finished device has been created by LPC, if the shape similarity of the simulated device is not sufficient to meet the design rules, OPC and / or MRC are repeated to further improve IC design layout 1022.

[0157] It should be understood that the above description of mask data preparation 1032 has been simplified for clarity. In some embodiments, data preparation 1032 includes additional features, such as modifying logic operations (LOPs) of IC design layout 1022 according to manufacturing rules. In addition, the processes applied to IC design layout 1022 during data preparation 1032 may be performed in a variety of different orders.

[0158] After the mask data preparation 1032 and during the mask fabrication 1044, a mask 1045 or a set of masks 1045 are fabricated based on the modified IC design layout 1022. In some embodiments, the mask fabrication 1044 includes performing one or more lithographic exposures based on the IC design layout 1022. In some embodiments, an electron-beam (e-beam) or a mechanism consisting of multiple electron beams is used to form a pattern on the mask (photomask or stencil) 1045 based on the modified IC design layout 1022. The mask 1045 can be formed by various techniques. In some embodiments, the mask 1045 is formed using a binary technique. In some embodiments, the mask pattern includes opaque areas and transparent areas. A radiation beam (e.g., an ultraviolet (UV) beam) used to expose an image-sensitive material layer (e.g., a photoresist) coated on a wafer is blocked by the opaque areas and transmitted through the transparent areas. In one example, a binary mask version of the mask 1045 includes a transparent substrate (e.g., fused silica) and an opaque material (e.g., chromium) coated in the opaque areas of the binary mask. In another example, the mask 1045 is formed using a phase shift technique. In a phase shift mask (PSM) version of the mask 1045, various features in the pattern formed on the phase shift mask are configured to have appropriate phase differences to enhance resolution and imaging quality. In various examples, the phase shift mask can be an attenuated PSM or an alternating PSM. The mask produced by the mask making 1044 is used in various processes. For example, such a mask is used in an ion implantation process to form various doped regions in the semiconductor wafer 1053, in an etching process to form various etched regions in the semiconductor wafer 1053, and / or in other suitable processes.

[0159] IC fabrication plant 1050 is an IC fabrication enterprise that includes one or more fabrication facilities for fabricating various IC products. In some embodiments, IC fabrication plant 1050 is a semiconductor foundry. For example, there may be a fabrication facility for front-end fabrication (front-end-of-line, FEOL) fabrication) of multiple IC products, while a second fabrication facility may provide back-end fabrication (back-end-of-line, BEOL) fabrication for interconnection and packaging of IC products, and a third fabrication facility may provide other services for the foundry enterprise.

[0160] IC fabrication facility 1050 includes fabrication tool 1052 configured to perform various fabrication operations on semiconductor wafer 1053, thereby fabricating IC device 1060 based on a mask (e.g., mask 1045). In various embodiments, fabrication tool 1052 includes one or more of the following: a wafer stepper, an ion implanter, a photoresist coater, a process chamber (e.g., a chemical vapor deposition (CVD) chamber or a low pressure chemical vapor deposition (LPCVD) furnace), a chemical mechanical polishing (CMP) system, a plasma etching system, a wafer cleaning system, or other fabrication equipment capable of performing one or more suitable fabrication processes discussed herein.

[0161] IC fabrication plant 1050 uses mask 1045 fabricated by mask division 1030 to fabricate IC device 1060. Therefore, IC fabrication plant 1050 at least indirectly uses IC design layout 1022 to fabricate IC device 1060. In some embodiments, IC fabrication plant 1050 uses mask 1045 to fabricate semiconductor wafer 1053 to form IC device 1060. In some embodiments, IC fabrication includes performing one or more lithography exposures based at least indirectly on IC design layout 1022. Semiconductor wafer 1053 includes a silicon substrate or other appropriate substrate having a material layer formed thereon. Semiconductor wafer 1053 further includes one or more of various doped regions, dielectric features, multilevel interconnects, and similar components (formed at subsequent manufacturing steps).

[0162] One aspect of the present disclosure is related to an integrated circuit. The integrated circuit includes a first time-controlled forwarding switch and a second time-controlled forwarding switch, each of which is implemented using a strong transistor, and includes a first time-controlled inverter and a second time-controlled inverter, each of which is implemented using a weak transistor. The output of the first time-controlled forwarding switch is conductively connected to the output of the first time-controlled inverter, and the output of the second time-controlled forwarding switch is conductively connected to the output of the second time-controlled inverter. The integrated circuit also includes a strong active region structure extending in a first direction and a weak active region structure extending in the first direction. Each of the strong active region structures has a portion of a strong transistor, and each of the weak active region structures has a portion of a weak transistor. The integrated circuit further includes a first inverter, the first inverter having an input conductively connected to the output of the first time-controlled inverter and an output conductively connected to the input of the first time-controlled inverter. The integrated circuit also includes a second inverter, the second inverter having an input conductively connected to the output of the second time-controlled inverter and an output conductively connected to the input of the second time-controlled inverter.

[0163] In one embodiment of the present disclosure, the strong active region structure includes at least two strong first type active region structures and at least one strong second type active region structure. In one embodiment of the present disclosure, the strong active region structure includes at least two strong first type active region structures and at least two strong second type active region structures. In one embodiment of the present disclosure, the integrated circuit further includes an input device and an output driver. The input device has an output conductively connected to the input of the first timing forwarding switch. The output driver has an input conductively connected to the output of the second inverter. In one embodiment of the present disclosure, each of the input device and the output driver is implemented using a strong transistor. In one embodiment of the present disclosure, one of the input device or the output driver is implemented using a strong transistor. In one embodiment of the present disclosure, the first timing forwarding switch is a transmission gate coupled between the output of the input device and the input of the first inverter. In one embodiment of the present disclosure, the second timing forwarding switch is a transmission gate coupled between the output of the first inverter and the input of the second inverter. In one embodiment of the present disclosure, the second timing forwarding switch is a third timing inverter coupled between the input of the first inverter and the input of the second inverter. In one embodiment of the present disclosure, the first inverter is a resettable inverter, and the second clocked inverter is a resettable clocked inverter. In one embodiment of the present disclosure, each of the first inverter and the second inverter is an inverter.

[0164] In one embodiment of the present disclosure, the strong active region structure and the weak active region structure are fin-shaped structures each associated with a plurality of fins. The number of fins in the strong active region structure having a p-channel strong transistor is greater than the number of fins in the weak active region structure having a p-channel weak transistor. The number of fins in the strong active region structure having an n-channel strong transistor is greater than the number of fins in the weak active region structure having an n-channel weak transistor.

[0165] In one embodiment of the present disclosure, the strong active region structure and the weak active region structure are nanosheet structures each associated with a plurality of nanosheets, wherein the number of nanosheets in the strong active region structure having p-channel strong transistors is greater than the number of nanosheets in the weak active region structure having p-channel weak transistors, and wherein the number of nanosheets in the strong active region structure having n-channel strong transistors is greater than the number of nanosheets in the weak active region structure having n-channel weak transistors.

[0166] In one embodiment of the present disclosure, the strong active region structure and the weak active region structure are nanowire structures each associated with a plurality of nanowires, wherein the number of nanowires in the strong active region structure having a p-channel strong transistor is greater than the number of nanowires in the weak active region structure having a p-channel weak transistor, and wherein the number of nanowires in the strong active region structure having an n-channel strong transistor is greater than the number of nanowires in the weak active region structure having an n-channel weak transistor.

[0167] In one embodiment of the present disclosure, each of the strong active region structure and the weak active region structure has a structure width measured along a second direction perpendicular to the first direction. The structure width of the strong active region structure having a p-channel strong transistor is greater than the structure width of the weak active region structure having a p-channel weak transistor. The structure width of the strong active region structure having an n-channel strong transistor is greater than the structure width of the weak active region structure having an n-channel weak transistor.

[0168] Another aspect of the present disclosure is related to an integrated circuit. The integrated circuit includes a first time-controlled forwarding switch and a second time-controlled forwarding switch, each of which is implemented using a strong transistor, and includes a first time-controlled inverter and a second time-controlled inverter, each of which is implemented using a weak transistor. The integrated circuit also includes a strong active region structure extending in a first direction and having a strong transistor therein, and a weak active region structure extending in a first direction and having a weak transistor therein. The average gate width of the strong transistor with a p-channel is greater than the average gate width of the weak transistor with a p-channel, and the average gate width of the strong transistor with an n-channel is greater than the average gate width of the weak transistor with an n-channel. The integrated circuit further includes a first connecting conductor and a second connecting conductor, each extending in a second direction perpendicular to the first direction. The first connecting conductor conductively connects the output of the first time-controlled forwarding switch to the output of the first time-controlled inverter. The second connecting conductor conductively connects the output of the second time-controlled forwarding switch to the output of the second time-controlled inverter. The integrated circuit also includes a first inverter coupled between the input of the first time-controlled inverter and the first connecting conductor, wherein the first inverter has an input conductively connected to the first connecting conductor. The integrated circuit also includes a second inverter coupled between an input of the second clocked inverter and the second connecting conductor, wherein the second inverter has an input conductively connected to the second connecting conductor.

[0169] In one embodiment of the present disclosure, the integrated circuit further includes an input device and an output driver. The input device has an output conductively connected to the input of the first time-controlled forwarding switch. The output driver has an input conductively connected to the output of the second inverter.

[0170] Another aspect of the present disclosure is related to a method. The method includes: making a strong first type active region structure and a weak first type active region structure extending in a first direction, and making a strong second type active region structure and a weak second type active region structure extending in the first direction. The method also includes: using a strong first type transistor in the strong first type active region structure and a strong second type transistor in the strong second type active region structure to form a first time-controlled forwarding switch and a second time-controlled forwarding switch, and using a weak first type transistor in the weak first type active region structure and a weak second type transistor in the weak second type active region structure to form a first time-controlled inverter and a second time-controlled inverter. The average gate width of the strong first type transistor is greater than the average gate width of the weak first type transistor, and the average gate width of the strong second type transistor is greater than the average gate width of the weak second type transistor. The method also includes: connecting the output of the first time-controlled forwarding switch to the output of the first time-controlled inverter, and connecting the output of the second time-controlled forwarding switch to the output of the second time-controlled inverter.

[0171] In an embodiment of the present disclosure, the method further includes: connecting the input of the first inverter to the output of the first clocked inverter; and connecting the output of the first inverter to the input of the first clocked inverter.

[0172] In an embodiment of the present disclosure, the method further includes: connecting the input of the second inverter to the output of the second clocked inverter; and connecting the output of the second inverter to the input of the second clocked inverter.

[0173] It will be readily apparent to one of ordinary skill in the art that one or more of the disclosed embodiments achieve one or more of the above advantages. After reading the foregoing description, one of ordinary skill in the art will be able to implement the various variations, substitutions of equivalents, and various other embodiments broadly disclosed herein. Accordingly, it is intended that the protection granted herein be limited only by the definitions contained in the appended claims and their equivalents.

Claims

1. An integrated circuit, characterized in that: The integrated circuit comprises: The first time-controlled forwarding switch and the second time-controlled forwarding switch are each implemented using a strong transistor; A first time-controlled inverter and a second time-controlled inverter, each implemented using a weak transistor, wherein the output of the first time-controlled forwarding switch is conductively connected to the output of the first time-controlled inverter, and wherein the output of the second time-controlled forwarding switch is conductively connected to the output of the second time-controlled inverter; Strong active region structures extending in a first direction, wherein each of the strong active region structures has a portion of the strong transistor; Weakly active region structures extending in the first direction, wherein each of the weakly active region structures has a portion of the weak transistor; a first inverter having an input conductively connected to the output of the first clocked inverter and having an output conductively connected to the input of the first clocked inverter; and A second inverter has an input conductively connected to the output of the second clocked inverter and has an output conductively connected to the input of the second clocked inverter.

2. The integrated circuit according to claim 1, characterized in that The integrated circuit further comprises: an input device having an output conductively connected to an input of the first clocked repeater switch; and An output driver has an input conductively connected to the output of the second inverter.

3. The integrated circuit according to claim 1, characterized in that The first time-controlled forwarding switch is a transmission gate coupled between an output of an input device and the input of the first inverter.

4. The integrated circuit according to claim 1, characterized in that The second time-controlled forwarding switch is a transmission gate coupled between the output of the first inverter and the input of the second inverter.

5. The integrated circuit according to claim 1, characterized in that The strong active region structure and the weak active region structure are fin-shaped structures each associated with a plurality of fins, wherein the number of fins in the strong active region structure having a p-channel strong transistor is greater than the number of fins in the weak active region structure having a p-channel weak transistor, and wherein the number of fins in the strong active region structure having an n-channel strong transistor is greater than the number of fins in the weak active region structure having an n-channel weak transistor.

6. The integrated circuit according to claim 1, characterized in that The strong active region structure and the weak active region structure are nanosheet structures each associated with a plurality of nanosheets, wherein the number of nanosheets in the strong active region structure having p-channel strong transistors is greater than the number of nanosheets in the weak active region structure having p-channel weak transistors, and wherein the number of nanosheets in the strong active region structure having n-channel strong transistors is greater than the number of nanosheets in the weak active region structure having n-channel weak transistors.

7. The integrated circuit according to claim 1, characterized in that The strong active region structure and the weak active region structure are nanowire structures each associated with a plurality of nanowires, wherein the number of nanowires in the strong active region structure having a p-channel strong transistor is greater than the number of nanowires in the weak active region structure having a p-channel weak transistor, and wherein the number of nanowires in the strong active region structure having an n-channel strong transistor is greater than the number of nanowires in the weak active region structure having an n-channel weak transistor.

8. The integrated circuit according to claim 1, characterized in that Each of the strong active region structure and the weak active region structure has a structure width measured along a second direction perpendicular to the first direction, wherein the structure width of the strong active region structure having a p-channel strong transistor is greater than the structure width of the weak active region structure having a p-channel weak transistor, and wherein the structure width of the strong active region structure having an n-channel strong transistor is greater than the structure width of the weak active region structure having an n-channel weak transistor.

9. An integrated circuit, characterized in that: The integrated circuit comprises: The first time-controlled forwarding switch and the second time-controlled forwarding switch are each implemented using a strong transistor; The first clocked inverter and the second clocked inverter are each implemented using a weak transistor; a strong active region structure extending in a first direction and having the strong transistor in the strong active region structure; a weak active region structure extending in the first direction and having the weak transistors in the weak active region structure, wherein an average gate width of the strong transistors having a p-channel is greater than an average gate width of the weak transistors having a p-channel, and wherein an average gate width of the strong transistors having an n-channel is greater than an average gate width of the weak transistors having an n-channel; a first connecting conductor extending in a second direction perpendicular to the first direction, wherein the first connecting conductor conductively connects the output of the first time-controlled forwarding switch to the output of the first time-controlled inverter; a second connecting conductor extending in the second direction, wherein the second connecting conductor conductively connects the output of the second time-controlled forwarding switch to the output of the second time-controlled inverter; A first inverter coupled between an input of the first clocked inverter and the first connecting conductor, wherein the first inverter has an input conductively connected to the first connecting conductor; and The second inverter is coupled between the input of the second clocked inverter and the second connecting conductor, wherein the second inverter has an input conductively connected to the second connecting conductor.

10. The integrated circuit according to claim 9, characterized in that The integrated circuit further comprises: an input device having an output conductively connected to an input of the first clocked forwarding switch; and an output driver having an input conductively connected to an output of the second inverter.

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