Semiconductor device

Abstract

The utility model discloses a semiconductor device which comprises a substrate, a plurality of plug structures, a plurality of gate line structures, a metal silicide layer, a plurality of bonding pads and a plurality of bonding pad intervals. The plug structures and the gate line structures are alternately disposed on the substrate. A metal silicide layer is disposed on and physically contacts the plug structure. A pad is disposed on the metal silicide layer and physically contacts the metal silicide layer. And the bonding pads are arranged between the bonding pads at intervals and are in physical contact with the plug structure and the side wall of the metal silicide layer. Therefore, the semiconductor device has more optimized component structure and efficiency, thereby improving operation performance.

Description

Technical Field

[0001] The utility model relates to a semiconductor device, in particular to a semiconductor device with a gate line structure. Background Art

[0002] As various electronic products develop towards miniaturization, the design of semiconductor devices must also meet the requirements of high integration and high density. For dynamic random access memory (DRAM) with a recessed gate structure, since it can obtain a longer carrier channel length in the same semiconductor substrate to reduce the leakage of the capacitor structure, it has gradually replaced the dynamic random access memory with only a planar gate structure under the current mainstream development trend. Generally speaking, a dynamic random access memory with a recessed gate structure is composed of a large number of memory cells gathered to form an array area for storing information, and each memory cell can be composed of a transistor component and a capacitor component connected in series to receive voltage information from a word line (WL) and a bit line (BL). In response to product requirements, the density of memory cells in the array area must be continuously improved, resulting in increasing difficulty and complexity in related manufacturing processes and designs. Therefore, the existing technology or structure needs to be further improved to effectively improve the performance and reliability of related memory devices. Utility Model Content

[0003] One of the purposes of the utility model is to provide a semiconductor device, wherein a pad spacing is provided between pads, the bottom surface of which is lower than the metal silicide layer, to effectively isolate the contact between the pads and the gate line structure. In this way, the short circuit problem caused by the possible structural defects between the plug structure and the gate line structure can be improved, thereby improving the component performance and operation performance of the semiconductor device.

[0004] One object of the utility model is to provide a semiconductor device including a substrate, a plurality of plug structures and a plurality of gate line structures, a metal silicide layer, a plurality of pads and a plurality of pad intervals. The plug structures and the gate line structures are alternately arranged on the substrate. The metal silicide layer is arranged on the plug structures and physically contacts the plug structures. The pads are arranged on the metal silicide layer and physically contacts the metal silicide layer. The pad intervals are arranged between the pads and physically contact the sidewalls of the plug structures and the metal silicide layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0005] The accompanying drawings provide a deeper understanding of the embodiments of the utility model and are incorporated into this specification as a part thereof. These drawings and descriptions are used to illustrate the principles of some embodiments. It should be noted that all drawings are schematic diagrams, and the relative sizes and proportions have been adjusted for the purpose of illustration and drawing convenience. The same symbols represent corresponding or similar features in different embodiments.

[0006] Figure 1 It is a schematic diagram of a semiconductor device in a first embodiment of the utility model;

[0007] Figure 2 A schematic diagram of a semiconductor device in a preferred embodiment of the utility model;

[0008] Figures 3 to 7 Schematic diagram of a method for manufacturing a semiconductor device in a preferred embodiment of the utility model, wherein:

[0009] Figure 3 is a schematic cross-sectional view of a semiconductor device after a gate line structure is formed;

[0010] Figure 4 is a cross-sectional schematic diagram of a semiconductor device after a plug structure is formed;

[0011] Figure 5 is a schematic cross-sectional view of a semiconductor device after a metal silicide layer is formed;

[0012] Figure 6 is a schematic cross-sectional view of a semiconductor device after a conductive material layer is formed; and

[0013] Figure 7 It is a cross-sectional schematic diagram of a semiconductor device after a photolithography process;

[0014] Figure 8 It is a schematic diagram of a semiconductor device in a second embodiment of the utility model;

[0015] Fig. 9 It is a schematic diagram of a semiconductor device in a third embodiment of the utility model;

[0016] Fig.10 It is a schematic diagram of a semiconductor device in a fourth embodiment of the present utility model.

[0017] Reference numerals:

[0018] 10, 30, 40, 50: semiconductor devices;

[0019] 100: substrate;

[0020] 102: Shallow trench isolation;

[0021] 104: active region;

[0022] 110: dielectric layer;

[0023] 112: silicon oxide layer;

[0024] 114: silicon nitride layer;

[0025] 116: silicon oxide layer;

[0026] 120: Gate line structure;

[0027] 120t: topmost surface;

[0028] 122: semiconductor layer;

[0029] 122a: contact;

[0030] 124: barrier layer;

[0031] 124t: topmost surface;

[0032] 126: metal layer;

[0033] 128: gate line cover layer;

[0034] 128b: bottommost surface;

[0035] 128t: top surface;

[0036] 130, 330: first spacer structure;

[0037] 130t: the top;

[0038] 132: first spacer wall;

[0039] 134: second spacer wall;

[0040] 136: third interspace wall;

[0041] 140: plug structure;

[0042] 140a: plug hole;

[0043] 140s: side wall;

[0044] 140t: topmost surface;

[0045] 142: metal silicide layer;

[0046] 142t: topmost surface;

[0047] 142b: bottommost surface;

[0048] 142s: side wall;

[0049] 150: pad;

[0050] 150b: bottommost surface;

[0051] 150s: side wall;

[0052] 152: barrier layer;

[0053] 152a: barrier material layer;

[0054] 154: metal layer;

[0055] 154a: metal material layer;

[0056] 160, 360, 460: pad spacing;

[0057] 160a: perforation;

[0058] 160b, 360b, 460b: bottom surface;

[0059] 170: Capacitor structure;

[0060] 172: bottom electrode layer;

[0061] 174: capacitor dielectric layer;

[0062] 176: top electrode layer;

[0063] 230, 530: second spacer structure;

[0064] 230a: spacer structure;

[0065] 230t: the top;

[0066] 334: void layer;

[0067] 538: fourth interstitial wall;

[0068] h1, h2: height;

[0069] w1, w2: maximum width. DETAILED DESCRIPTION

[0070] In order to enable those skilled in the art to further understand the present invention, the following lists the preferred embodiments of the present invention, and with the accompanying drawings, describes in detail the composition and intended effects of the present invention. It should be noted that the following embodiments can replace, reorganize, and mix the features of several different embodiments to complete other embodiments without departing from the spirit of the present invention.

[0071] Please refer to Figure 1, which is a schematic diagram of a semiconductor device 10 according to a first embodiment of the present invention. The semiconductor device 10 includes a substrate 100, a plurality of gate line structures 120 and a plurality of plug structures 140, a metal silicide layer 142, a plurality of pads 150, and a plurality of pad spacers 160. The substrate 100 includes, for example, a silicon substrate, a silicon-containing substrate, an epitaxial silicon substrate, a silicon-on-insulator substrate, or a substrate made of other suitable materials, and includes, in detail, a plurality of shallow trench isolations 102 (for example, including silicon oxide) and a plurality of active regions 104 disposed therein. The gate line structure 120 and the plug structure 140 are alternately disposed on the substrate 100, and a metal silicide layer 142 and a pad 150 are sequentially disposed above the plug structure 140, wherein the metal silicide layer 142 physically contacts the plug structure 140, and the pad 150 physically contacts the metal silicide layer 142. In one embodiment, each pad 150 includes, for example, a barrier layer 152 and a metal layer 154 stacked in sequence. The barrier layer 152 conformally covers the plug structure 140 and the gate line cap layer 128 additionally disposed above the gate line structure 120, and includes, for example, conductive barrier materials such as titanium (Ti) and / or titanium nitride (TiN), tantalum (Ta) and / or tantalum oxide (TaN), and the metal layer 154 covers the barrier layer 152, and includes, for example, copper (Cu), aluminum (Al), tungsten (W) or other suitable low-resistivity conductive materials, but is not limited thereto.

[0072] It should be noted that the pad spacer 160 is disposed between adjacent pads 150 and physically contacts the sidewall 150s of the pad 150, the sidewall 142s of the metal silicide layer 142 and a portion of the sidewall 140s of the plug structure 140, so as to effectively electrically isolate the pad 150 from the contact between the adjacent components (such as the gate line structure 120, etc.). In one embodiment, the pad spacer 160 includes, for example, insulating materials such as silicon nitride (SiN) and silicon carbonitride (SiCN), but is not limited thereto. Under this configuration, the short circuit problem that may be derived from the structural defects of the plug structure 140 and the gate line structure 120 due to the continuous improvement of the component integration can be improved by configuring the pad spacer 160, thereby improving the component performance and operation performance of the semiconductor device 10.

[0073] Specifically, the gate line structure 120 includes a semiconductor layer 122, a barrier layer 124, and a metal layer 126 stacked in order from bottom to top. The semiconductor layer 122 includes, for example, semiconductor materials such as doped polysilicon and doped amorphous silicon, the barrier layer 124 includes, for example, conductive barrier materials such as titanium and / or titanium nitride, tantalum and / or tantalum oxide, the metal layer 126 includes, for example, copper, aluminum, tungsten or other suitable low resistivity conductive materials, and the gate line cap layer 128 includes, for example, insulating materials such as silicon oxide, silicon nitride or silicon oxynitride, but is not limited thereto. The gate line structure 120 is in principle disposed on the dielectric layer 110 covering the substrate 100, and a portion of the semiconductor layer 122 passes through the dielectric layer 110 and extends into the substrate 100 to become a contact 122a that physically contacts the active area 104. In one embodiment, the dielectric layer 110 includes, for example, a silicon oxide layer 112 , a silicon nitride layer 114 , and a silicon oxide layer 116 stacked in sequence to have an oxide-nitride-oxide (ONO) structure, but the present invention is not limited thereto.

[0074] The top surface 120t of the gate line structure 120 and the bottom surface 128b of the gate line capping layer 128 disposed thereon are coplanar, and the bottom surface 160b of the pad spacer 160 is preferably higher than the top surface 120t of the gate line structure 120 and the bottom surface 128b of the gate line capping layer 128. In other words, the bottom of the pad spacer 160 further extends into the gate line capping layer 128 above the gate line structure 120, but does not contact the bottom surface 128b of the gate line capping layer 128, so that the pad spacer 160 is partially disposed in the gate line capping layer 128, thereby effectively isolating the top surface 120t of the gate line structure 120 from the bottom surface 150b of the pad 150. On the other hand, the bottom of the pad spacer 160 also partially extends into the plug structure 140, so that the top surface 140t of the plug structure 140 is preferably higher than the bottom surface 160b of the pad spacer 160 and the top surface 120t of the gate line structure 120. Furthermore, the maximum width w1 of the metal silicide layer 142 is smaller than the maximum width w2 of the plug structure 140. Thus, the top surface 142t of the metal silicide layer 142 and the pad 150 sequentially disposed above the plug structure 140 are also higher than the bottom surface 160b of the pad spacer 160 and the top surface 120t of the gate line structure 120, and simultaneously contact and cover the sidewall 150s of the pad 150, the sidewall 142s of the metal silicide layer 142, and a portion of the sidewall 140s of the plug structure 140 through the pad spacer 160, so as to effectively isolate the gate line structure 120 from the contact between the pad 150 and the plug structure 140.

[0075] For example Figure 1As shown, the semiconductor device 10 further includes a first spacer structure 130 and a second spacer structure 230 respectively disposed on the sidewalls of both sides of the gate line structure 120. The top of the first spacer structure 130 physically contacts the bottom surface 160b of the pad interval 160, and has a relatively low height h1 on the substrate 100. The top 130t of the first spacer structure 130 is, for example, lower than the top surface 140t of the plug structure 140, and higher than the top surface 120t of the gate line structure 120 and the bottom surface 160b of the pad interval 160. The second spacer structure 230 is located between two adjacent pad intervals 160, does not contact the pad intervals 160, and has a relatively high height h2 on the substrate 100. The top 230t of the second spacer structure 230 is higher than the top surface 142t of the metal silicide layer 142, and is coplanar with the top surface 128t of the gate line cap layer 128. In one embodiment, the first spacer structure 130 and the second spacer structure 230 respectively include a first spacer 132, a second spacer 134 and a third spacer 136 which are sequentially arranged on the side walls of the gate line structure 120 and the gate line cap layer 128, wherein the first spacer 132 and the third spacer 136, for example, include the same insulating material, such as silicon nitride, silicon carbonitride, etc., and are preferably the same as the insulating material of the pad spacer 160, and the second spacer 134, for example, includes an insulating material different from the first spacer 132 and the third spacer 136, such as silicon oxide, silicon oxynitride, etc., but is not limited to this.

[0076] According to the semiconductor device 10 of the present embodiment, a pad spacer 160 partially extending into the plug structure 140 and the gate line cap layer 128 is provided between adjacent pads 150, so that the pad spacer 160 physically contacts the pad 150, the metal silicide layer 142, and the sidewalls 150s, 142s, 140s of the plug structure 140. Thus, the bottom surface 160b of the pad spacer 160 is lower than the top surface 142t of the metal silicide layer 142, so as to effectively electrically isolate the contact between the pad 150 and the gate line structure 120, thereby improving the short circuit problem that may be derived from the structural defects of the plug structure 140 and the gate line structure 120 due to the continuous improvement of the device integration. In a preferred embodiment, the semiconductor device 10 may further include a capacitor structure 170 disposed above the pad 150, which includes a plurality of bottom electrode layers 172, a capacitor dielectric layer 174, and a top electrode layer 176 disposed in sequence, forming a plurality of vertically extending capacitors to serve as storage nodes (SN) of the semiconductor device 10 and electrically connected to the pad 150 that can serve as storage node pads (SN pads), such as Figure 2As shown. Meanwhile, the gate line structure 120 of the semiconductor device 10 can be used as a bit line (BL) of the semiconductor device 10, and is electrically connected to a component (such as a transistor component, not shown) disposed in the substrate 100 by means of a contact 122a extending into the substrate 100 as a bit line contact (BLC); the plug structure 140 can be used as a storage node contact (SNC) of the semiconductor device 10, and is also electrically connected to the component disposed in the substrate 100. Thus, the semiconductor device 10 of the preferred embodiment can form a dynamic random access memory (DRAM) device, and the capacitor and the transistor component disposed in the substrate 100 form a memory cell (memory cell) of the smallest component in the dynamic random access memory array, which receives voltage information from the bit line (i.e., the gate line structure 120) and the word line (not shown) to achieve optimized component performance and operation performance.

[0077] In order to enable a person skilled in the art to which the present invention belongs to easily understand the semiconductor device 10 of the present invention, a method for manufacturing the semiconductor device 10 a of the present invention will be further described below.

[0078] See also Figures 3 to 7 FIG. 1 is a schematic diagram of a method for manufacturing a semiconductor device 10 in a preferred embodiment of the present invention. First, Figure 3 As shown, a substrate 100 is provided, and a shallow trench isolation 102 is formed in the substrate 100, and an active area 104 is simultaneously defined. In one embodiment, the shallow trench isolation 102 is formed by, for example, first forming a plurality of trenches (not shown) in the substrate 100 using an etching process, and then filling the trenches with at least one insulating material (such as silicon oxide, silicon nitride, etc.) to form a shallow trench isolation 102 whose surface is flush with the top surface of the substrate 100, but the present invention is not limited thereto.

[0079] Next, a dielectric layer 110, a gate line structure 120 and a gate line capping layer 128 are formed on the substrate 100. In one embodiment, the manufacturing process of the gate line structure 120 and the gate line capping layer 128 includes, but is not limited to, the following steps. First, a plurality of openings (not shown) are formed on the substrate 100 through a mask layer (not shown), penetrating the dielectric layer 110 and partially exposing the corresponding active area 104. After removing the mask layer, a semiconductor material layer (not shown, for example, including semiconductor materials such as polycrystalline silicon and doped amorphous silicon) is sequentially formed on the substrate 100 to fill the openings. Then, a barrier material layer (not shown, for example, including conductive barrier materials such as titanium and / or titanium nitride, tantalum and / or tantalum oxide), a metal material layer (not shown, for example, including metal materials with low resistivity such as tungsten, aluminum or copper) and a capping material layer (not shown, for example, including insulating materials such as silicon oxide, silicon nitride or silicon oxynitride) are formed on the semiconductor material layer. Finally, through a patterning process, the following are formed at the same time. Figure 1 The gate line structure 120 and the gate line capping layer 128 disposed thereon are shown. The gate line structure 120 includes a semiconductor layer 122, a barrier layer 124, and a metal layer 126 stacked in sequence from bottom to top, wherein a portion of the semiconductor layer 122 fills the opening to form a contact 122a that physically contacts the active region 104.

[0080] Then, Figure 3 As shown, a spacer structure 230a is formed on the sidewalls of the gate line structure 120 and the gate line cap layer 128, including a first spacer 132, a second spacer 134 and a third spacer 136 stacked in sequence in a horizontal direction, and the top surface of the spacer structure 230 is coplanar with the topmost surface 128t of the gate line cap layer 128. In one embodiment, the manufacturing process of the spacer structure 230a includes, but is not limited to, the following steps. First, multiple deposition and back etching manufacturing processes are performed on the substrate 100, and a first spacer material layer (for example, including silicon nitride, silicon carbonitride), a second spacer material layer (for example, including silicon oxide, silicon oxynitride), and a third spacer material layer (for example, including silicon nitride, silicon carbonitride) are sequentially deposited and back-etched on the gate line cap layer 128 and the gate line structure 120 to form the spacer structure 230a.

[0081] like Figure 4As shown, a portion of the substrate 100 between adjacent gate line structures 120 is etched through another mask layer (not shown) to form a plug hole 140a extending into the substrate 100. Then, an epitaxial manufacturing process is performed to form an epitaxial material such as silicon, silicon phosphorus, silicon germanium, or germanium from the exposed surface of the plug hole 140a to fill the plug hole 140a and further fill the portion of the space between adjacent gate line structures 120 to form a plug structure 140. The top surface 140t of the plug structure 140 is preferably higher than the topmost surface 120t of the gate line structure 120 and the bottommost surface 128b of the gate line cap layer 128, but the present invention is not limited thereto.

[0082] like Figure 5 As shown, a metal silicide manufacturing process is performed on the plug structure 140 to form a metal silicide layer 142. In one embodiment, the metal silicide manufacturing process includes but is not limited to the following steps. First, a selective deposition process is performed to form a metal layer (not shown) on the plug structure 140, for example, a metal material suitable for reacting with a silicon material such as cobalt, titanium, nickel, etc., preferably including cobalt, and then a heat treatment process is performed to make the metal layer partially react with the plug structure 140 below to form a metal silicide layer 142. The metal silicide layer 142 includes, for example, metal silicide materials such as cobalt silicide, titanium silicide and nickel silicide, preferably including cobalt disilicide, but not limited thereto. In addition, after the metal silicide layer 142 is formed, the metal layer and the other mask layer that have not reacted completely are completely removed.

[0083] like Figure 6 As shown, at least one deposition process and a planarization process are performed to sequentially form a barrier material layer 152a (e.g., including conductive barrier materials such as titanium and / or titanium nitride, tantalum and / or tantalum oxide) and a metal material layer 154a (e.g., including copper, aluminum, tungsten or other suitable low-resistivity metal materials) on the substrate 100. The barrier material layer 152a is conformally formed on the plug structure 140, the gate line cap layer 128 and the spacer structure 230a, and the metal material layer 154a fills the remaining space between adjacent gate line structures 120 and further covers the gate line cap layer 128 and the spacer structure 230a.

[0084] like Figure 7As shown, a photolithography process is performed on the metal material layer 154a and the barrier material layer 152a through another mask layer (not shown), and the metal material layer 154a and the barrier material layer 152a are partially removed to form a metal layer 154 and a barrier layer 152. In addition, each pad 150 is formed by the barrier layer 152 and the metal layer 154 stacked in sequence. It should be noted that when the photolithography process is performed, the etching conditions of the etching process are also adjusted, so that part of the gate line cap layer 128, part of the metal silicide layer 142 and part of the plug structure 140 are removed together with the removed metal material layer 154a and the barrier material layer 152a, forming a plurality of through holes 160a. The bottom of the through hole 160a preferably extends into the gate line capping layer 128 and the plug structure 140, so that the bottom surface 160b of the through hole 160a is lower than the top surface 142t of the metal silicide layer 142 and higher than the top surface 120t of the gate line structure 120 and the bottom surface 128b of the gate line capping layer 128, and the side wall 150s of the pad 150, the side wall 142s of the metal silicide layer 142 and part of the side wall 140s of the plug structure 140 can be exposed at the same time. On the other hand, part of the spacer structure 230a is also removed during the photolithography process to form Figure 1 The first spacer structure 130 is shown, and the spacer structure 230 a on the other side forms a second spacer structure 230 .

[0085] Thus, the deposition and etching back processes are continued on the substrate 100 to fill the through hole 160a with insulating material (eg, insulating material such as silicon nitride or silicon carbonitride), thereby forming a Figure 1 The pad spacer 160 is shown in FIG. 1 , and the bottom surface 160b is lower than the top surface 142t of the metal silicide layer 142 and higher than the top surface 120t of the gate line structure 120. According to the manufacturing method of this embodiment, a pad spacer 160 partially extending into the plug structure 140 and the gate line cap layer 128 is formed between adjacent pads 150, so that the pad spacer 160 physically contacts the pad 150, the metal silicide layer 142 and the sidewalls 150s, 142s, 140s of the plug structure 140. In this operation, the bottom surface 160b of the pad spacer 160 formed by the manufacturing method of this embodiment is lower than the top surface 142t of the metal silicide layer 142, which can effectively electrically isolate the contact between the pad 150 and the gate line structure 120, thereby improving the short circuit problem that may be derived from the structural defects of the plug structure 140 and the gate line structure 120 due to the continuous improvement of the component integration.

[0086] In a preferred embodiment, it is also possible to form Figure 1 After the semiconductor device 10 is shown, a further structure is formed on the pad 150 as shown in FIG. Figure 2The capacitor structure 170 shown includes a plurality of bottom electrode layers 172, capacitor dielectric layers 174, and top electrode layers 176 arranged in sequence, forming a plurality of vertically extending capacitors to serve as storage nodes (SN) of the semiconductor device 10 and electrically connected to pads 150 that can serve as storage node pads (SN pads). At the same time, the gate line structure 120 formed by the aforementioned manufacturing method can serve as a bit line of the semiconductor device 10, which can be electrically connected to a component (such as a transistor component, not shown) arranged in the substrate 100 by means of a contact 122a extending into the substrate 100 as a bit line plug; and the plug structure 140 formed by the aforementioned manufacturing method can serve as a storage node plug of the semiconductor device 10, and is also electrically connected to the component arranged in the substrate 100. Thus, the semiconductor device 10 formed by the aforementioned manufacturing method forms a dynamic random access memory device, and the capacitor and the transistor components arranged in the substrate 100 constitute the smallest storage unit in the dynamic random access memory array, which receives voltage information from the bit line (i.e., the gate line structure 120) and the word line to achieve optimized device performance and operation performance.

[0087] A person skilled in the art of the present invention should be able to easily understand that, in order to meet the actual product requirements, the semiconductor device and the method for manufacturing the same may also have other aspects and are not limited to the above. The following will further describe other embodiments or variations of the semiconductor device and the method for manufacturing the same. In order to simplify the description, the following description mainly describes the differences between the embodiments, and will not repeat the same aspects. In addition, the same components in the embodiments of the present invention are marked with the same reference numerals to facilitate comparison between the embodiments.

[0088] Please refer to Figure 8 As shown, it is a cross-sectional schematic diagram of a semiconductor device 30 in the second embodiment of the present invention. The structure of the semiconductor device 30 in this embodiment is substantially the same as that of the semiconductor device 10 in the aforementioned embodiment. Figure 1 The main difference between the semiconductor device 30 of the present embodiment and the aforementioned embodiment is that the bottom surface 360b of the pad spacer 360 of the present embodiment is lower than the top surface 140t of the plug structure 140 (i.e., the bottom surface 142b of the metal silicide layer 142) and the top surface 120t of the gate line structure 120.

[0089] Specifically, in this embodiment, when the metal material layer 154a and the barrier material layer 152a are subjected to a photolithography process, the etching conditions of the etching process are further adjusted to remove the metal material layer 154a and the barrier material layer 152a, and the second spacer 134 below is removed simultaneously, and an air gap layer 334 is formed between the first spacer 132 and the third spacer 136. In this way, the first spacer 132, the air gap layer 334 and the third spacer 136 stacked in sequence in the horizontal direction form the first spacer structure 330 of this embodiment. Then, the deposition and back etching process is continued on the substrate 100 to fill in the insulating material (for example, including insulating materials such as silicon nitride and silicon carbonitride), so as to form the following. Figure 8 The pad spacer 360 is shown. The bottom portion of the pad spacer 360 extends into the gap layer 334 , so that the bottom surface 360 ​​b of the pad spacer 360 is lower than the top surface 140 t of the plug structure 140 .

[0090] In this operation, the semiconductor device 30 formed by the manufacturing method of the present embodiment can also form a pad spacer 360 between adjacent pads 150, and the pad spacer 360 extends into the plug structure 140, the gate line cap layer 128 and the gap layer 334, and physically contacts the pad 150, the metal silicide layer 142 and the sidewalls 150s, 142s, 140s of the plug structure 140. In addition, the bottom surface 360b of the pad spacer 360 is lower than the top surface 140t of the plug structure 140 (i.e., the bottom surface 142b of the metal silicide layer 142) and the top surface 120t of the gate line structure 120, which can not only effectively electrically isolate the contact between the pad 150 and the gate line structure 120, but also achieve more optimized structural stability, thereby improving the short circuit problem that may be derived from the structural defects of the plug structure 140 and the gate line structure 120 due to the continuous improvement of the component integration. Therefore, the semiconductor device 30 of this embodiment also has a reliable structure and performance, and achieves more optimized device performance and operation performance.

[0091] Please refer to Fig. 9 , which is a cross-sectional schematic diagram of a semiconductor device 40 in the third embodiment of the present invention. The structure of the semiconductor device 40 in this embodiment is substantially the same as that of the semiconductor device 30 in the aforementioned embodiment, and the similarities are not repeated here. The main difference between the semiconductor device 40 in this embodiment and the aforementioned embodiment is that the bottom surface 460b of the pad spacer 460 in this embodiment is also lower than the top surface 124t of the barrier layer 124.

[0092] Specifically, in this embodiment, when the photolithography process is performed on the metal material layer 154a and the barrier material layer 152a, the second spacer 134 below is removed simultaneously to form the gap layer 334, and then the pad spacer 460 whose bottom part extends into the gap layer 334 is formed. In this way, the bottom surface 460b of the pad spacer 460 can be lower than the metal layer 126 of the gate line structure 120. Under this operation, the semiconductor device 40 formed by the manufacturing method of this embodiment can also make the pad spacer 460 extend into the plug structure 140, the gate line cap layer 128 and the gap layer 334, so as to physically contact the pad 150, the metal silicide layer 142 and the sidewalls 150s, 142s, 140s of the plug structure 140. Furthermore, the bottom surface 460b of the pad spacer 460 is lower than the top surface 124t of the barrier layer 124, which can not only effectively electrically isolate the contact between the pad 150 and the gate line structure 120, but also achieve a more optimized structural stability, thereby improving the short circuit problem that may be derived from the structural defects of the plug structure 140 and the gate line structure 120 due to the continuous improvement of the component integration. Therefore, the semiconductor device 40 of this embodiment also has a reliable structure and performance, and achieves a more optimized component performance and operation performance.

[0093] Please refer to Fig.10 As shown, it is a cross-sectional schematic diagram of a semiconductor device 50 in a fourth embodiment of the present invention. The structure of the semiconductor device 50 in this embodiment is substantially the same as that of the semiconductor device 10 in the aforementioned embodiment. Figure 1 The main difference between the semiconductor device 50 of this embodiment and the above-mentioned embodiment is that the second spacer structure 530 of this embodiment includes a first spacer 132, a second spacer 134, a third spacer 136 and a fourth spacer 538 stacked in sequence in the horizontal direction.

[0094] In detail, this embodiment is to implement Figure 5 Before the metal silicide manufacturing process shown in the figure, an additional deposition and back etching manufacturing process is performed to form a fourth spacer 538 on the sidewall of the third spacer 136 of the spacer structure 230a. In this way, the first spacer 132, the second spacer 134, the third spacer 136 and the fourth spacer 538 stacked in sequence in the horizontal direction form the second spacer structure 530 of this embodiment. In one embodiment, the fourth spacer 538 includes materials such as silicon oxide, silicon oxynitride, etc., but is not limited thereto. Subsequently, the aforementioned implementation is sequentially performed. Figures 5 to 7 The various processes shown in the figure form Fig.10The metal silicide layer 142, the pad 150, and the first spacer structure 130 are shown. Then, the insulating material (such as insulating materials such as silicon nitride and silicon carbonitride) is continuously filled on the substrate 100 to form the Fig.10 The pads are shown spaced 160 apart and 360 apart.

[0095] Under this operation, the semiconductor device 50 formed by the manufacturing method of this embodiment can also form a pad spacer 160 between adjacent pads 150, and the pad spacer 160 extends into the plug structure 140 and the gate line cap layer 128, and physically contacts the pad 150, the metal silicide layer 142 and the sidewalls 150s, 142s, 140s of the plug structure 140, so as to effectively electrically isolate the contact between the pad 150 and the gate line structure 120, thereby improving the short circuit problem that may be derived from the structural defects of the plug structure 140 and the gate line structure 120 due to the continuous improvement of the device integration. Therefore, the semiconductor device 50 of this embodiment also has a reliable structure and performance, and achieves a more optimized device performance and operation performance.

[0096] The above description is only the preferred embodiment of the utility model, and is not intended to limit the utility model. For those skilled in the art, the utility model can have various modifications and changes. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the utility model shall be included in the protection scope of the utility model.

Claims

1. A semiconductor device, characterized in that include: substrate; A plurality of gate line structures and a plurality of plug structures are alternately arranged on the substrate; a metal silicide layer disposed on the plug structure and physically contacting the plug structure; A plurality of pads, disposed on the metal silicide layer and physically contacting the metal silicide layer; as well as A plurality of pad intervals are disposed between the pads and physically contact the plug structure and the sidewalls of the metal silicide layer.

2. The semiconductor device according to claim 1, wherein: The bottom surface of the pad interval is higher than the top surface of the gate line structure.

3. The semiconductor device according to claim 2, characterized in that Also includes: The gate line cover layer is arranged on the gate line structure, and the pad spacer is arranged in the gate line cover layer.

4. The semiconductor device according to claim 3, characterized in that The bottommost surface of the pad gap is also higher than the bottommost surface of the gate line capping layer.

5. The semiconductor device according to claim 1, wherein: Also includes: The first spacer structure is disposed at one side of the gate line structure and is in physical contact with the pad spacer, wherein the top of the first spacer structure is lower than the top surface of the plug structure.

6. The semiconductor device according to claim 2, wherein: The bottommost surface of the pad interval is lower than the bottommost surface of the pad.

7. The semiconductor device according to claim 1, wherein: The bottom surface of the metal silicide layer is higher than the top surface of the gate line structure.

8. The semiconductor device according to claim 5, characterized in that Also includes: The second spacer structure is disposed on the other side of the gate line structure, and the top of the second spacer structure is higher than the top surface of the metal silicide layer.

9. The semiconductor device according to claim 1, wherein: The top surface of the plug structure is higher than the top surface of the gate line structure.

10. The semiconductor device according to claim 1, wherein: The bottom surface of the pad is higher than the top surface of the gate line structure.

11. The semiconductor device according to claim 8, characterized in that The pad spacer also physically contacts the topmost point of the first spacer structure.

12. The semiconductor device according to claim 11, characterized in that The second spacer structure is arranged between two adjacent pad gaps.

13. The semiconductor device according to claim 8, characterized in that The first spacer structure and the second spacer structure respectively include a first spacer, a second spacer and a third spacer sequentially arranged on the sidewall of the gate line structure, wherein the first spacer and the third spacer include the same material as the pad spacer.

14. The semiconductor device according to claim 1, wherein: The maximum width of the metal silicide layer is smaller than the maximum width of the plug structure.

15. The semiconductor device according to claim 1, wherein: The bottom surface of the pad spacer is lower than the top surface of the metal silicide layer.

16. The semiconductor device according to claim 1, wherein: The bottom surface of the pad spacer is lower than the top surface of the gate line structure.

17. The semiconductor device according to claim 16, characterized in that The gate line structure includes a semiconductor layer, a barrier layer, and a metal layer stacked in sequence, and the bottom surface of the pad gap is lower than the top surface of the barrier layer.

18. The semiconductor device according to claim 5, characterized in that The first spacer structure includes a first spacer, a gap layer and a third spacer which are sequentially arranged, and the topmost surface of the pad gap physically contacts the gap layer.

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