Semiconductor device

Abstract

Various semiconductor devices are disclosed that include recessed isolation regions in trench regions formed by removing dummy gate structures. The recessed isolation regions may allow for larger fin heights in the channel regions. Metal gate structures may be formed on the recessed isolation regions and the fins.

Description

Technical Field

[0001] The present disclosure relates to a semiconductor device. Background Art

[0002] The integrated circuit (IC) industry has experienced exponential growth. Technological advances in IC materials and design have produced generations of ICs, each with smaller and more complex circuits than the previous generation. During IC evolution, functional density (i.e., the number of interconnected devices per chip area) has generally increased while geometry size (i.e., the smallest component (or wire) that can be produced using a manufacturing process) has decreased. This scaling down process generally provides benefits by increasing production efficiency and reducing associated costs.

[0003] This scaling down has also increased the complexity of processing and manufacturing ICs, and in order to achieve these advances, similar advances in IC processing and manufacturing are needed. For example, as fin-like field effect transistor (FinFET) technology progresses toward smaller feature sizes (e.g., 32 nanometers, 28 nanometers, 20 nanometers and below), advanced techniques are needed to precisely control fin profiles and / or dimensions to ensure and optimize FinFET performance, reliability and / or manufacturability. Although existing device formation techniques have generally been suitable for their intended uses, these techniques have not yet been completely satisfactory in all respects. Utility Model Content

[0004] In some embodiments, a semiconductor device includes a first semiconductor structure, a second semiconductor structure, an isolation structure, a first metal gate structure, and an interlayer dielectric layer. The first semiconductor structure and the second semiconductor structure each extend above the substrate along a first direction and have a length extending along a second direction. The isolation structure extends between a bottom portion of the first semiconductor structure and a bottom portion of the second semiconductor structure. The first metal gate structure is disposed above a channel region of an upper portion of the first semiconductor structure and a channel region of an upper portion of the second semiconductor structure, wherein the first metal gate structure extends longitudinally along a third direction. The interlayer dielectric layer is disposed above the isolation structure and adjacent to the first metal gate structure. The isolation structure has a first thickness below the first metal gate structure and a second thickness below the interlayer dielectric layer, wherein the first thickness is less than the second thickness.

[0005] In some embodiments, a semiconductor device includes a substrate, a first fin, a second fin, an isolation region, and a metal gate structure. The first fin and the second fin extend above the substrate. The isolation region is between the first fin and the second fin. The metal gate structure is above the first fin, the second fin, and the isolation region. The isolation region has a first thickness outside the metal gate structure, and the isolation region has a second thickness below the metal gate structure, and the first thickness is greater than the second thickness.

[0006] In some embodiments, a semiconductor device includes a substrate, a fin, an isolation region, a metal gate structure, and an interlayer dielectric layer. The fin extends above the substrate. The isolation region is next to the fin. The metal gate structure is above the fin and the isolation region. The interlayer dielectric layer is above the fin and the isolation region and adjacent to the metal gate structure. The isolation region has a first thickness below the metal gate structure and a second thickness below the interlayer dielectric layer, wherein the first thickness is less than the second thickness. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] This disclosure is in conjunction with the attached Figure 1 The following detailed description is best understood when read together. It should be emphasized that, in accordance with standard industry practice, various features are not drawn to scale and are used for illustrative purposes only. In fact, the size of various features may be arbitrarily increased or reduced for clarity of discussion.

[0008] Figure 1 is a flow chart of a method for manufacturing a fin-like field effect transistor (FinFET) device according to various aspects of the present disclosure;

[0009] Figure 2A , Figure 3A , Figure 4A , Figure 5A , Fig. 6A , Fig. 7A , Fig. 8A and Fig.9A According to various aspects of the present disclosure, according to various manufacturing stages, such as Figure 1 A partial top view of a FinFET device of an embodiment of various manufacturing stages associated with a method;

[0010] Figure 2B , Figure 3B , Figure 4B , Figure 5B , Figure 6B , Figure 7B , Figure 8B and Fig. 9B are partial cross-sectional views of FinFET devices in the x-x' plane according to various aspects of the present disclosure, which are at various manufacturing stages, such as Figure 1Respective top view cutouts at manufacturing stages associated with the method;

[0011] Figure 2C , Figure 3C , Figure 4C , Figure 5C , Figure 6C , Figure 7C , Figure 8C and Fig. 9C FIG. 1 is a partial cross-sectional view of a FinFET device in a y1-y1' plane (eg, an isolation region) according to various aspects of the present disclosure, wherein the partial cross-sectional views are taken at various stages of fabrication, such as with Figure 1 Respective top view cutouts at manufacturing stages associated with the method;

[0012] Figure 2D , Figure 3D , Figure 4D , Figure 5D , Fig.6D , Fig.7D , Fig.8D and Fig.9D are partial cross-sectional views of FinFET devices in the y2-y2' plane (eg, along the active region) according to various aspects of the present disclosure, these partial cross-sectional views are taken at various stages of fabrication, such as with Figure 1 Respective top view cutouts at manufacturing stages associated with the method;

[0013] Fig. 6E , Fig. 7E , Fig. 8E and Fig.9E are partial cross-sectional views of FinFET devices in the x2-x2' plane according to various aspects of the present disclosure, these partial cross-sectional views are taken at various stages of manufacture, such as Figure 1 Respective top view cutouts at manufacturing stages associated with the method;

[0014] Fig.10 is a perspective view of an embodiment of a FinFET device according to various aspects of the present disclosure.

[0015]

Explanation of symbols

[0016] 100: Method

[0017] 102: Block

[0018] 104: Block

[0019] 106: Block

[0020] 108: Block

[0021] 110: Block

[0022] 112: Block

[0023] 114: Block

[0024] 116: Block

[0025] 118: Block

[0026] 200:FinFET device

[0027] 200':FinFET device

[0028] 200”: FinFET device

[0029] 202:Substrate

[0030] 204: Isolation Features

[0031] 206: Fins

[0032] 206': Fins

[0033] 206”: Fins

[0034] 240: Spacer layer

[0035] 302: Gate stack

[0036] 304: Gate spacer

[0037] 402: Epitaxial source / drain characteristics

[0038] 502: Dielectric layer

[0039] 504: Gate trench

[0040] 602: concave part

[0041] 900: Metal gate structure

[0042] 902: Gate dielectric

[0043] 904: Gate electrode

[0044] C: Channel area

[0045] D1: Thickness

[0046] D2: Thickness

[0047] FH1: Fin height

[0048] FH2: Fin height

[0049] S / D: S / D zone

[0050] w: width

[0051] w1: width

[0052] w2: width DETAILED DESCRIPTION

[0053] The present disclosure generally relates to integrated circuit devices, and more particularly to fin-like field effect transistors (FinFETs). However, the present disclosure may also be applied to other types of transistors including other multi-gate transistors such as gate-all-around (GAA) devices.

[0054] The following disclosure provides many different embodiments or examples for implementing the different features of the present disclosure. The following describes specific examples of elements and configurations to simplify the present disclosure. Of course, these elements and configurations are only examples and are not intended to be restrictive. For example, in the following description, forming a first feature above or on a second feature may include an embodiment in which the first and second features are directly contacted, and may also include an embodiment in which an additional feature may be formed between the first and second features so that the first and second features may not be directly contacted. In addition, spatial relative terms, such as "lower", "upper", "horizontal", "vertical", "... above", "up", "below", "below", "upward", "down", "top" and "bottom" and their derivatives (e.g., "horizontally", "downwardly", "upwardly", etc.) are used for the purpose of easily presenting the relationship between one feature and another feature of the present disclosure. Spatial relative terms are intended to cover different orientations of devices including features. In addition, when a number or a range of numbers is described with "about", "approximately" and the like, the term is intended to cover a number within a reasonable range of changes that are inherently present during manufacturing. For example, a number or range of numbers encompasses numbers within a reasonable range, which includes the described number, such as within + / -10% of the described number or other values ​​as would be understood by one of ordinary skill in the art. For example, the term "about 5 nm" encompasses a size range from 4.5 nm to 5.5 nm. Furthermore, the disclosure may repeatedly reference numbers and / or letters in various examples. This repetition is for the purpose of simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0055] Fin-type field effect transistors, or FinFETs, have become a popular and promising candidate for high-performance and low-leakage applications. As FinFETs scale down through various technology nodes, it may be desirable to change the geometry of the fins, such as reducing the width of the fins or increasing the height of the fins for improved transistor performance considerations. However, the manufacture of such tall structures leads to problems during processing, such as fin collapse during manufacturing. Therefore, in some embodiments, the present disclosure provides multiple methods and devices that allow for improved drive current, better channel control, less source / drain leakage, and / or other performance improvements in transistor performance, including those achieved by geometric modifications of the fins. The provided methods and devices can provide any of these performance benefits while improving fin structure support by maintaining wider and / or shorter fins for initial processing, and modifying the aspect ratio, width, or height of the fins during subsequent processing (e.g., replacement gate processes). As discussed above, although a fin-type active region has been described, similar performance enhancements and processing benefits may be achieved applying aspects to other configurations of active regions.

[0056] According to one example of the principles described herein, a FinFET device has an increased height in a portion covered by a gate structure (e.g., a channel in the z direction). This increased height can improve the performance of the FinFET. In addition, the portion of the fin that is not covered by the gate structure can have a larger width, thereby providing the desired structural support. In some examples, manufacturing such a device includes forming a dummy gate structure around the fin structure, depositing an interlayer dielectric (ILD), and removing the dummy gate structure to form a trench. After removing the dummy gate structure, the portion of the fin where the replacement metal gate structure will be placed above the fin is exposed, as is the adjacent dielectric between the fins (e.g., shallow trench isolation (STI)). Therefore, an etching process can be applied to recess the adjacent dielectric, thereby increasing the height of the fin. In some embodiments, an etching process can also be applied to reduce the width of the fin structure at the exposed portion. Other portions of the fin structure are covered by the ILD and are therefore not affected by the etching process. After the etching process modifies the shape of the fin, a replacement gate can be formed. Using this technique, the fin structure can be short / wide enough to provide desired structural strength during processing, while being tall / narrow enough in the channel region so as to provide improved performance of the transistor device.

[0057] Figure 11 is a flow chart of a method 100 for manufacturing an integrated circuit device according to various aspects of the present disclosure. In the present embodiment, the method 100 manufactures an integrated circuit device including a FinFET device. However, in other implementations, the method 100 may also be applied to other device types such as a fully-surrounding gate device.

[0058] Exemplary embodiments of the method According to various aspects of the present disclosure, see FIG. 2A to FIG. 9E To provide an overview, these figures partially illustrate a FinFET device 200 . Figure 2A , Figure 3A , Figure 4A , Figure 5A , Fig. 6A , Fig. 7A , Fig. 8A and Fig.9A FIG. 2 is a partial top view of a FinFET device 200. For ease of illustration, a top view generally omits one or more layers or features. Figure 2B , Figure 3B , Figure 4B , Figure 5B , Figure 6B , Figure 7B , Figure 8B and Fig. 9B is a partial cross-sectional view of the FinFET device 200 in the xx' plane taken from the respective top views; Figure 2C , Figure 3C , Figure 4C , Figure 5C , Figure 6C , Figure 7C , Figure 8C and Fig. 9C are partial cross-sectional views of a FinFET device 200 in a y1-y1' plane (eg, an isolation region) according to various aspects of the present disclosure, these partial cross-sectional views are taken at various stages of fabrication, such as with Figure 1 Respective top view cutouts at manufacturing stages associated with the method. Figure 2D , Figure 3D , Figure 4D , Figure 5D , Fig.6D , Fig.7D , Fig.8D and Fig.9D FIG. 1 is a partial cross-sectional view of a FinFET device in the y2-y2' plane (eg, along the fin active region) according to various aspects of the present disclosure, wherein the partial cross-sectional views are taken at various stages of fabrication, such as with Figure 1 Respective top view cutouts at manufacturing stages associated with the method. Fig. 6E , Fig. 7E , Fig. 8E and Fig.9Eare partial cross-sectional views of FinFET devices in the x2-x2' plane according to various aspects of the present disclosure, these partial cross-sectional views are taken at various stages of manufacture, such as Figure 1 Respective top view cutouts at manufacturing stages associated with the method.

[0059] In some embodiments, the FinFET device 200 is part of an IC chip, a system on chip (SoC), or a portion thereof, each of which includes various passive and active microelectronic devices, such as resistors, capacitors, inductors, diodes, p-type field effect transistors (PFETs), n-type field effect transistors (NFETs), metal-oxide semiconductor field effect transistors (MOSFETs), complementary metal-oxide semiconductor (CMOS) transistors, bipolar junction transistors (BJTs), laterally diffused MOS (LDMOS) transistors, high voltage transistors, high frequency transistors, other suitable components, or combinations thereof. FIG. 2A to FIG. 9E The description has been simplified for clarity to better understand the novel concepts of the present disclosure. Additional features may be added in the FinFET device 200 , and some of the features described below may be replaced, modified, or eliminated in other embodiments of the FinFET device 200 . Fig. 7A , Figure 7B , Figure 7C , Fig.7D and Fig. 7E An embodiment of a FinFET device 200 ′ is shown; Fig. 8A , Figure 8B , Figure 8C , Fig.8D and Fig. 8E Modifications of the FinFET device 200 are shown, which are substantially similar to the FinFET device 200 with the noted differences.

[0060] exist Figure 1 In block 102 of method 100, a substrate is provided. Figure 2A , Figure 2B , Figure 2C and Figure 2DIn an example of the present invention, a substrate (e.g., a wafer) 202 is provided for the FinFET device 200. In an embodiment, the substrate 202 includes silicon. Alternatively or in addition, the substrate 202 includes another elemental semiconductor semiconductor, such as germanium; a compound semiconductor, such as silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide and / or indium antimonide; an alloy semiconductor, such as silicon germanium (SiGe), GaAsP, AlInAs, AlGaAs, GaInAs, GaInP and / or GaInAsP; or a combination thereof. Alternatively, the substrate 202 is a semiconductor-on-insulator substrate, such as a silicon-on-insulator (SOI) substrate, a silicon germanium-on-insulator (SGOI) substrate, or a germanium-on-insulator (GOI) substrate. The semiconductor-on-insulator substrate can be manufactured using separation by implantation of oxygen (SIMOX), wafer bonding, and / or other suitable methods. The substrate 202 may include various doping regions according to the design requirements of the FinFET device 200 .

[0061] At block 104 of method 100, active regions and isolation regions are defined on a substrate. In embodiments, active regions may be formed in semiconductor structures extending from a substrate, and these active regions are referred to as fin-type active regions in illustrative and exemplary FinFET devices. However, in forming other devices, other configurations of active regions may be formed. See Figure 2A , Figure 2B , Figure 2C and Figure 2D , the fin 206 is formed above the substrate 202. Figure 2A and Figure 2B , two fins 206 are shown. The present disclosure contemplates embodiments in which the fins 206 include a plurality of fins or a single fin extending from the substrate 202. The fins 206 extend substantially parallel to each other along the y-direction and have a length defined in the y-direction, a width defined in the x-direction, and a height defined in the z-direction. For example, the fin height FH1 of the fin 206 is defined along the z-direction between the top surface of the isolation feature 204 discussed below and the respective top surfaces of the fin 206. In some embodiments, the fin height FH1 is about 40 nm to about 70 nm. Each of the fins 206 has a channel region (C), a source region (S), and a drain region (D) defined along its length (hereinafter y-direction), wherein the channel region is disposed between the source region and the drain region, both of which are collectively referred to as source / drain (S / D) regions. The gate structure described below is formed above the channel region (C) of the fin 206.

[0062] In some embodiments, the fin 206 is part of the substrate 202. For example, in embodiments where the substrate 202 includes silicon, the fin 206 may include silicon. Alternatively, the fin 206 is defined in a material layer disposed on the substrate 202, such as a semiconductor material layer. The semiconductor material may be silicon, germanium, silicon germanium, a III-V semiconductor material, other suitable semiconductor materials, or a combination thereof. In some embodiments, the fin 206 includes a stack of semiconductor layers disposed above the substrate 202. Depending on the design requirements of the FinFET device 200, the semiconductor layers may include the same or different materials, dopants, etching rates, atomic percentages, weight percentages, thicknesses, and / or structures. In an embodiment, the stack of semiconductor layers forming the fin 206 includes alternating channel layers and sacrificial layers.

[0063] A combination of deposition, lithography, and / or etching processes may be performed to define the fin 206 extending from the substrate 202. For example, forming the fin 206 includes performing a lithography process to form a patterned mask layer over the substrate 202 (or a material layer (e.g., an epitaxial layer) disposed over the substrate 202), and performing an etching process to transfer the pattern defined in the patterned mask layer to the substrate 202 (or the material layer). The lithography process may include forming an etchant layer over the substrate 202 (e.g., by spin coating), performing a pre-exposure bake process, performing an exposure process using a mask, performing a post-exposure bake process, and performing a development process. During the exposure process, the resist layer is exposed to radiation energy (e.g., ultraviolet (UV) light, deep UV (DUV) light, or extreme UV (EUV) light), wherein the mask blocks radiation, transmits radiation, and / or reflects radiation to the resist layer, depending on the mask pattern and / or mask type (e.g., binary mask, phase shift mask, or EUV mask) of the mask, so that an image is projected onto the resist layer corresponding to the mask pattern. Since the resist layer is sensitive to the radiation energy, the chemical properties of the exposed portion of the resist layer are changed, and the exposed (or non-exposed) portion of the resist layer is dissolved during the development process depending on the properties of the resist layer and the properties of the developing solution used in the development process. After development, the patterned resist layer includes a resist pattern corresponding to the mask. In some embodiments, the patterned resist layer is a patterned mask layer. In such embodiments, the patterned resist layer is used as an etching mask to remove portions of the substrate 202 (or material layer). In some embodiments, a patterned resist layer is formed over a mask layer, the mask layer is formed over the substrate 202 before the resist layer, and the patterned resist layer is used as an etching mask to remove multiple portions of the mask layer formed over the substrate 202. In such embodiments, the patterned mask layer is used as an etching mask to remove multiple portions of the substrate 202 (or material layer). The etching process may include a dry etching process, a wet etching process, other suitable etching processes, or a combination thereof. In some embodiments, a reactive ion etching (RIE) process is used to form the fin 206. After the etching process, the patterned resist layer is removed from the substrate 202, for example, by a resist stripping process. In some embodiments, after the etching process, the patterned mask layer is removed from the substrate 202 (in some embodiments, removed by a resist stripping process). In some embodiments, the patterned mask layer is removed during etching of the substrate 202 (or material layer).Alternatively, the fin 206 is formed by a multiple patterning process such as: a double patterning lithography (DPL) process (e.g., a lithography-etch-lithography-etch (LELE) process, a self-aligned double patterning (SADP) process, a spacer-is-dielectric (SID) SADP process, other double patterning processes or combinations thereof), a triple patterning process (e.g., a lithography-etch-lithography-etch-lithography-etch (LELELE) process, a self-aligned triple patterning (SATP) process, other triple patterning processes or combinations thereof), other multiple patterning processes (e.g., a self-aligned quadruple patterning (SAQP) process), or combinations thereof. In some embodiments, directed self-assembly (DSA) technology is implemented for forming the fin 206. Additionally, in some alternative embodiments, the exposure process may implement maskless lithography, electron beam writing, and / or ion beam writing for patterning.

[0064] Isolation features 204 are formed over and / or in substrate 202 to separate and isolate various regions of FinFET device 200, such as separating and isolating one fin 206 from an adjacent fin 206. In the depicted embodiment, isolation features 204 surround a lower portion of fin 206. An upper portion of fin 206 extends over isolation features 204 along the z-direction, such that a top surface of fin 206 is disposed above a top surface of isolation features 204 along the z-direction. The upper portion of fin 206 may form a channel region of FinFET device 200. Isolation features 204 include silicon oxide, silicon nitride, silicon oxynitride, other suitable isolation materials (e.g., including silicon, oxygen, nitrogen, carbon, or other suitable isolation components), or a combination thereof. Isolation features 204 may be configured as shallow trench isolation (STI) structures, deep trench isolation (DTI) structures, and / or local oxidation of silicon (LOCOS) structures. For example, the isolation feature 204 may be an STI feature that defines the fin 206 and electrically isolates the fins 206 from each other. The STI feature may be formed by etching a trench in the substrate 202 (e.g., by using a dry etching process and / or a wet etching process), and filling the trench with an insulator material (e.g., using a chemical vapor deposition (CVD) process or a spin coating process). A chemical mechanical polishing (CMP) process may be performed to remove excess insulator material and / or planarize the top surface of the isolation feature 204. The insulator material may then be etched back to form the fin 206, thereby increasing the fin height FH1 above the isolation feature 204. In another example, the isolation feature can be formed by depositing an insulator material over the substrate 202 after forming the fins 206 (in some embodiments, such that the insulator material layer fills the gaps (trench) between the fins 206), and etching back the insulator material layer to form the isolation feature 204, wherein the fins 206 extend over the etched-back isolation feature 204 to the fin height FH1. In some embodiments, the isolation feature includes a multilayer structure filling the trench, such as a silicon nitride layer disposed over a thermal oxide liner layer. In another example, the isolation feature 204 includes a dielectric layer disposed over a doped liner layer (including, for example, boron silicate glass (BSG) or phosphosilicate glass (PSG)). In yet another example, the isolation feature includes a bulk dielectric layer disposed over a liner dielectric layer, wherein the bulk dielectric layer and the liner dielectric layer include a variety of materials depending on the design requirements of the FinFET device 200.Although illustrated as having planar surfaces, the isolation features 204 may include curved linear or arcuate surfaces between the fins 206. The fin height FH1 may be measured from the interface of the isolation features 204 and the fins 206 in the z-direction.

[0065] At block 106 of the method 100, a dummy gate structure or stack is formed over an active region (eg, a semiconductor structure or a fin). Figure 3A , Figure 3B , Figure 3C and Figure 3D , a gate stack 302 is shown formed over portions of the fin 206 and over the isolation feature 204. The gate stack 302 extends longitudinally in a direction different from (e.g., orthogonal to) the longitudinal direction of the fin 206. For example, the gate stacks 302 extend substantially parallel to each other along the x-direction, thereby having a length defined in the x-direction, a width defined in the y-direction, and a height defined in the z-direction. The gate stack 302 is disposed between the S / D regions of the fin 206, wherein the channel region of the fin 206 underlies the gate stack 302. In the XZ plane, the gate stack 302 covers the top surface and sidewall surfaces of the fin 206, as shown in FIG. Figure 3B In the YZ plane, the gate stack 302 is disposed as shown in FIG. Figure 3D The top surface of each channel region of the fin 206 shown in FIG. Figure 3C. In the depicted embodiment, the gate stack 302 is a dummy gate stack including a dummy gate electrode. The dummy gate electrode includes a suitable dummy gate material, such as a polysilicon layer. In some embodiments, the gate stack 302 may therefore be referred to as a polycrystalline (poly, PO) gate stack. In some embodiments, a hard mask layer is formed above the polysilicon layer. The hard mask layer includes silicon oxide, silicon carbide, silicon nitride, other suitable hard mask materials, or a combination thereof. In some embodiments, the gate stack 302 further includes a gate dielectric disposed between the dummy gate electrode and the fin 206, wherein the gate dielectric includes a dielectric material, such as silicon oxide, a high-k dielectric material, other suitable dielectric materials, or a combination thereof. In some embodiments, the gate dielectric includes an interface layer (e.g., a silicon oxide layer) disposed above the fin 206 and a dielectric layer disposed above the interface layer. The gate dielectric layer may be a sacrificial layer or used in a gate structure for forming the FinFET device 200. The gate stack 302 may include numerous other layers, such as a cap layer, an interface layer, a diffusion layer, a barrier layer, or a combination thereof. The gate stack 302 is formed by a deposition process, a lithography process, an etching process, other suitable processes, or a combination thereof. For example, a deposition process is performed to form a dummy gate electrode layer over the fin 206 and the isolation feature 204, and a hard mask layer is formed over the dummy gate dielectric layer. In some embodiments, before forming the dummy gate electrode layer, a deposition process is performed to form a gate dielectric layer over the fin 206 and / or the isolation feature 204. In such embodiments, the dummy gate electrode layer is deposited over the gate dielectric layer. The deposition process includes CVD, physical vapor deposition (PVD), atomic layer deposition (ALD), high density plasma CVD (HDPCVD), metal organic CVD (MOCVD), remote plasma CVD (RPCVD), plasma enhanced CVD (PECVD), plasma enhanced ALD (PEALD), low-pressure CVD (LPCVD), atomic layer CVD (ALCVD), atmospheric pressure CVD (APCVD), other suitable methods, or combinations thereof. A gate patterning process (including, for example, various lithography processes, etching processes, and / or cleaning processes) is then performed to pattern the dummy gate electrode layer and the hard mask layer (and in some embodiments, the gate dielectric layer) to form a gate electrode layer such as. Figure 3A , Figure 3B , Figure 3C and Figure 3D . The gate stack 302 is depicted in FIG.

[0066] After forming the dummy gate structure, gate spacers are formed along the sidewalls of the gate stack. Figure 3A , Figure 3B , Figure 3C and Figure 3D In an example, gate spacers 304 are formed on the sidewalls of gate stack 302. Forming the gate spacers may include forming a dielectric layer of a spacer material over gate stack 302 and fin 206, and performing one or more spacer etching processes. The deposition process may be CVD, PECVD, ALD, PEALD, PVD, other suitable deposition processes, or combinations thereof. The dielectric material may include silicon, oxygen, carbon, nitrogen, other suitable spacer components or combinations thereof (e.g., silicon oxide, silicon nitride, silicon oxynitride (SiON), silicon carbide, silicon carbonitride (SiCN), silicon oxycarbide (SiOC), silicon oxycarbonitride (SiOCN), silicon borocarbon nitride (SiBCN), etc.). In an embodiment, spacer layer 240 includes silicon and nitrogen (and may therefore be referred to as a silicon nitride spacer). In some embodiments, spacer layer 240 is a single layer, such as a silicon nitride layer. In some embodiments, spacer layer 240 includes multiple layers, such as a first dielectric layer disposed over a second dielectric layer. For example, the first dielectric layer may include silicon carbonitride, and the second dielectric layer may include silicon nitride.

[0067] At block 108 of method 100, source / drain features may be formed. For example, forming the source / drain features may include forming a recess in the source / drain region of the fin 206, and epitaxially growing a source / drain material in the recess to fill the recess, thereby forming a semiconductor source / drain feature. In some embodiments, the depth of the source / drain recess is greater than about 20% of the fin height FH1. In some embodiments, the depth of the source / drain recess is between about 20% and 90% of the fin height FH1. In one embodiment, the width (e.g., critical dimension (CD)) of the fin is approximately x nm, the fin height FH1 is approximately 6*x–10*x nm, and the recess depth is approximately 5*x-8*x nm.

[0068] exist Figure 4A , Figure 4B , Figure 4C and Figure 4DIn the example of , the epitaxial source / drain features 402 are formed in the source / drain recesses, and the source / drain recesses are formed in the fin 206. The gate stack 302 is inserted into the respective epitaxial source / drain features 402, so that the channel region is defined between the respective epitaxial source / drain features 402. In some embodiments, the gate stack 302 and its respective epitaxial source / drain features 402 form part of a first FinFET, and the gate stack 302 and its respective epitaxial source / drain features 402 form part of a second FinFET. In some embodiments, the source / drain features 402 can be shared by adjacent gate stacks 302.

[0069] In some embodiments, a deposition process is performed to fill the source / drain recesses with epitaxial semiconductor material, thereby forming epitaxial source / drain features 402. For example, the semiconductor material is epitaxially grown using portions of the fin 206 as seed regions. The epitaxial process may implement a CVD deposition technique (e.g., vapor-phase epitaxy (VPE), ultra-high vacuum CVD (UHV-CVD), LPCVD and / or PECVD), molecular beam epitaxy, other suitable selective epitaxial growth (SEG) processes, or combinations thereof. The epitaxial process may use gaseous (e.g., Si-containing gases, such as SiH4, and / or Ge-containing gases, such as GeH4), and / or liquid precursors that interact with the composite of the fin 206 and / or the substrate 202. The epitaxial source / drain features 402 are doped with n-type dopants and / or p-type dopants. In some embodiments, the epitaxial source / drain features 402 are epitaxial layers including silicon and / or carbon, wherein the epitaxial layer including silicon or the epitaxial layer including silicon carbon is doped with phosphorus, other n-type dopants, or a combination thereof. In some embodiments, the epitaxial source / drain features 402 are epitaxial layers including silicon and / or germanium, wherein the epitaxial layer including silicon and germanium is doped with boron, other p-type dopants, or a combination thereof. In some embodiments, the epitaxial source / drain features 402 include materials and / or dopants that achieve the desired tensile stress and / or compressive stress in the channel region. In some embodiments, the epitaxial source / drain features 402 are doped during deposition by adding impurities to the source material of the epitaxial process. In some embodiments, the epitaxial source / drain features 402 are doped by an ion implantation process after the deposition process. In some embodiments, an annealing process is performed to activate dopants in the epitaxial source / drain features 402 and / or other source / drain regions (eg, HDD regions and / or LDD regions) of the FinFET device 200 .

[0070] Go to Figure 5A , Figure 5B , Figure 5C and Figure 5D , the FinFET device 200 may undergo additional processing. For example, a dielectric layer 502 is formed over the fin 206, the gate stack 302, the gate spacer 304, and the epitaxial source / drain features 402. The dielectric layer 502 may include an interlayer dielectric (ILD) layer and a contact etch stop layer (CESL). The ILD layer includes a dielectric material, and the dielectric material includes, for example, silicon oxide, carbon-doped silicon oxide, silicon nitride, silicon oxynitride, tetraethyl orthosilicate (TEOS), PSG, BSG, boron-doped phosphosilicate glass (BPSG), fluorine-doped silicate glass (FSG), Black (Applied Materials, Santa Clara, California), xerogel, aerogel, amorphous fluorinated carbon, p-xylene, benzocyclobutene (BCB)-based dielectric materials, SiLK (Dow Chemical, Midland, Michigan), polyimide, other suitable dielectric materials or combinations thereof. In some embodiments, dielectric layer 502 includes a low-k dielectric material, which generally refers to a dielectric material with a lower dielectric constant relative to the dielectric constant of silicon dioxide (k≈3.9). For example, a low-k dielectric material has a dielectric constant of less than about 3.9. In some embodiments, a low-k dielectric material has a dielectric constant of less than about 2.5, and such a low-k dielectric material may be referred to as an extreme low-k (ELK) dielectric material. CESL may be part of dielectric layer 502 and include a dielectric material different from the dielectric material of the ILD layer. The ILD layer and / or CESL may include a multilayer structure having multiple dielectric materials. In the depicted embodiment where the ILD layer includes silicon and oxygen (e.g., SiCOH, SiOx, or other materials including silicon and oxygen), the CESL layer includes nitrogen and / or carbon (e.g., SiN, SiCN, SiCON, SiON, SiC, SiCO, metal nitrides, and / or metal carbonitrides). The ILD layer and / or CESL are formed by a deposition process such as CVD, PVD, ALD, HDPCVD, MOCVD, RPCVD, PECVD, LPCVD, ALCVD, APCVD, PEALD, other suitable methods, or combinations thereof. In some embodiments, the dielectric layer 502 is formed by a flowable CVD (FCVD) process, which includes, for example, depositing a flowable material (e.g., a liquid compound) over the substrate 202 and converting the flowable material into a solid material by a suitable technique such as thermal annealing and / or treating the flowable material by ultraviolet radiation. After the deposition of the ILD layer and / or CESL, a chemical mechanical polish (CMP) process and / or other planarization processes are performed such that the dielectric layer 502 has a substantially planar surface and the top surface of the gate stack 302 is exposed.

[0071] At block 110, after forming the dielectric layer 502, the gate stack 302 is removed by a suitable etching process. In one embodiment, the dummy gate dielectric and / or the dummy gate electrode are removed to form a gate trench (or opening) 504, such as Figure 5A , Figure 5B , Figure 5C and Figure 5DThe gate trench 504 exposes the fin 206. The gate trench 504 also exposes the isolation feature 204. The gate trench 504 may be defined by the gate spacer 304.

[0072] Figure 1 Block 112 of method 100 includes recessing isolation features extending between active regions. The isolation features are recessed by etching within gate trenches formed by removing dummy gate structures. Fig. 6A , Figure 6B , Figure 6C , Fig.6D and Fig. 6E In an example, the isolation feature 204 is recessed in the region of the gate trench 504 to form a recess 602. The recess 602 extends continuously from the gate trench 504. In an embodiment, the isolation feature 204 is recessed, thereby removing the isolation feature 204 by approximately 2 to 10 nanometers (nm). In an embodiment, approximately 5% to 20% of the original thickness of the isolation feature 204 is removed. In some embodiments, the height of the fin extending above the isolation feature 204 is modified from the fin height FH1 to the fin height FH2. FH2 can be approximately 5% to 20% larger than FH1. In an embodiment, FH2-FH1 is equal to approximately 4 to 8 nm.

[0073] The recessing of the isolation feature may be performed by a selective etching process. In general, the selective etching process may be selective to the material of the isolation feature 204 and does not substantially etch the fin 206 and / or the gate spacer 304. In an embodiment, the etching is also selective such that the dielectric layer 502 is substantially unetched. In an embodiment, the isolation feature 204 is an oxide and is selectively etched relative to the gate spacer 304 (e.g., a nitride).

[0074] The recessing of the isolation feature may be performed by an anisotropic etching process, which generally refers to an etching process having different etching rates in different directions, such that the etching process removes material in a particular direction, such as substantially in one direction. Here, the anisotropic etching process is such that the isolation feature 204 is substantially etched vertically (e.g., having a vertical etching rate that is greater than a horizontal etching rate (in some embodiments, the horizontal etching rate is equal to zero)). The etching thus substantially removes the isolation feature material (e.g., dielectric of oxide) in the vertical direction (here, the z-direction), with minimal (to no) material removal in the horizontal direction (here, the z-direction and / or the y-direction). In some embodiments, the etching is a dry etching process, such as an RIE process that performs selective etching. The etching may remove the material of the isolation feature (e.g., silicon oxide) at a higher rate than the spacer material (e.g., nitride such as silicon nitride) and / or the fin 206 material (e.g., silicon) (i.e., the etchant has a high etching selectivity with respect to oxide).

[0075] In an embodiment, an atomic layer etch (ALE) is performed to recess the isolation features. ALE sequentially alternates between: a self-limiting chemical modification step that affects only the top atomic layer of the target material (e.g., the isolation feature); and an etching step that removes only the chemically modified region, thereby allowing the removal of individual atomic layers. In an embodiment, ALD is performed multiple times, such as 100 to 140 times. The ALE process may include a carrier gas such as argon. ALE may also include an oxygen-containing etchant such as O2, and a fluorine-containing etchant such as C4F6. In some embodiments, the selectivity of oxide (e.g., SiO2) to nitride (e.g., SiN) provided by the ALE process is greater than 10:1. In some embodiments, the selectivity of oxide (e.g., SiO2) to nitride (e.g., SiN) provided by the ALE process is greater than 11:1. ALE provides an etching process that introduces a target material (e.g., the isolation feature 204) and feeds reactants to the target material. In an embodiment, the reactants include C4F6 and O2. The reactants are deposited as free radicals. Ions are then introduced for etching, for example by bombardment. In some embodiments, the ions are argon ions. There is desorption of atomic layers removed from the target material. This process is completed as many cycles as needed to remove the desired target material thickness. In an embodiment, the process is carried out between about 100°C and 160°C. In an embodiment, the pressure of the process is between about 10 mTorr and about 20 mTorr. In some embodiments, etching can be performed by an etching tool, such as a dry plasma etching chamber.

[0076] In implementations, etching may also or alternatively include: etching a fluorine-containing etching gas, which may include fluorine (F2), fluoromethane (e.g., CH3F), difluoromethane (e.g., CH2F2), trifluoromethane (e.g., CHF3), tetrafluoromethane (e.g., CF4), hexafluoroethane (e.g., C2F6), sulfur hexafluoride (e.g., SF6), nitrogen trifluoride (e.g., NF3), other fluorine-containing etchants, or combinations thereof; hydrogen-containing etching gases (e.g., H2 and / or CH4); nitrogen-containing etching gases (e.g., N2 and / or NH3); chlorine-containing etching gases (e.g., Cl2, CHCl3, CCl4, and / or BCl3); oxygen-containing etching gases (e.g., O2); bromine-containing etching gases (e.g., HBr and / or CHBr3); iodine-containing etching gases; other suitable etching gases, or combinations thereof. In some embodiments, etching may be configured to generate plasma from any of the etching gases disclosed herein, so that etching uses plasma-excited species for etching. In some embodiments, the carrier gas is used to deliver the fluorine-containing etching gas and / or other etching gases. The carrier gas may be an inert gas, such as an argon-containing gas, a helium-containing gas, a xenon-containing gas, other suitable inert gases, or combinations thereof.

[0077] Various etching parameters of the etching may be adjusted to achieve selective and anisotropic etching of the isolation feature 204, such as etching gas composition, carrier gas composition, etching gas flow rate, carrier gas flow rate, etching time, etching pressure, etching temperature, source power, RF and / or DC bias voltage, RF and / or DC bias power, cycling (e.g., ALE), other suitable etching parameters, or combinations thereof.

[0078] In some embodiments, shielding elements can be formed over portions of substrate 202 during the selective etching of isolation features 204. For example, shielding elements can cover dielectric layer 502.

[0079] Figure 1 Block 114 of method 100 includes further modifying the channel region of the fin in the gate trench region. In some embodiments, block 114 is omitted. That is, in some embodiments, after increasing the height of fin 206 by recessing isolation feature 204, method 100 proceeds to block 116 without further modifying the channel region. In other embodiments, block 114 is performed wherein the channel of the active region is increased by modifying the width of the channel (e.g., Fig. 7A , Figure 7B , Figure 7C , Fig.7D and Fig. 7E ) and / or modify its shape (as shown in Fig. 8A , Figure 8B , Figure 8C , Fig.8D and Fig. 8E to modify it as shown in the figure).

[0080] In some embodiments of block 114, the width of the active area, such as the fin, is reduced. Fig. 7A , Figure 7B , Figure 7C , Fig.7D and Fig. 7E , the embodiment of the FinFET device 200' shows a portion of the fin 206' having a width w2, the width w2 being reduced from the width w1 (see Fig. 7A , Figure 7B ). In some embodiments, the width of the fin 206' is reduced by an etching process, also referred to as a trimming process. In an embodiment, the width w2 is at least about 10% smaller than the width w1. In some instances, the second width w2 is smaller than the first width w1 by a value in the range of about 0 to 10 nanometers. For example, the etching process may remove about 0 to 5 nanometers from each side of the fin 206 to form the fin 206'. In this example, the etching process does not reduce the width of the fin 206' below the gate spacer 304. The etching process also does not reduce the width of the fin 206' below the dielectric layer 502. The process used to reduce the width of the fin 206' may be an isotropic etching process, such as a wet etching process. The etching is selective to the silicon material of the fin 206.

[0081] In some embodiments in block 114, rounding of the active area (eg, fin) is performed. The rounding of the fin and the reduction of the width of the fin discussed above may be performed together or independently. Fig. 8A , Figure 8B , Figure 8C and Fig.8D In an example, an embodiment of a FinFET device 200" includes a fin 206" having a width w2, wherein the width w2 is substantially reduced from the width w1 similar to the FinFET device 200' discussed above. In some embodiments, the width of the fin is reduced by an etching process, also referred to as a trimming process, as discussed above. The fin 206" has a rounded tip. The tip rounding can be performed by an annealing process. In some embodiments, w2 is measured 10% below the topmost surface of the rounded fin 206". Note that the rounded tip is confined to the gate trench region.

[0082] Block 116 of method 100 includes forming a metal gate in the gate trench and on the recessed isolation feature. Fig.9A , Fig. 9B , Fig. 9C and Fig.9DIn an example of the present invention, the FinFET device 200 includes a metal gate structure 900. The metal gate structure 900 is used to achieve the desired functionality according to the design requirements of the FinFET device 200, so that one metal gate structure 900 may include the same or different layers and / or materials as the second metal gate structure. In some embodiments, the metal gate structure 900 includes a gate dielectric (e.g., a gate dielectric layer 902) and a gate electrode 904 (e.g., a work function layer and a bulk conductive layer).

[0083] The metal gate structure 900 may include numerous other layers, such as a cap layer, an interface layer, a diffusion layer, a barrier layer, a hard mask layer, or a combination thereof. In some embodiments, a gate dielectric layer 902 is disposed above the interface layer (including a dielectric material, such as silicon oxide), and a gate electrode is disposed above the gate dielectric layer. The gate dielectric layer 902 includes a dielectric material, such as silicon oxide, a high-k dielectric material, other suitable dielectric materials, or a combination thereof. Examples of high-k dielectric materials include hafnium dioxide (HfO2), HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, zirconium oxide, aluminum oxide, hafnium dioxide-aluminum oxide (HfO2-Al2O3) alloys, other suitable high-k dielectric materials, and / or combinations thereof. High-k dielectric materials generally refer to dielectric materials having a high dielectric constant relative to the dielectric constant of silicon dioxide (k≈3.9). For example, a high-k dielectric material has a dielectric constant greater than about 3.9. In some embodiments, the gate dielectric layer is a high-k dielectric layer. The gate electrode 904 includes a conductive material, such as polysilicon, Al, Cu, Ti, Ta, W, Mo, Co, TaN, NiSi, CoSi, TiN, WN, TiAl, TiAlN, TaCN, TaC, TaSiN, other conductive materials, or combinations thereof. In some embodiments, the work function layer is a conductive layer adjusted to have a desired work function (e.g., an n-type work function or a p-type work function), and the conductive bulk layer is a conductive layer formed above the work function layer. In some embodiments, the work function layer includes an n-type work function material, such as Ti, Ag, Mn, Zr, TaAl, TaAlC, TiAlN, TaC, TaCN, TaSiN, other suitable n-type work function materials, or combinations thereof. In some embodiments, the work function layer includes a p-type work function material, such as Ru, Mo, Al, TiN, TaN, WN, ZrSi2, MoSi2, TaSi2, NiSi2, WN, other suitable p-type work function materials, or combinations thereof. The bulk (or filling) conductive layer includes a suitable conductive material, such as Al, W and / or Cu. The bulk conductive layer may additionally or jointly include polysilicon, Ti, Ta, metal alloys, other suitable materials, or combinations thereof.

[0084] Due to the etch-back of the isolation feature 204 in the block 112, the thickness of the isolation feature 204 below the metal gate 900 structure is less than the thickness of the isolation feature 204 outside the metal gate structure 900, such as below the dielectric layer 502. Fig. 9C In an example of the present invention, the isolation region 204 has a thickness D2 below the metal gate structure 900 and a thickness D1 outside the metal gate structure 900. The thickness D1 is greater than the thickness D2. In an embodiment, the thickness difference between the thickness D1 and the thickness D2 (i.e., D1-D2) is between about 3 nanometers and 10 nanometers. In an embodiment, the thickness difference (i.e., D1-D2) is at least 3 nanometers.

[0085] Please note that the Fig.9A , Fig. 9B , Fig. 9C , Fig.9D and Fig.9E The FinFET device 200 in FIG. 1 is illustrated as having a recess in area 112 to provide a modified height of the fin structure, but does not include a width reduction or rounding of the fin structure in area 114. In other embodiments, the metal gate structure is formed over the fin 206' and / or the fin 206" in substantially the same manner.

[0086] Fig.10 An embodiment of a FinFET device 200 is shown in perspective view. Like numbers refer to like components. As shown, the fin 206 includes a fin height FH1 above the isolation feature 204 in the S / D region S / D, and includes a fin height FH2 above the isolation feature 204 in the channel region (C), and has a width w. The isolation feature 204 includes a sidewall extending in the z direction with a length (fin height FH2-fin height FH1). The sidewalls are interposed with a metal gate structure 900.

[0087] Block 118 of method 100 includes continued processing of the device. In some embodiments, various interconnects of multi-layer interconnect (MLI) features are formed to facilitate operation of the FinFET device 200. The MLI features electrically couple various devices (e.g., transistors, resistors, capacitors, and / or inductors) and / or elements of the FinFET device 200 (e.g., gate structures and / or source / drain features) so that the various devices and / or elements can operate as specified by the design requirements of the FinFET device. The MLI features further include a combination of dielectric layers, such as dielectric layer 502, and conductive layers used to form various interconnects. During operation of the FinFET device 200, the interconnects are used to route signals between the devices and / or elements of the FinFET device 200 and / or distribute signals (e.g., clock signals, voltage signals, and / or ground signals) to the devices and / or elements of the FinFET device 200. The conductive layer is used to form vertical interconnects, such as device-level contacts and / or vias, and / or horizontal interconnects, such as conductive wires. Vertical interconnects typically connect horizontal interconnects in different layers (or different planes) of an MLI feature. Device-level contacts (also referred to as local interconnects or local contacts) electrically and / or physically couple IC device features, such as source / drain features 402 and metal gate structures 900 to other conductive features of the MLI feature, such as vias. Device-level contacts include: metal-to-poly (MP) contacts, which typically refer to contacts to a gate structure (such as a polycrystalline gate structure or a metal gate structure); and metal-to-device (MD) contacts, which typically refer to conductive regions of a FinFET device 200, such as epitaxial source / drain features 402.

[0088] The source / drain or gate contacts include a conductive metal, such as a metal. The metal includes aluminum, an aluminum alloy (such as an aluminum / silicon / copper alloy), copper, a copper alloy, titanium, titanium nitride, tantalum, a tantalum alloy, tantalum nitride, tungsten, tungsten alloys, cobalt, a cobalt alloy, ruthenium, a ruthenium alloy, polysilicon, a metal silicide, other suitable metals, or combinations thereof. The metal silicide may include nickel silicide, cobalt silicide, tungsten silicide, tantalum silicide, titanium silicide, platinum silicide, erbium silicide, palladium silicide, or combinations thereof. In some embodiments, a damascene process and / or a dual damascene process is used to form copper-based MLI features.

[0089] Thus, provided are devices and methods that allow for increased channel region height (e.g., in the z-direction) in a multi-gate device. The methods and devices allow for a relatively reduced height (e.g., in the z-direction) of active regions (e.g., fins) outside the channel region. Height, width, and channel length are geometric dimensions that characterize the behavior of a FinFET. The devices and methods of the present disclosure allow for tuning of the fin size in the channel region differently than the fin size in other regions, where other performance characteristics (e.g., stability) may be important. Increasing the fin height in the channel region may provide a higher relative drive current for the same footprint of the device. Drain current may also be improved by increased fin height. The thickness of the fin affects short channel behavior; it may control the subthreshold swing, and thus the efficiency of the FinFET.

[0090] In one embodiment, the present disclosure provides a method, the method comprising forming a first semiconductor structure extending from a substrate along a first direction. The first semiconductor structure has a height along the first direction, and the first semiconductor structure extends longitudinally along a second direction different from the first direction. The method also comprises forming a second semiconductor structure extending from the substrate along the first direction. And the second semiconductor structure extends longitudinally along the second direction. An isolation structure is formed above the substrate and extends between the first semiconductor structure and the second semiconductor structure along a third direction different from the second direction. A dummy gate structure is formed on the substrate above the first semiconductor structure and the isolation structure. The dummy gate structure extends longitudinally along the third direction. The dummy gate structure is removed to form a trench exposing the upper surface of the isolation structure. And the isolation structure exposed in the trench is etched to make the isolation structure recessed. After etching the isolation structure, a metal gate structure is formed on the recessed isolation structure located in the trench.

[0091] In another embodiment of a method, after forming the dummy gate stack, the first semiconductor structure is recessed and a source / drain is epitaxially grown in the recessed first semiconductor structure. In one embodiment, a plurality of gate spacers are formed on the dummy gate stack. And forming a trench may form a trench defined between these gate spacers. In yet another embodiment, etching the isolation structure is a selective etch such that these gate spacers are substantially not etched. For example, the selective etching includes an etch selectivity of about 1:10 between the material of the gate spacers and the material of the isolation structure. In one embodiment, etching the isolation structure is an anisotropic etch. In one instance, the anisotropic etch is performed by atomic layer etching.

[0092] In another embodiment, the method includes etching the first semiconductor structure to reduce a dimension in a third direction after etching the isolation structure and before forming the metal gate structure. In one embodiment, a height of the first semiconductor structure along the first direction is measured from a top surface of the isolation structure, and after etching the isolation structure, the first semiconductor structure has an increased height along the first direction measured from a top surface of the isolation structure.

[0093] In another of the broader embodiments, a method is provided, the method including forming a first fin and a second fin extending above a substrate, and forming an isolation region between the first fin and the second fin. The first fin and the second fin have a first fin height above the isolation region. A gate stack is formed above the first fin, the second fin, and the isolation region. Epitaxial source / drain features are grown in the source / drain region of the first fin. After growth, the gate stack is removed to form a trench. The method continues to include selectively etching the isolation region in the trench between the first fin and the second fin. After the selective etching, the first fin has a second fin height in the trench and above the isolation region, and the second fin height is greater than the first fin height.

[0094] In one embodiment, a plurality of gate spacers are formed on the gate stack, and the selective etching includes an etch selectivity of at least greater than 10:1 between the isolation regions and the gate spacers. In one embodiment, after growing the epitaxial source / drain features, an interlayer dielectric material (ILD) is deposited. And in one embodiment, after selectively etching the isolation regions in the trench, a portion of the first fin below the interlayer dielectric material maintains the first fin height. In some embodiments, after the selective etching, the width of the first fin in the trench is trimmed (e.g., reduced). In some embodiments, the trimmed fin is annealed to round the top surface of the first fin. In one embodiment, the method continues to include forming a metal gate structure on the first fin and the second fin.

[0095] In another of the broader embodiments, a semiconductor device is provided, the semiconductor device comprising a first semiconductor structure and a second semiconductor structure, each of which extends above a substrate in a first direction and has a length extending in a second direction. An isolation structure extends between a bottom portion of the first semiconductor structure and a bottom portion of the second semiconductor structure. And a first metal gate structure is disposed above a channel region of an upper portion of the first semiconductor structure and a channel region of an upper portion of the second semiconductor structure. The first metal gate structure extends longitudinally along a third direction. An interlayer dielectric layer is disposed above the isolation structure and adjacent to the first metal gate structure. The isolation structure has a first thickness below the first metal gate structure and a second thickness below the interlayer dielectric layer, wherein the first thickness is less than the second thickness.

[0096] In one embodiment, the first semiconductor structure has a first height measured along a first direction in a channel region of an upper portion of the first semiconductor structure, and a second height measured along the first direction outside the channel region of the upper portion of the first semiconductor structure. The second height is less than the first height. The first height and the second height are measured from a top surface of the isolation structure.

[0097] In one embodiment, a semiconductor device includes a plurality of gate spacers on a plurality of sidewalls of a first metal gate structure, wherein the first semiconductor structure has a second height below the gate spacers. In one embodiment, the first semiconductor structure has a first width in a channel region of an upper portion of the first semiconductor structure and a second width outside the channel region of the upper portion of the first semiconductor structure, the first width being less than the second width.

[0098] In one embodiment, a semiconductor device includes a substrate, a first fin, a second fin, an isolation region, and a metal gate structure. The first fin and the second fin extend above the substrate. The isolation region is between the first fin and the second fin. The metal gate structure is above the first fin, the second fin, and the isolation region. The isolation region has a first thickness outside the metal gate structure, and the isolation region has a second thickness below the metal gate structure, and the first thickness is greater than the second thickness.

[0099] In one embodiment, the difference between the first thickness and the second thickness is between 3 nanometers and 10 nanometers.

[0100] In one embodiment, the first fin and the second fin below the metal gate structure each have a rounded tip.

[0101] In one embodiment, a semiconductor device includes a substrate, a fin, an isolation region, a metal gate structure, and an interlayer dielectric layer. The fin extends above the substrate. The isolation region is next to the fin. The metal gate structure is above the fin and the isolation region. The interlayer dielectric layer is above the fin and the isolation region and adjacent to the metal gate structure. The isolation region has a first thickness below the metal gate structure and a second thickness below the interlayer dielectric layer, wherein the first thickness is less than the second thickness.

[0102] In one embodiment, the fin under the interlayer dielectric layer has a first fin height above the isolation region, and the fin under the metal gate structure has a second fin height above the isolation region, and the second fin height is greater than the first fin height.

[0103] In one embodiment, the fin under the interlayer dielectric layer has a first width, and the fin under the metal gate structure has a second width, and the first width is greater than the second width.

[0104] The foregoing summarizes the features of some embodiments so that those skilled in the art can better understand the aspects of the present disclosure. Those skilled in the art should understand that they can readily use the present disclosure as a basis for designing or modifying other processes and structures for implementing the same purposes and / or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and such equivalent constructions may be variously changed, substituted, and replaced herein without departing from the spirit and scope of the present disclosure.

Claims

1. A semiconductor device, characterized in that: Include: A first semiconductor structure and a second semiconductor structure, each extending above a substrate along a first direction and having a length extending along a second direction; an isolation structure extending between a bottom portion of the first semiconductor structure and a bottom portion of the second semiconductor structure; a first metal gate structure disposed above a channel region of an upper portion of the first semiconductor structure and a channel region of an upper portion of the second semiconductor structure, wherein the first metal gate structure extends longitudinally along a third direction; an interlayer dielectric layer disposed above the isolation structure and adjacent to the first metal gate structure; and The isolation structure has a first thickness below the first metal gate structure and a second thickness below the interlayer dielectric layer, wherein the first thickness is smaller than the second thickness.

2. The semiconductor device according to claim 1, wherein The first semiconductor structure has a first height measured along the first direction in the channel region of the upper part of the first semiconductor structure, and has a second height measured along the first direction outside the channel region of the upper part of the first semiconductor structure, and the second height is less than the first height, wherein the first height and the second height are measured from a top surface of the isolation structure.

3. The semiconductor device according to claim 2, wherein: The method further comprises: a plurality of gate spacers on a plurality of sidewalls of the first metal gate structure, wherein the first semiconductor structure has the second height below the plurality of gate spacers.

4. The semiconductor device according to any one of claims 1 to 3, wherein: The first semiconductor structure has a first width in the channel region of the upper portion of the first semiconductor structure and a second width outside the channel region of the upper portion of the first semiconductor structure, and the first width is smaller than the second width.

5. A semiconductor device, characterized in that: Include: a substrate; A first fin and a second fin extending above the substrate; an isolation region between the first fin and the second fin; and a metal gate structure, above the first fin, the second fin and the isolation region, The isolation region has a first thickness outside the metal gate structure, and the isolation region has a second thickness below the metal gate structure, and the first thickness is greater than the second thickness.

6. The semiconductor device according to claim 5, wherein: A thickness difference between the first thickness and the second thickness is between 3 nanometers and 10 nanometers.

7. The semiconductor device according to claim 5 or claim 6, wherein: The first fin and the second fin below the metal gate structure each have a rounded tip.

8. A semiconductor device, characterized in that: Include: a substrate; a fin extending above the substrate; an isolation zone adjacent to the fin; a metal gate structure over the fin and the isolation region; as well as an interlayer dielectric layer above the fin and the isolation region and adjacent to the metal gate structure, The isolation region has a first thickness below the metal gate structure and a second thickness below the interlayer dielectric layer, wherein the first thickness is smaller than the second thickness.

9. The semiconductor device according to claim 8, wherein: The fin below the interlayer dielectric layer has a first fin height above the isolation region, and the fin below the metal gate structure has a second fin height above the isolation region, and the second fin height is greater than the first fin height.

10. The semiconductor device according to claim 8 or claim 9, wherein: The fin under the interlayer dielectric layer has a first width, and the fin under the metal gate structure has a second width, and the first width is greater than the second width.

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