Anti-crosstalk full-color micro display device

Abstract

The utility model discloses an anti-crosstalk full-color micro display device, and relates to the technical field of semiconductors. The full-color micro display device comprises a driving wafer and a display module integrated with the driving wafer through a bonding metal layer, wherein the display module at least comprises a display device layer and a color conversion layer which are stacked in the vertical direction; the display device layer comprises a pixel unit and a metal fence surrounding the pixel unit, and the metal fence is of a fence type structure generated in the process of etching the bonding metal layer through ion beams; an upper optical cavity is prepared in the surface, away from the driving wafer, of the display device layer, the projection of the pixel units on the driving wafer is located in the projection of the upper optical cavity on the driving wafer, and the upper optical cavity is filled with the color conversion layer; the metal fence and the upper optical cavity are used for restraining the light-emitting angle of the pixel unit.

Description

Technical Field

[0001] The utility model relates to the technical field of semiconductors, in particular to a full-color micro display device capable of preventing crosstalk. Background Art

[0002] Micro-LEDs have the advantages of high contrast, low power consumption, long life, and fast response speed. They have great application potential in virtual reality / augmented reality, visible light communication, biomedicine, flexible displays, wearable devices, and other fields.

[0003] Full colorization is an important research direction in the development of Micro-LED display technology. Full-color micro-display devices can be prepared through color conversion technology. Specifically, color conversion technology uses ultraviolet or blue light to excite the red and green quantum dot fluorescent materials coated on the Micro-LED pixel unit, thereby achieving high-resolution and high-efficiency full-color display technology. It has the characteristics of low technical threshold, low cost, and easy industrialization, and has attracted widespread attention.

[0004] For full-color micro-display devices prepared by color conversion technology, a black matrix is ​​generally used to solve the optical crosstalk between pixel units. Utility Model Content

[0005] The utility model aims to provide a full-color micro display device with crosstalk prevention, which double-constrains the light-emitting angle of a pixel unit through the combined structure of a metal fence and an upper optical cavity, thereby effectively avoiding crosstalk between adjacent pixel units in the full-color micro display device.

[0006] In order to achieve the above-mentioned utility model purpose, the utility model proposes the following technical solutions:

[0007] On the one hand, a full-color micro display device with crosstalk prevention is provided, the full-color micro display device comprising: a driving wafer, a display module integrated with the driving wafer through a bonding metal layer, the display module comprising at least: a display device layer and a color conversion layer stacked in a vertical direction;

[0008] The display device layer includes: a pixel unit and a metal fence surrounding the pixel unit, wherein the metal fence is a fence-style structure generated during the bonding metal layer by ion beam etching (IBE);

[0009] An upper optical cavity is prepared on the surface of the display device layer away from the driving wafer, the projection of the pixel unit on the driving wafer is located within the projection of the upper optical cavity on the driving wafer, and the upper optical cavity is filled with the color conversion layer;

[0010] Wherein, the metal fence and the upper optical cavity are used to constrain the light-emitting angle of the pixel unit.

[0011] In a possible implementation manner, a projection of the metal fence on the driving wafer is located within a projection of the upper optical cavity on the driving wafer.

[0012] In a possible implementation, one end of the metal fence is connected to a surface of the driving wafer close to the display device layer, and the other end is separated from the upper optical cavity by a preset distance.

[0013] In a possible implementation manner, a ratio between a height of the upper optical cavity and a width of the upper optical cavity is between 2:1 and 10:1.

[0014] In a possible implementation manner, a first insulating layer is further included between the color conversion layer and the display device layer, and a multi-ring structure is provided in the first insulating layer.

[0015] In a possible implementation, the pixel unit at least includes: the bonding metal layer, the P-type ohmic contact layer, the compound semiconductor layer and the N-type ohmic contact layer vertically stacked in sequence in a direction away from the driving wafer;

[0016] The sidewall of the metal fence contacts the sidewalls of the bonding metal layer and the P-type ohmic contact layer, and is spaced apart from the sidewalls of the compound semiconductor layer and the N-type ohmic contact layer.

[0017] In a possible implementation manner, the display device layer further includes:

[0018] a second insulating layer, the second insulating layer filling the blank space of the display device layer;

[0019] A common cathode, the common cathode is covered on the second insulating layer and connected to the N-type ohmic contact layer on the top of the pixel unit;

[0020] Wherein, the upper optical cavity is prepared on the common cathode.

[0021] In a possible implementation manner, the common cathode and the upper optical cavity are made of metal material, and the common cathode is continuous or discontinuous.

[0022] In a possible implementation manner, a third insulating layer is disposed on the color conversion layer.

[0023] Compared with the prior art, the utility model has the following beneficial effects:

[0024] The driving wafer and display module in the full-color micro-display device are bonded and integrated through a bonding metal layer. The display module includes a display device layer and a color conversion layer. Due to physical characteristics, a metal fence is inevitably formed through the process of ion beam etching the bonding metal layer. This metal fence is fully utilized to form an optical resonant cavity for the pixel unit in the display device layer, and the color conversion layer is set in the upper optical cavity of the display device layer. The combined structure of the metal fence and the upper optical cavity is used to doubly constrain the light-emitting angle of the pixel unit, thereby effectively avoiding crosstalk between adjacent pixel units in the full-color micro-display device.

[0025] Furthermore, the metal fence and the upper optical cavity are made of inorganic materials with high reliability, avoiding affecting the integrity of the full-color micro-display device. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] Figure 1 is a schematic structural diagram of a full-color micro-display device provided in an embodiment of the present application;

[0027] Figure 2 is a schematic structural diagram of a full-color micro-display device provided in an embodiment of the present application;

[0028] Figure 3 is a schematic structural diagram of a full-color micro-display device provided in an embodiment of the present application;

[0029] Figure 4 is a method flow chart of a method for preparing a full-color micro-display device provided in an embodiment of the present application;

[0030] Figure 5 It is a schematic diagram of the structure after a compound wafer and a driver wafer are bonded and integrated provided in an embodiment of the present application;

[0031] Figure 6 It is a schematic diagram of the structure of a compound wafer after a P-type ohmic contact layer is prepared according to an embodiment of the present application;

[0032] Figure 7 It is a schematic diagram of the structure of a compound wafer after a bonding metal layer is prepared according to an embodiment of the present application;

[0033] Figure 8 It is a schematic structural diagram of a driver wafer after a bonding metal layer is prepared according to an embodiment of the present application;

[0034] Fig. 9 It is a schematic diagram of the structure after a compound wafer and a driver wafer are bonded and integrated provided in an embodiment of the present application;

[0035] Fig.10 is a schematic diagram of the structure of a continuous film layer in a display area provided in an embodiment of the present application;

[0036] Fig.11 It is a schematic diagram of a structure after removing the substrate of a compound wafer provided in an embodiment of the present application;

[0037] Fig.12 It is a structural schematic diagram of completing pixelation preparation of a compound wafer provided in an embodiment of the present application;

[0038] Fig.13 It is a structural schematic diagram of a full-color micro display device after a photoresist layer is prepared according to an embodiment of the present application;

[0039] Fig.14 It is a structural schematic diagram of a full-color micro-display device prepared by a metal fence provided in an embodiment of the present application;

[0040] Fig.15 is a structural schematic diagram of a full-color micro-display device after the photoresist layer is removed provided in an embodiment of the present application;

[0041] Fig.16 It is a schematic diagram of a structure of a common cathode connected to each other provided in an embodiment of the present application;

[0042] Fig.17 is a schematic structural diagram of a disconnected common cathode provided in an embodiment of the present application;

[0043] Fig.18 It is a structural schematic diagram of a full-color micro-display device after the upper optical cavity is prepared provided in an embodiment of the present application.

[0044] Reference numerals:

[0045] 100-driving wafer, 200-display device layer, 300-color conversion layer, 400-compound wafer, 10-pixel unit, 11-bonding metal layer, 12-P-type ohmic contact layer, 13-compound semiconductor layer, 14-N-type ohmic contact layer, 20-metal fence, 30-upper optical cavity, 40-first insulating layer, 50-multi-ring structure, 60-second insulating layer, 70-common cathode, 80-photoresist layer. DETAILED DESCRIPTION

[0046] In order to make the purpose, technical solution and advantages of the utility model clearer, the technical solution in the embodiment of the utility model will be clearly and completely described below in conjunction with the drawings in the embodiment of the utility model. Obviously, the described embodiment is only a part of the embodiment of the utility model, not all of the embodiments. Based on the embodiment of the utility model, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the utility model.

[0047] In the description of the present utility model, it should be understood that the terms "vertical", "upper", "lower", "top", "side", "inner", "outer" and the like indicate orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the present utility model. In addition, the terms "first" and "second" are used for descriptive purposes only, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Therefore, the features defined as "first" and "second" may explicitly or implicitly include one or more of the features. In the description of the present utility model, unless otherwise specified, "multiple" means two or more.

[0048] In the description of the present invention, it should be noted that, unless otherwise clearly specified and limited, the terms "installation", "connection" and "connection" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection, or it can be indirectly connected through an intermediate medium, or it can be the internal communication of two components. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0049] In the related art, a black matrix structure is often used to avoid crosstalk between pixel units in full-color micro-display devices. Specifically, in this type of full-color micro-display device, a color conversion layer is used to cover the pixel unit, and the light output of the pixel unit can be converted into color through the color conversion layer, and a black matrix structure surrounding the pixel unit is used around the pixel unit to avoid crosstalk between the light outputs of adjacent pixel units.

[0050] Since the black matrix structure has the defect of poor high temperature resistance, it will affect the overall performance of the full-color micro-display device.

[0051] In order to avoid the above problems, in an embodiment of the present application, a new anti-crosstalk solution is proposed for a full-color micro-display device, in which a color conversion layer is disposed in an optical cavity above the pixel unit, and the pixel unit is surrounded by a metal fence generated during the IBE metal etching process. The light-emitting angle of the pixel unit is doubly constrained by the combined structure of the metal fence and the optical cavity above.

[0052] First, the specific structure of the full-color micro-display device proposed in this application is described.

[0053] The present application embodiment provides a full-color micro display device, such as Figure 1 , Figure 2As shown, the full-color micro display device includes: a driving wafer 100, and a display module integrated with the driving wafer 100 through a bonding metal layer 11, and the display module at least includes: a display device layer 200 and a color conversion layer 300 stacked in a vertical direction.

[0054] The display device layer 200 includes: a pixel unit 10, and a metal fence 20 surrounding the pixel unit 10, wherein the metal fence 20 is a fence-style structure produced in the process of ion beam etching the bonding metal layer 11; an upper optical cavity 30 is prepared on the surface of the display device layer 200 away from the driving wafer 100, and the projection of the pixel unit 10 on the driving wafer 100 is located within the projection of the upper optical cavity 30 on the driving wafer 100, and the upper optical cavity 30 is filled with a color conversion layer 300.

[0055] The metal fence 20 and the upper optical cavity 30 are used to restrict the light emitting angle of the pixel unit 10 .

[0056] It is understandable that the driving wafer 100 and the pixel unit 10 may be in a one-to-one relationship or a one-to-many relationship, that is, the driving wafer 100 may include only one anode contact, and one pixel unit 10 electrically connected to the anode contact is correspondingly provided, or the driving wafer 100 may include multiple anode contacts, and multiple pixel units 10 electrically connected to the anode contacts are correspondingly provided. In addition, the corresponding relationship between the anode contact and the pixel unit 10 may be one-to-one, or multiple anode contacts may correspond to one pixel unit 10.

[0057] Among them, the driving wafer 100 can be an active design that combines one or more of a thin film transistor (TFT), a low temperature polycrystalline silicon (LTPS), a CMOS integrated circuit, a high mobility transistor (HEMT), etc. Specifically, the driving wafer 100 is provided with a driving circuit, and the driving circuit is provided with at least one anode contact. The driving circuit may include an active, passive or semi-passive control circuit. All anode contacts included in the driving circuit may be arranged linearly or in an array, and any anode contact is located in the middle or at the edge of the driving wafer 100, which is not limited in this embodiment.

[0058] Among them, the pixel unit 10 in the display module is usually a compound wafer or a suitable size area cut from a compound wafer. Taking a compound wafer as an example, the wafer refers to a compound formed by two or more elements, including crystalline inorganic compounds (such as III-V group, II-VI group compound semiconductors) and oxide semiconductors. The compound wafer involved in the embodiment of the present application is mainly an LED epitaxial material, such as an InGaN ternary material system or an AlGaInP quaternary material system, etc., and its luminous wavelength can cover the entire band from ultraviolet, visible light and infrared, and its substrate material can be GaN, Si, SiC, Sapphire, etc.

[0059] Taking the Micro-LED field as an example, the materials of some compound wafers involved in this application are shown in the following table. In some practical applications, the film layer of the compound wafer will be more complicated, or there will be cross-use of materials. It typically mainly includes a P-type ohmic contact layer, an N-type ohmic contact layer, and a multiple quantum well (MQW) sandwiched between the two and other functional layers. In this application, the functional layer between the P-type ohmic contact layer and the N-type ohmic contact layer is recorded as a compound semiconductor layer:

[0060]

[0061] Among them, the driving wafer 100 and the display module are bonded and integrated through the bonding metal layer 11. The material of the bonding metal layer 11 can be a combination of multiple metal materials, such as: Ni, Sn combination, Au, Sn combination, Cu, Sn combination, Au, In combination, Au, Au combination, Al, Al combination, Cu, Cu combination, ITO, ITO combination, etc. One or more. Further, the bonding metal layer 11 and the driving wafer 100 / display module can also include an adhesion layer and a blocking depletion layer to form a bonding structure together. Among them, the adhesion layer is used to increase the adhesion between the upper and lower layers, and the material of the adhesion layer can be Cr, Ti, Ni, etc. The blocking depletion layer is used to block the migration of the metal, and the material of the blocking depletion layer can be Ni, Pt, Cu, etc. Further, the bonding structure on the driving wafer 100 and the display module can be symmetrical or asymmetrical. If necessary, a reflective layer such as Al, Ag, Au, etc. can be introduced into the bonding structure.

[0062] Exemplarily, using AuSn bonding, the bonding structure on the surface of the display module is Ni (10A, adhesion layer) / AlCu (80nm, reflective layer) / NiV (10nm, blocking layer) / Au (100nm) / Sn (150nm) / Au (50nm), and the bonding structure on the surface of the driving wafer 100 is Cr (10nm, adhesion layer) / Pt (50nm, blocking depletion layer) / Au (100nm) / Sn (150nm) / Au (50nm).

[0063] Exemplarily, using CuCu bonding, the bonding structure on the surface of the display module is Ni (10A, adhesion layer) / AlCu (80nm, reflective layer) / NiV (10nm, barrier layer) / Cu (300nm, bonding layer), and the bonding structure on the surface of the driving wafer 100 is Ti (20nm, adhesion layer) / Cu (300nm, bonding layer).

[0064] The display module is provided with a metal fence 20 surrounding the pixel unit 10, and the metal fence 20 is a fence-style structure generated in the process of IBE isolating the bonding metal layer 11. Specifically, after the display module and the driving wafer 100 are integrated through the bonding metal layer 11 and the pixel unit 10 is prepared, when the bonding metal layer 11 is patterned by IBE etching, the metal atoms corresponding to the bonding metal layer 11 are re-sputtered and deposited to form the metal fence 20 surrounding the pixel unit 10.

[0065] In the present application, the metal fence 20 is fully utilized. The metal fence 20 forms a cylindrical optical resonant cavity for the pixel unit 10. The optical resonant cavity is a cavity in which light waves can reflect back and forth to provide optical positive feedback. It is usually composed of two or more optical reflective mirrors (implemented by the metal fence 20 in the present application). Because of its role in enhancing and regulating light energy, it is widely used in optical fields such as lasers. In the present application, the light waves emitted by the pixel unit 10 circle around in the optical resonant cavity, connected head to tail, forming constructive interference, and all the light energy is bound in the resonant cavity, which increases the energy density per unit volume of the resonant cavity, thereby greatly improving the luminous efficiency of the microdisplay device. At the same time, the structure does not require a fence elimination process. It can be understood that the present application does not limit the specific style of the optical resonant cavity formed by the metal fence 20, such as a rectangular column style or a cylindrical style.

[0066] Among them, an upper optical cavity 30 is prepared on the surface of the display device layer 200 away from the driving wafer 100. When the projection of the pixel unit 10 on the driving wafer 100 is located within the projection of the upper optical cavity 30 on the driving wafer 100, the light emitted upward from the display device layer 200 by the pixel unit 10 will pass through the upper optical cavity 30, and the light-emitting angle is constrained by the upper optical cavity 30. The upper optical cavity 30 can be an alloy or laminate of a metal material, such as an alloy of Al, AlCu, AlNi, etc., an Al / TiN, AlCu / TiN laminate, a laminate of metals such as Al / Ni / Ti / Au, or an alloy or laminate of metals such as Au / Ge / Ni / Au.

[0067] Furthermore, the projection of the metal fence 20 on the driver wafer 100 is within the projection of the upper optical cavity 30 on the driver wafer 100. A portion of the light emitted by the pixel unit 10 may not be completely constrained by the metal fence 20. Therefore, the projection range of the upper optical cavity 30 is set to be larger than the projection range of the metal fence 20, so as to effectively process the light emitted upward from the display device layer 200 after the pixel unit 10 is constrained by the metal fence 20.

[0068] Further, one end of the metal fence 20 is connected to a side of the driving wafer 100 close to the display device layer 200, and the other end is separated from the upper optical cavity 30 by a preset distance. In order to avoid the short circuit of the full-color micro display device caused by the connection between the metal fence 20 and the upper optical cavity 30, the top of the metal fence 20 is set to be separated from the upper optical cavity 30 by a preset distance. Exemplarily, the distance between the top of the metal fence 20 and the bottom of the upper optical cavity 30 is not less than 50nm.

[0069] Furthermore, the ratio between the height of the upper optical cavity 30 and the width of the upper optical cavity 30 is between 2:1 and 10:1. In the present application, the upper optical cavity 30 is designed to have a larger aspect ratio, specifically, the aspect ratio is between 2:1 and 10:1. The larger the aspect ratio, the larger the cavity formed by the upper optical cavity 30, which can be used to carry the color conversion layer 300 and other optical structures.

[0070] The upper optical cavity 30 is filled with a color conversion layer 300, which is used to convert the color of the light emitted by the pixel unit 10. The color conversion layer 300 may be a functional material such as quantum dots and phosphors. The present application does not limit the specific material of the color conversion layer 300. The color conversion layer 300 may be a whole surface or may be patterned. Furthermore, the height of the top of the color conversion layer 300 may be higher than the height of the upper optical cavity 30, may be flush with the height of the upper optical cavity 30, or may be lower than the height of the upper optical cavity 30.

[0071] In one possible implementation, Figure 3 As shown, a first insulating layer 40 is further included between the color conversion layer 300 and the display device layer 200, and a multi-ring structure 50 is arranged in the first insulating layer 40. The multi-ring structure 50 refers to a ring-shaped structure formed by multiple ring structures nested with each other, and the height of the multi-ring structure 50 is less than the height of the optical cavity 30 above.

[0072] The first insulating layer 40 is mainly silicon oxide, and optionally includes silicon oxide, aluminum oxide, silicon nitride, aluminum nitride, and a combination thereof, which is not limited in the present application. The multi-ring structure 50 can be made of metal material to form a metal multi-ring structure, or it can be embedded in the first insulating layer 40 in the form of an internally unfilled material to form a dielectric multi-ring structure.

[0073] Exemplarily, the distance between each ring structure in the multi-ring structure 50 is n*λ / 4, and the distance between each ring structure can be the same or different, and the distance between the multi-ring structure 50 and the upper optical cavity 30 around it is also n*λ / 4, where n is a positive integer and λ is the wavelength. At this spacing, the light is more sensitive to refraction and oscillation, which can further enhance the optical resonant cavity.

[0074] In a possible implementation, the pixel unit 10 includes at least the following layers, which are stacked vertically in sequence along a direction away from the driving wafer 100: a bonding metal layer 11, a P-type ohmic contact layer 12, a compound semiconductor layer 13, and an N-type ohmic contact layer 14; the bottom of the metal fence 20 is connected to a side of the driving wafer 100 close to the display module; the side walls of the metal fence 20 are in contact with the side walls of the bonding metal layer 11 and the P-type ohmic contact layer 12, and are spaced apart from the side walls of the compound semiconductor layer 13 and the N-type ohmic contact layer 14.

[0075] The surface dimensions corresponding to the bonding metal layer 11 and the P-type ohmic contact layer 12 are larger than the surface dimensions corresponding to the compound semiconductor layer 13 and the N-type ohmic contact layer 14. The projections of the compound semiconductor layer 13 and the N-type ohmic contact layer 14 on the driving wafer 100 are within the projections of the bonding metal layer 11 and the P-type ohmic contact layer 12 on the driving wafer 100. Therefore, the metal fence 20 extending in the vertical direction may have a bottom sidewall in contact with the sidewalls of the bonding metal layer 11 and the P-type ohmic contact layer 12, and a top sidewall may be spaced apart from the sidewalls of the compound semiconductor layer 13 and the N-type ohmic contact layer 14, thereby preventing the P-type ohmic contact layer 12 and the N-type ohmic contact layer 14 of the pixel unit 10 from being short-circuited through the metal fence 20, causing leakage.

[0076] It is understandable that since the metal fence 20 is formed by metal atoms being reversely sputtered and deposited during the IBE etching process, in practice, the thickness of the metal fence 20 may vary in the vertical direction, specifically, the thickness gradually becomes thinner from the bottom to the top.

[0077] In a possible implementation, the display device layer 200 also includes: a second insulating layer 60, which fills the blank space of the display device layer 200; a common cathode 70, which is covered on the second insulating layer 60 and connected to the N-type ohmic contact layer 14 on the top of the pixel unit 10; wherein the upper optical cavity 30 is prepared on the common cathode 70.

[0078] like Figure 1 , Figure 2 As shown, by filling the second insulating layer 60 in the display module, the optical resonant cavity formed by the metal fence 20 can be fixed, and the top metal fence 20 can be insulated and isolated from the pixel unit 10, further avoiding the situation where the P-type ohmic contact layer 12 and the N-type ohmic contact layer 14 of the pixel unit 10 are short-circuited through the metal fence 20 to cause leakage. The second insulating layer 60 is mainly silicon oxide, and optionally includes silicon oxide, aluminum oxide, silicon nitride, aluminum nitride and a combination of these, which is not limited in the present application.

[0079] like Figure 1 , Figure 2 As shown, an N-type ohmic contact layer 14 is exposed on the top of the pixel unit 10 , and a common cathode 70 connected to the exposed N-type ohmic contact layer 14 is prepared on a surface of the second insulating layer 60 away from the driving wafer 100 .

[0080] Furthermore, the common cathode 70 and the upper optical cavity 30 are made of metal materials, and the cathode electrical performance of the micro display device is enhanced by the common cathode 70 and the upper optical cavity 30 made of metal materials. In addition, the common cathode 70 can form a single-side, double-side, or multi-side contact with the N-type ohmic contact layer of the pixel unit 10, so that the common cathode 70 can be continuous or discontinuous.

[0081] In a possible implementation, a third insulating layer is provided on the color conversion layer 300. The third insulating layer can be used to isolate the color conversion layer 300 from water vapor. The third insulating layer is mainly silicon oxide, and optionally, the insulating layer is a single layer or a combination of oxides such as silicon oxide, aluminum oxide, silicon nitride, and aluminum nitride, which is not limited in the present application.

[0082] Exemplarily, the dimension data of the micro display device introduced in the above embodiment is illustrated as an example, the width of the insulating layer between the metal fence 20 and the side wall of the pixel unit 10 is denoted as D1, the width of the metal fence 20 is denoted as d, the height is denoted as h, the width of the pixel unit 10 is denoted as D2, the height is denoted as H, and the spacing between the outsides of two adjacent metal fences 20 is denoted as D3, which may have the following dimension data: 50nm≤D1≤D2 / 2; 110nm≤D2≤1000um; 28nm≤d≤1um; 50nm≤h≤H; 180nm≤H≤5um; 90nm≤D3≤D2 / 2.

[0083] In summary, in the full-color micro-display device provided in the embodiment of the present application, the driving wafer and the display module in the full-color micro-display device are bonded and integrated through a bonding metal layer. The display module includes a display device layer and a color conversion layer. Due to the physical characteristics, a metal fence is inevitably formed through the process of ion beam etching the bonding metal layer. The metal fence is fully utilized to form an optical resonant cavity for the pixel unit in the display device layer, and the color conversion layer is arranged in the upper optical cavity of the display device layer. The light-emitting angle of the pixel unit is doubly constrained by the combined structure of the metal fence and the upper optical cavity, thereby effectively avoiding crosstalk between adjacent pixel units in the full-color micro-display device.

[0084] Furthermore, the metal fence and the upper optical cavity are made of inorganic materials with high reliability, avoiding affecting the integrity of the full-color micro-display device.

[0085] Next, the preparation method of the full-color micro-display device described in the above embodiment is described. Figure 4 As shown, the method may include the following steps:

[0086] S1: Prepare the drive wafer.

[0087] Specifically, the driver wafer includes anode contacts in a vertical direction, and an insulating medium is arranged around the anode contacts.

[0088] S2: Prepare a display module integrated with a driving wafer through a bonding metal layer, the display module at least comprising: a display device layer and a color conversion layer stacked in a vertical direction; the display device layer comprises: a pixel unit, and a metal fence surrounding the pixel unit, the metal fence is a fence-style structure generated in the process of ion beam etching the bonding metal layer; an upper optical cavity is prepared on the surface of the display device layer away from the driving wafer, the projection of the pixel unit on the driving wafer is located within the projection of the upper optical cavity on the driving wafer, and the upper optical cavity is filled with a color conversion layer.

[0089] Among them, the metal fence and the upper optical cavity are used to constrain the light-emitting angle of the pixel unit.

[0090] Wherein, S2 may specifically include the following steps S21 to S26:

[0091] S21: The compound wafer and the driver wafer are bonded and integrated via a bonding metal layer.

[0092] Specifically, since bonding metal has been deposited on the surfaces of the compound wafer and the driver wafer, the bonding metal on the surfaces of the two wafers is used to form a bonding metal layer, and the two wafers are integrated together by wafer-level thermal compression bonding to form a bonding metal layer. Figure 5 The structure shown, Figure 5 In the structure shown, the bonding metal layer is continuous across the entire surface of the wafer.

[0093] In a possible implementation, step S21 specifically includes the following steps:

[0094] (1) Prepare a P-type ohmic contact layer on the P-side of the compound wafer.

[0095] Specifically, Figure 6 As shown, a P-type ohmic contact layer 12 is prepared on the P surface of the compound wafer 400, and its P-type contact material can be a transparent conductive material such as ITO, ZnO, etc., or a metal material such as Ni whose work function is greater than the work function of the P-type semiconductor.

[0096] In one embodiment, a Si-based blue light InGaN compound is selected as a compound wafer, and an ITO film is coated on its P surface by evaporation, sputtering, etc. The ITO film thickness is 70nm, and an ohmic contact is formed by high-temperature annealing at 550°C in an N2 environment. The thickness of the P-type ohmic contact layer on the surface of the compound wafer and the conditions for forming the contact can be adjusted according to needs.

[0097] (2) Bonding metal layers are respectively prepared on the surface of the P-type ohmic contact layer of the compound wafer and the surface of the driving wafer, and at least one of the two bonding metal layers is continuous in the pixel area and supported by an insulating medium in the non-pixel area.

[0098] Specifically, Figure 7 As shown, a bonding metal is deposited on the P-type ohmic contact layer 12 by a general semiconductor thin film growth method such as plasma vapor deposition, evaporation, sputtering, atomic layer deposition (ALD), etc. to form a bonding metal layer 11. Accordingly, as shown in FIG. Figure 8 As shown, bonding metal is also deposited on the surface of the driving wafer 100 to form another bonding metal layer 11 .

[0099] The bonding metal layer may be continuous only in the pixel region, which is the region for preparing the pixel unit, but a discontinuous film layer in the non-pixel region, which is filled with an insulating medium for support, such as Fig. 9 As shown, the bonding metal layer on the surface of the compound wafer 400 is continuous only in the pixel area, and the bonding metal layer on the surface of the driving wafer 100 is continuous over the entire surface of the wafer. Fig.10 As shown, the granularity of the continuous film layer can be a single display area or multiple display areas, and each display area corresponds to a micro display chip.

[0100] (3) The compound wafer and the driver wafer are bonded and integrated via the bonding metal layers on their respective surfaces.

[0101] S22: performing pixelation processing on the compound wafer to prepare pixel units.

[0102] Specifically, the substrate of the compound wafer is removed by a substrate removal method. After the substrate is removed, Fig.11 As shown, the N-type ohmic contact layer 14 in the compound wafer 400 is exposed on the surface of the compound wafer 400, and then through semiconductor lithography and etching processes, such as Fig.12 As shown, the compound wafer 400 is patterned to prepare pixels with the P-type ohmic contact layer 12 as the etching stop layer, and the pixel unit 10 corresponds to the anode contact in the driving wafer 100, and the pixel unit 10 can cover the corresponding anode contact.

[0103] Among them, the substrate removal method can adopt corresponding process methods according to different substrate materials, such as laser stripping to remove sapphire substrate, HNA wet etching to remove silicon substrate, etc., and this application does not limit this.

[0104] S23: Patterning the bonding metal layer by ion beam etching to generate a metal fence surrounding the pixel unit.

[0105] Specifically, step S23 can be replaced by the following steps:

[0106] (1) Fig.13 As shown, a photoresist mask is used to cover the top and side surfaces of the pixel unit 10 to form a photoresist layer 80 .

[0107] The photoresist may be of positive polarity or reverse polarity, which is not limited in the present application.

[0108] (2) Fig.14 As shown, the bonding metal layer 11 is patterned by ion beam etching using the photoresist layer 80 as a mask to generate a metal fence 20 surrounding the pixel unit 10 .

[0109] (3) Fig.15 As shown, the photoresist layer 80 is removed.

[0110] S24: The cathode of the pixel unit is electrically connected to form a common cathode covering the display device layer, and the common cathode is connected to the N-type ohmic contact layer on the top of the pixel unit.

[0111] S25: preparing an upper optical cavity above the common cathode, wherein a projection of the metal fence on the driver wafer is within a projection of the upper optical cavity on the driver wafer.

[0112] In a possible implementation, the common cathode and the upper optical cavity may be prepared together by metal coating. Specifically, step S24 and step S25 may be replaced by the following steps:

[0113] (1) The blank space in the display device layer is filled with an insulating dielectric to form a second insulating layer.

[0114] The second insulating layer may be formed by chemical vapor deposition (CVD), physical vapor deposition (PVD), ALD, spin coating, etc.

[0115] (2) The second insulating layer is planarized or patterned and etched to expose the N-type ohmic contact layer of the pixel unit.

[0116] (3) Performing metal plating on the N-type ohmic contact layer to form a metal layer, wherein the metal layer includes a common cathode.

[0117] Specifically, the entire surface may be plated with a metal film by evaporation or sputtering to form a metal layer including the common cathode.

[0118] (4) The metal layer is patterned and etched to obtain the upper optical cavity.

[0119] In another possible implementation, the common cathode may be prepared by a dual damascene process, and then an upper optical cavity is further prepared. Specifically, step S24 and step S25 may be replaced by the following steps:

[0120] (1) The blank space in the display device layer is filled with an insulating dielectric to form a second insulating layer.

[0121] The second insulating layer may be formed by CVD, PVD, ALD, spin coating, etc.

[0122] (2) Performing pit etching on the surface of the second insulating layer to obtain at least one connected or disconnected pit, wherein at least one pit is in contact with the N-type ohmic contact layer at the top of the pixel unit.

[0123] (3) Metal filling is performed in the pits to form a common cathode.

[0124] Specifically, the second insulating layer is pit-etched, and then a metal seed layer is sputtered to realize N-type ohmic contact and common cathode connection with the pixel unit, and then metal filling is realized by electroplating and chemical mechanical polishing (CMP) process. On the N-type contact with the pixel unit, single-side, double-side, or multi-side contact can be made with the N-type ohmic contact layer, and the common cathode can be at the top of the pixel unit as shown in FIG. Fig.16 The following table shows the connection. Fig.17 The metal seed layer can be Ti / Cu or Al / Ni / Cu.

[0125] (4) Electroplating metal on the common cathode to form an upper optical cavity.

[0126] Specifically, Fig.18 As shown, a metal dam with a high aspect ratio is formed on the common cathode 70 by electroplating as the upper optical cavity 30 .

[0127] S26: Filling a color conversion layer in the upper optical cavity.

[0128] Specifically, the color conversion layer is filled in the upper optical cavity to obtain Figure 1 , Figure 2 The structure shown.

[0129] In a possible implementation, step S26 specifically includes:

[0130] (1) Filling the upper optical cavity with an insulating medium to form a first insulating layer.

[0131] (2) A multi-ring structure is prepared in the first insulating layer.

[0132] Specifically, the multi-ring structure can be a dielectric multi-ring structure, and the preparation method includes: etching a first insulating layer with a ring-shaped groove to form a dielectric multi-ring structure. Insulating layer coating is performed in the upper optical cavity to form a first insulating layer, and a groove structure of a ring structure is formed in the first insulating layer by semiconductor patterning etching as a dielectric multi-ring structure. When the light source enters the first insulating layer and is totally reflected in the air where the first insulating layer and the dielectric multi-ring structure are located, the light source is reflected and refracted multiple times inside the first insulating layer to form oscillation enhancement.

[0133] Specifically, the multi-ring structure can be a metal multi-ring structure, and the preparation method includes: etching a ring-shaped groove on the first insulating layer, and filling the groove with metal to form a metal multi-ring structure. After the groove structure in the first insulating layer is formed, metal filling is performed, and when the light source enters the first insulating layer and reflects between the first insulating layer and the metal where the groove is located, the light source is reflected and refracted multiple times inside the first insulating layer to form oscillation enhancement.

[0134] (3) A color conversion layer is filled in the region above the first insulating layer in the upper optical cavity.

[0135] Furthermore, after step S26, the following step may be performed: an insulating medium is coated on the color conversion layer to form a third insulating layer. Insulating medium coating may be performed on the color conversion layer to isolate water vapor.

[0136] In summary, in the preparation method of the full-color micro-display device provided in the embodiment of the present application, the driving wafer and the display module in the full-color micro-display device are bonded and integrated through a bonding metal layer, and the display module includes a display device layer and a color conversion layer. Due to the physical characteristics, a metal fence is inevitably formed in the process of ion beam etching the bonding metal layer. This metal fence is fully utilized to form an optical resonant cavity for the pixel unit in the display device layer, and the color conversion layer is arranged in the upper optical cavity of the display device layer. The light-emitting angle of the pixel unit is doubly constrained by the combined structure of the metal fence and the upper optical cavity, thereby effectively avoiding crosstalk between adjacent pixel units in the full-color micro-display device.

[0137] Furthermore, the metal fence and the upper optical cavity are made of inorganic materials with high reliability, avoiding affecting the integrity of the full-color micro-display device.

[0138] All the above-mentioned optional technical solutions can be combined in any way to form optional embodiments of the present invention, that is, any multiple embodiments can be combined to meet the needs of different application scenarios. They are all within the protection scope of this application and will not be described one by one here.

[0139] It should be noted that the above is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present invention should be included in the protection scope of the present invention.

Claims

1. A full-color micro-display device with crosstalk prevention, characterized in that: The full-color micro display device comprises: a driving wafer, and a display module integrated with the driving wafer through a bonding metal layer, wherein the display module comprises at least: a display device layer and a color conversion layer stacked in a vertical direction; The display device layer includes: a pixel unit and a metal fence surrounding the pixel unit, wherein the metal fence is a fence pattern structure generated in the process of ion beam etching the bonding metal layer; An upper optical cavity is prepared on the surface of the display device layer away from the driving wafer, the projection of the pixel unit on the driving wafer is located within the projection of the upper optical cavity on the driving wafer, and the upper optical cavity is filled with the color conversion layer; Wherein, the metal fence and the upper optical cavity are used to constrain the light-emitting angle of the pixel unit.

2. The full-color micro-display device according to claim 1, characterized in that: The projection of the metal fence on the driving wafer is located within the projection of the upper optical cavity on the driving wafer.

3. The full-color micro-display device according to claim 2, characterized in that: One end of the metal fence is connected to a surface of the driving wafer close to the display device layer, and the other end is separated from the upper optical cavity by a preset distance.

4. The full-color micro-display device according to claim 1, characterized in that: A ratio between a height of the upper optical cavity and a width of the upper optical cavity is between 2:1 and 10:

1.

5. The full-color micro-display device according to claim 1, characterized in that: A first insulating layer is further provided between the color conversion layer and the display device layer, and a multi-ring structure is provided in the first insulating layer.

6. The full-color micro-display device according to claim 1, characterized in that: The pixel unit at least includes: the bonding metal layer, the P-type ohmic contact layer, the compound semiconductor layer and the N-type ohmic contact layer which are vertically stacked in sequence in a direction away from the driving wafer; The sidewall of the metal fence contacts the sidewalls of the bonding metal layer and the P-type ohmic contact layer, and is spaced apart from the sidewalls of the compound semiconductor layer and the N-type ohmic contact layer.

7. The full-color micro-display device according to any one of claims 1 to 6, characterized in that: The display device layer also includes: a second insulating layer, the second insulating layer filling the blank space of the display device layer; A common cathode, the common cathode is covered on the second insulating layer and connected to the N-type ohmic contact layer on the top of the pixel unit; Wherein, the upper optical cavity is prepared on the common cathode.

8. The full-color micro-display device according to claim 7, characterized in that: The common cathode and the upper optical cavity are made of metal materials, and the common cathode is continuous or discontinuous.

9. The full-color micro-display device according to claim 1, characterized in that: A third insulating layer is disposed on the color conversion layer.

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