Display panel

Abstract

A display panel includes: a display panel test circuit including an open-short test transistor including a gate electrode receiving a test gate signal, a first electrode receiving an open-short test voltage, and a second electrode connected to a data line transmitting a data voltage; and an electrostatic discharge protection circuit including: a first electrostatic discharge diode including a cathode electrode connected to the data line and an anode electrode receiving a first voltage; a first switching element that determines a minimum voltage of the display panel as a first voltage under a first condition, and determines an electrostatic discharge low potential voltage higher than the minimum voltage of the display panel as the first voltage under a second condition; and a second electrostatic discharge diode including a cathode electrode receiving the second voltage and an anode electrode connected to the data line.

Description

Technical Field

[0001] The embodiments of the present invention relate to a display panel. More specifically, the embodiments of the present invention relate to a display panel including an electrostatic discharge protection circuit. Background Art

[0002] Typically, a display device may include a display panel. The display panel may include data lines and pixels. A display panel test circuit may be disposed around the display panel for use in an illumination test, an open circuit-short circuit test, or a module crack test of the display panel. In the display device, an electrostatic discharge protection circuit may be disposed around the display panel to protect the display panel from an electrostatic discharge current introduced from the outside. The electrostatic discharge protection circuit may be disposed adjacent to the display panel test circuit. The electrostatic discharge protection circuit may receive a minimum voltage and a maximum voltage. The minimum voltage may be a first gate drive voltage corresponding to a low voltage level of a gate signal. The maximum voltage may be a second gate drive voltage corresponding to a high voltage level of a gate signal. The data voltage and the maximum voltage may be higher than the minimum voltage.

[0003] In such a display device, the data line can output the data voltage to the open-short test transistor through the first connection line that transmits the data voltage. The electrostatic discharge protection circuit can receive the minimum voltage through the second connection line. The electrostatic discharge protection circuit can receive the maximum voltage through the third connection line. Utility Model Content

[0004] In such a device, when the voltage difference between the data voltage applied to the data line through the first connection line and the minimum voltage applied to the electrostatic discharge protection circuit through the second connection line is large, ions can easily move to the first connection line. Accordingly, an oxidation-reduction reaction can easily occur in the first connection line, and corrosion can easily occur in the first connection line. When the voltage difference between the minimum voltage and the maximum voltage applied to the electrostatic discharge protection circuit is large, corrosion can occur in the third connection line through which the maximum voltage is applied to the electrostatic discharge protection circuit.

[0005] An embodiment of the utility model provides a display panel for preventing corrosion of wires.

[0006] In an embodiment of a display panel according to the utility model, the display panel includes: a display panel test circuit, including an open-short test transistor, the open-short test transistor including a gate electrode receiving a test gate signal, a first electrode receiving an open-short test voltage and a second electrode connected to a data line transmitting a data voltage; and an electrostatic discharge protection circuit, including: a first electrostatic discharge diode, including a cathode electrode connected to the data line and an anode electrode receiving a first voltage; a first switching element, which determines the minimum voltage of the display panel as a first voltage under a first condition, and determines an electrostatic discharge low potential voltage higher than the minimum voltage of the display panel as the first voltage under a second condition; and a second electrostatic discharge diode, including a cathode electrode receiving a second voltage and an anode electrode connected to the data line.

[0007] In an embodiment, when the driving integrated circuit is electrically connected to the display panel, the first condition may be satisfied, and when the driving integrated circuit is not electrically connected to the display panel, the second condition may be satisfied.

[0008] In an embodiment, the electrostatic discharge low potential voltage may be determined based on a minimum gamma reference voltage output from a driving integrated circuit or a flexible circuit board.

[0009] In an embodiment, the display panel may further include: a touch screen panel, and the electrostatic discharge low potential voltage may be a touch ground voltage of a touch ground line electrically connected to the touch screen panel.

[0010] In an embodiment, the electrostatic discharge low potential voltage may be a ground voltage of a driving integrated circuit or a flexible circuit board.

[0011] In an embodiment, a voltage difference between the ESD low potential voltage and the data voltage may be greater than or equal to the offset voltage.

[0012] In an embodiment, the first switching element may include a first ESD transistor transmitting the ESD low potential voltage to the first ESD diode based on the first ESD gate signal.

[0013] In an embodiment, the first switching element may further include a second ESD transistor transmitting a minimum voltage of the display panel to the first ESD diode based on the second ESD gate signal.

[0014] In an embodiment, when the display panel is in a display panel test environment, the first condition may be satisfied, and when the display panel is in a user use environment, the second condition may be satisfied.

[0015] In an embodiment, the minimum voltage of the display panel may be a first gate driving voltage corresponding to a low voltage level of the gate signal.

[0016] According to an embodiment of the display panel, the open-short test circuit and the first electrostatic discharge diode of the electrostatic discharge protection circuit can be arranged adjacent to or close to each other. In such an embodiment, the first switching element can be electrically connected to the first electrostatic discharge diode. In such an embodiment, the first switching element can receive an electrostatic discharge low potential voltage higher than the minimum voltage according to the condition. Accordingly, the voltage difference between the data voltage received by the open-short test circuit and the first voltage received by the first electrostatic discharge diode of the electrostatic discharge protection circuit can be selectively reduced, so that the corrosion of the first connection line electrically connected to the open-short test circuit can be effectively prevented. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] The above and other features of the embodiments of the present invention will become more apparent by describing the embodiments of the present invention in detail with reference to the accompanying drawings, in which:

[0018] Figure 1 is a plan view for illustrating a display device according to an embodiment of the utility model;

[0019] Figure 2 Is used for illustration Figure 1 A conceptual diagram of the structure of a display panel;

[0020] Figure 3 Is used for illustration Figure 1 A circuit diagram of a display panel test circuit;

[0021] Figure 4 Is used for illustration Figure 1 Circuit diagram of electrostatic discharge protection circuit;

[0022] Figure 5 Is used for illustration Figure 1 Display panel test circuit and Figure 1 Circuit diagram of electrostatic discharge protection circuit;

[0023] Figure 6 Is used for illustration Figure 5 The voltage difference between the first connection line and the second connection line in Figure 5 A circuit diagram showing a voltage difference between a second connection line and a third connection line in FIG.

[0024] Figure 7 is a circuit diagram for illustrating an electrostatic discharge protection circuit according to an embodiment of the utility model;

[0025] Figure 8 Is used for illustration Figure 7 Circuit diagram of an example of an electrostatic discharge low potential voltage;

[0026] Fig. 9 Is used for illustration Figure 7Circuit diagram of an example of an electrostatic discharge low potential voltage;

[0027] Fig.10 is a cross-sectional view for illustrating first to fourth connection lines;

[0028] Fig.11 Is used for illustration Figure 7 Circuit diagram of an example of an electrostatic discharge low potential voltage;

[0029] Fig.12 is a conceptual diagram used to illustrate offset voltage;

[0030] Fig.13 Is used for illustration Figure 7 a circuit diagram of an example of a first switching element;

[0031] Fig.14 Is used for illustration Figure 7 a circuit diagram of an example of a first switching element;

[0032] Fig.15 Is used for illustration Figure 7 a circuit diagram of an example of a first switching element;

[0033] Fig.16 is a circuit diagram for illustrating an electrostatic discharge protection circuit according to an embodiment of the utility model;

[0034] Fig.17 Is used for illustration Figure 7 Circuit diagram of electrostatic discharge protection circuit;

[0035] Fig.18 is a block diagram for illustrating an electronic device according to an embodiment of the present utility model; and

[0036] Fig.19 It is used to illustrate Fig.18 FIG. 1 is a diagram of an embodiment in which the electronic device is implemented as a smart phone. DETAILED DESCRIPTION

[0037] The present invention will now be described more fully below with reference to the accompanying drawings in which various embodiments are shown. However, the present invention can be implemented in many different forms and should not be construed as being limited to the embodiments set forth herein. On the contrary, these embodiments are provided so that the present disclosure will be thorough and complete, and these embodiments will fully convey the scope of the present invention to those skilled in the art. The same reference numerals refer to the same elements throughout.

[0038] It will be understood that when an element is referred to as being "on" another element, it can be directly on the other element or intervening elements may be present therebetween. In contrast, when an element is referred to as being "directly on" another element, there are no intervening elements present.

[0039] It will be understood that although the terms "first", "second", "third", etc. may be used herein to describe various elements, components, regions, layers and / or sections, these elements, components, regions, layers and / or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Therefore, without departing from the teachings of this article, the first element, component, region, layer or section discussed below may be referred to as a second element, component, region, layer or section.

[0040] The terms used in this article are only used to describe the purpose of specific embodiments, and are not intended to limit. As used in this article, "one", "the (described)" and "at least one" do not represent the limitation of quantity, and are intended to include both singular and plural, unless the context clearly indicates otherwise. Therefore, the reference to "one" element in the claim includes one element and multiple elements. For example, unless the context clearly indicates otherwise, "one element" has the same meaning as "at least one element". "At least one" should not be interpreted as limiting "one". "Or" means "and / or". As used in this article, the term "and / or" includes any and all combinations of one or more of the associated listed items. It will be further understood that when used in this specification, the term "includes" or "comprising" and its variants specify the existence of stated features, regions, wholes, steps, operations, elements and / or parts, but does not exclude the existence or addition of one or more other features, regions, wholes, steps, operations, elements, parts and / or its groups.

[0041] In addition, relative terms such as "lower" or "bottom" and "upper" or "top" may be used herein to describe the relationship of one element to another element as illustrated in the various figures. It will be understood that, in addition to the orientation depicted in the various figures, relative terms are intended to cover different orientations of the device. For example, if the device in one of the various figures is turned over, the element described as being on the "lower" side of the other elements will then be oriented on the "upper" side of the other elements. Therefore, depending on the specific orientation of the figure, the term "lower" can cover both the "lower" and "upper" orientations. Similarly, if the device in one of the various figures is turned over, the element described as being "below" or "below" the other elements will then be oriented "above" the other elements. Therefore, the term "below" or "below" can cover both the above and below orientations.

[0042] Unless otherwise defined, all terms (including technical and scientific terms) used in this article have the same meaning as those commonly understood by ordinary technicians in the field to which the present disclosure belongs. It will be further understood that terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant field and the present disclosure, and will not be interpreted in an idealized or overly formal sense unless explicitly defined as such in this article.

[0043] Embodiments are described herein with reference to schematic cross-sectional illustrations that are idealized embodiments. Therefore, variations in the shapes of the illustrations as a result of, for example, manufacturing techniques and / or tolerances are contemplated. Therefore, the embodiments described herein should not be interpreted as being limited to the specific shapes of the regions as illustrated herein, but rather to include deviations in shapes, for example, caused by manufacturing. For example, a region illustrated or described as flat may typically have rough and / or nonlinear features. In addition, illustrated sharp corners may be rounded. Therefore, the regions illustrated in the figures are schematic in nature, and their shapes are not intended to illustrate the precise shapes of the regions and are not intended to limit the scope of the claims.

[0044] Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

[0045] Figure 1 1 is a plan view for illustrating a display device 10 according to an embodiment of the present invention. Figure 2 Is used for illustration Figure 1 A conceptual diagram of the structure of the display panel.

[0046] refer to Figure 1 and Figure 2 , an embodiment of the display device 10 may include a display panel, a driving integrated circuit IC, a display panel test circuit IP1 and a flexible circuit board FPC.

[0047] The display panel may include a display area DA for displaying an image and a peripheral area NDA disposed around the display area DA. In an embodiment, for example, in a plan view or when viewed in a thickness direction of the display panel, the peripheral area NDA may surround at least a portion of the display area DA. A driving integrated circuit IC for driving the pixels P may be disposed in the peripheral area NDA.

[0048] The peripheral area NDA may include a pad area PA. In an embodiment, for example, the pad area PA may be adjacent to a lower portion of the display area DA.

[0049] In an embodiment, for example, the display panel may be an organic light emitting diode display panel including an organic light emitting diode. In an alternative embodiment, for example, the display panel may be a quantum dot organic light emitting diode display panel including an organic light emitting diode and a quantum dot color filter. In an alternative embodiment, for example, the display panel may be a quantum dot nano light emitting diode display panel including a nano light emitting diode and a quantum dot color filter. In an alternative embodiment, for example, the display panel may be a liquid crystal display panel including a liquid crystal layer.

[0050] In an embodiment, Figure 2 As shown in , the display panel may include gate lines GL, data lines DL1 , DL2 , DL3 , and DL4 , and pixels P electrically connected to the gate lines GL and the data lines DL1 , DL2 , DL3 , and DL4 .

[0051] In an embodiment, the driving integrated circuit IC may provide a gate signal, a gamma reference voltage, a data voltage, a power voltage, etc. to the pixel P through the flexible circuit board FPC.

[0052] In an embodiment, the display panel test circuit IP1 may overlap with the driver integrated circuit IC. In an embodiment, for example, the display panel test circuit IP1 may be integrated in the pad area PA of the display panel. The driver integrated circuit IC may be mounted in the form of a chip at a location where the display panel test circuit IP1 is provided.

[0053] The display panel test circuit IP1 may test whether the pixels P of the display panel display images normally. In an embodiment, for example, before the driver integrated circuit IC is mounted on the display panel, the display panel test circuit IP1 may determine whether the pixels P of the display panel display images normally.

[0054] After the display panel test is completed, the display panel test circuit IP1 may be disconnected from the data lines DL1, DL2, DL3, and DL4. In an embodiment, for example, a switch may be formed between the display panel test circuit IP1 and the data lines DL1, DL2, DL3, and DL4. The switch may determine the connection relationship between the display panel test circuit IP1 and the data lines DL1, DL2, DL3, and DL4.

[0055] In the open-short test of the data lines DL1, DL2, DL3 and DL4, a vertical stripe pattern (a voltage corresponding to the vertical stripe pattern image) may be applied to the display panel to check whether an open circuit or a short circuit occurs between the data lines DL1, DL2, DL3 and DL4. In an embodiment, for example, when a high brightness image is applied to the first data line DL1 and a low brightness image is applied to the second data line DL2 adjacent to the first data line DL1, the pixel P connected to the first data line DL1 may exhibit high brightness, and the pixel P connected to the second data line DL2 may exhibit low brightness. However, when an open circuit occurs in the first data line DL1 or the second data line DL2, the open data line may not display the desired grayscale. In addition, when a short circuit occurs between the first data line DL1 and the second data line DL2, the pixels P connected to the first data line DL1 and the second data line DL2 may partially or entirely exhibit the same grayscale as each other.

[0056] In the following, reference will be made to Figure 3 The configuration and operation of the display panel test circuit IP1 are described in detail.

[0057] Figure 3 Is used for illustration Figure 1 2 is a circuit diagram of a display panel test circuit IP1.

[0058] refer to Figures 1 to 3 , an embodiment of the display panel test circuit IP1 may include an open-short test circuit T1.

[0059] The open-short test circuit T1 may include an open-short test transistor including a gate electrode receiving a test gate signal TGOS, a first electrode receiving an open-short test voltage TEST_VDATA, and a second electrode connected to a data line DL transmitting a data voltage VDATA.

[0060] Figure 4 Is used for illustration Figure 1 A circuit diagram of an electrostatic discharge protection circuit 400 is shown. Figure 5 Is used for illustration Figure 1 The display panel test circuit IP1 and Figure 1 A circuit diagram of an electrostatic discharge protection circuit 400 is shown. Figure 6 Is used for illustration Figure 5 The voltage difference between the first connection line CL1 and the second connection line CL2 in Figure 5 Circuit diagram of the voltage difference between the second connection line CL2 and the third connection line CL3 in FIG.

[0061] refer to Figures 1 to 6, an embodiment of the electrostatic discharge protection circuit 400 may be disposed adjacent to or close to the display panel test circuit IP1 including the open-short test circuit T1. In an embodiment, static electricity may be introduced through the data line DL. The static electricity introduced through the data line DL may damage the pixel P directly connected to the data line DL. The electrostatic discharge protection circuit 400 may effectively prevent the pixel P from being damaged by static electricity by discharging the static electricity. In an embodiment, one or more electrostatic discharge protection circuits 400 may be connected to the data line DL to discharge the static electricity introduced through the data line DL.

[0062] In an embodiment, the electrostatic discharge protection circuit 400 may include a first electrostatic discharge diode FDD and a second electrostatic discharge diode SDD. The electrostatic discharge protection circuit 400 may receive a minimum voltage VGL and a maximum voltage VGH. The data voltage VDATA and the maximum voltage VGH may be higher than the minimum voltage VGL. The minimum voltage VGL may be a first gate drive voltage corresponding to a low voltage level of a gate signal. The maximum voltage VGH may be a second gate drive voltage corresponding to a high voltage level of a gate signal.

[0063] When the static electricity is less than the minimum voltage VGL, the static electricity can be discharged through the first static electricity discharge diode FDD, and when the static electricity is greater than the maximum voltage VGH, the static electricity can be discharged through the second static electricity discharge diode SDD.

[0064] In an embodiment, Figure 6 As shown in , when the voltage difference between the minimum voltage VGL and the data voltage VDATA is large, ions may easily move to the first connection line CL1 for transmitting the data voltage VDATA having a voltage higher than the minimum voltage VGL. Accordingly, an oxidation-reduction reaction may easily occur in the first connection line CL1, and corrosion may easily occur in the first connection line CL1. When the voltage difference between the minimum voltage VGL and the maximum voltage VGH is large, corrosion may occur in the third connection line CL3 for transmitting the maximum voltage VGH higher than the minimum voltage VGL.

[0065] In an embodiment, the voltage difference between the minimum voltage VGL and the data voltage VDATA can be reduced by adjusting the minimum voltage VGL to prevent such corrosion. In an embodiment, the voltage difference between the minimum voltage VGL and the maximum voltage VGH can be reduced by adjusting the minimum voltage VGL to prevent such corrosion. In an embodiment, the voltage difference between the minimum voltage VGL and the maximum voltage VGH can be reduced by adjusting the maximum voltage VGH to prevent such corrosion. In an embodiment, the distance between the lines to which the voltage is applied can be adjusted to prevent such corrosion.

[0066] Figure 7is a circuit diagram for illustrating an electrostatic discharge protection circuit 400 according to an embodiment of the present invention.

[0067] refer to Figures 1 to 7 , an embodiment of the electrostatic discharge protection circuit 400 may include a first electrostatic discharge diode FDD, a second electrostatic discharge diode SDD, and a first switching element FSE.

[0068] In such an embodiment, the first ESD diode FDD may include a cathode electrode connected to the data line DL and an anode electrode receiving the first voltage V1. The second ESD diode SDD may include a cathode electrode receiving the second voltage V2 and an anode electrode connected to the data line DL.

[0069] The first switching element FSE may determine the minimum voltage VGL of the display panel as the first voltage V1 which is the output voltage of the first switching element FSE under the first condition, and determine the electrostatic discharge low potential voltage ESD_LOW higher than the minimum voltage VGL of the display panel as the first voltage V1 under the second condition.

[0070] In such an embodiment, the display panel test circuit IP1 including the open-short test circuit T1 may be effectively prevented from being corroded by reducing the voltage difference between the data voltage VDATA and the first voltage V1.

[0071] Figure 8 Is used for illustration Figure 7 A circuit diagram of an example of an electrostatic discharge low potential voltage ESD_LOW.

[0072] refer to Figures 1 to 8 In an embodiment, the electrostatic discharge low potential voltage ESD_LOW may be determined based on the minimum gamma reference voltage VGREF_MIN output from the driver integrated circuit IC or the flexible circuit board FPC. The minimum gamma reference voltage VGREF_MIN may be the minimum value of the gamma reference voltage. In an embodiment, for example, the minimum voltage VGL may be -8 volts (V), the maximum voltage VGH may be 8V, and the data voltage VDATA may be in the range of 2V to 6V. The electrostatic discharge low potential voltage ESD_LOW may be determined based on the minimum gamma reference voltage VGREF_MIN that is higher than the minimum voltage VGL and lower than the maximum voltage VGH and the data voltage VDATA. In an embodiment, for example, the minimum gamma reference voltage VGREF_MIN may be 0.5V, and the electrostatic discharge low potential voltage ESD_LOW may be the minimum gamma reference voltage VGREF_MIN. In an embodiment, for example, the minimum gamma reference voltage VGREF_MIN may be 0.5V, and the electrostatic discharge low potential voltage ESD_LOW may be 0.5V lower than the minimum gamma reference voltage VGREF_MIN.

[0073] In such an embodiment, the display panel test circuit IP1 including the open-short test circuit T1 may be effectively prevented from being corroded by reducing the voltage difference between the data voltage VDATA and the first voltage V1.

[0074] Fig. 9 Is used for illustration Figure 7 A circuit diagram of an example of an electrostatic discharge low potential voltage ESD_LOW. Fig.10 is a cross-sectional view for illustrating first to fourth connection lines CL1 , CL2 , CL3 , and CL4 .

[0075] refer to Figures 1 to 10 In an embodiment, the display panel may further include a touch screen panel TSP, and the electrostatic discharge low potential voltage ESD_LOW may be a touch ground voltage VGND_TSP of a touch ground line (or fourth connection line) CL4 electrically connected to the touch screen panel TSP. In an embodiment, for example, the minimum voltage VGL may be -8V, the maximum voltage VGH may be 8V, and the data voltage VDATA may be in the range of 2V to 6V. In an embodiment, for example, the touch ground voltage VGND_TSP may be 0V, and the electrostatic discharge low potential voltage ESD_LOW may be the touch ground voltage VGND_TSP.

[0076] In an embodiment, Fig.10As shown in, in the first connection line CL1 to the fourth connection line CL4, the source-drain electrode SD1, the first through-hole insulating layer VIA1, the connection electrode SD2, the second through-hole insulating layer VIA2, the pixel defining layer PDL, the first touch electrode YMTL1, the first touch insulating layer YCNT and YILD, the second touch electrode YMTL2 and the second touch insulating layer YPVX can be sequentially formed. The first connection line CL1 can be connected to the open-short test circuit T1. The first connection line CL1 can be arranged in the first region R1 and can be arranged in the same layer as the source-drain electrode SD1. The second connection line CL2 can be connected to the anode electrode of the first electrostatic discharge diode FDD. The second connection line CL2 can be arranged in the second region R2 and can be arranged in the same layer as the source-drain electrode SD1. The third connection line CL3 can be connected to the cathode electrode of the second electrostatic discharge diode SDD. The third connection line CL3 can be arranged in the third region R3 and can be arranged in the same layer as the source-drain electrode SD1. The fourth connection line CL4 can be connected to the touch screen panel TSP. The fourth connection line CL4 may be disposed in the fourth region R4 and may be disposed in the same layer as the second touch electrode YMTL2. In an embodiment, the fourth connection line (or touch ground line) CL4 may be connected to the source-drain electrode SD1 through a contact hole in the fourth region R4. In an embodiment, the second connection line CL2 and the fourth connection line CL4 may be a touch ground line CL4 connected to the source-drain electrode SD1 through a contact hole in the second region R2. Since the first touch insulating layer YCNT and YILD may be disposed between the source-drain electrode SD1 and the second touch electrode YMTL2, ions may be effectively prevented from moving between the source-drain electrode SD1 and the second touch electrode YMTL2.

[0077] In such an embodiment, as described above, the display panel test circuit IP1 including the open-short test circuit T1 may be effectively prevented from being corroded by reducing the voltage difference between the data voltage VDATA and the first voltage V1.

[0078] Fig.11 Is used for illustration Figure 7 A circuit diagram of an example of an electrostatic discharge low potential voltage ESD_LOW.

[0079] refer to Figures 1 to 11 In an embodiment, the electrostatic discharge low potential voltage ESD_LOW may be a ground voltage VGND of a driving integrated circuit IC or a flexible circuit board FPC. In an embodiment, for example, the minimum voltage VGL may be -8V, the maximum voltage VGH may be 8V, and the data voltage VDATA may be in a range of 2V to 6V. In an embodiment, for example, the ground voltage VGND may be 0V, and the electrostatic discharge low potential voltage ESD_LOW may be the ground voltage VGND.

[0080] In such an embodiment, the display panel test circuit IP1 including the open-short test circuit T1 may be effectively prevented from being corroded by reducing the voltage difference between the data voltage VDATA and the first voltage V1.

[0081] Fig.12 2 is a conceptual diagram for illustrating an offset voltage VOFFSET.

[0082] refer to Figures 1 to 12 In an embodiment, when the data voltage VDATA is equal to the electrostatic discharge low potential voltage ESD_LOW, the first electrostatic discharge diode FDD may be turned on. Therefore, when the first electrostatic discharge diode FDD is turned on, the pixel P may not emit light as large as the grayscale corresponding to the data voltage VDATA. Accordingly, in such an embodiment, the voltage difference between the electrostatic discharge low potential voltage ESD_LOW and the data voltage VDATA may be greater than or equal to the offset voltage VOFFSET to emit light as large as the grayscale corresponding to the data voltage VDATA. The offset voltage VOFFSET may be the minimum voltage difference between the data voltage VDATA and the electrostatic discharge low potential voltage ESD_LOW to prevent the first electrostatic discharge diode FDD from being turned on.

[0083] Fig.13 Is used for illustration Figure 7 FIG. 1 is a circuit diagram of an example of a first switching element FSE. Fig.14 Is used for illustration Figure 7 FIG. 1 is a circuit diagram of an example of a first switching element FSE.

[0084] refer to Figures 1 to 14 In an embodiment, the first switching element FSE may determine the minimum voltage VGL of the display panel as the first voltage V1 under a first condition, and determine the electrostatic discharge low potential voltage ESD_LOW higher than the minimum voltage VGL of the display panel as the first voltage V1 under a second condition.

[0085] In an embodiment, when the driver integrated circuit IC is electrically connected to the display panel, the first condition is satisfied, and when the driver integrated circuit IC is not electrically connected to the display panel, the second condition is satisfied. Fig.13As shown in , the first switch element FSE may include a first electrostatic discharge transistor TD1 that transmits an electrostatic discharge low potential voltage ESD_LOW to a first electrostatic discharge diode FDD based on (or in response to) a first electrostatic discharge gate signal GD1. In this case, the first electrostatic discharge gate signal GD1 may be output by a driver integrated circuit IC or a flexible circuit board FPC. Under the first condition, the first electrostatic discharge transistor TD1 may be turned off by the first electrostatic discharge gate signal GD1, and the minimum voltage VGL may be transmitted to the first electrostatic discharge diode FDD. Therefore, by ensuring the voltage difference between the data voltage VDATA and the first voltage V1, the performance of the first electrostatic discharge diode FDD in discharging static electricity may be ensured. Under the second condition, the first electrostatic discharge transistor TD1 may be turned on by the first electrostatic discharge gate signal GD1, and the first switch element FSE may be turned on based on the first electrostatic discharge gate signal GD1. Therefore, the electrostatic discharge low potential voltage ESD_LOW may be transmitted to the first electrostatic discharge diode FDD. Therefore, the display panel test circuit IP1 including the open-short test circuit T1 may be effectively prevented from being corroded by reducing the voltage difference between the data voltage VDATA and the first voltage V1.

[0086] In an alternative embodiment, if Fig.14 As shown in , the first switching element FSE may include an ESD transistor TD1 that transmits the minimum voltage VGL to the first ESD diode FDD based on the first ESD gate signal GD1. In such an embodiment, except that the first switching element FSE controls the transmission of the minimum voltage VGL, the first switching element FSE may be substantially similar to Fig.13 The first switching element FSE.

[0087] Fig.15 Is used for illustration Figure 7 FIG. 1 is a circuit diagram of an example of a first switching element FSE.

[0088] refer to Figures 1 to 15 The first switching element FSE may determine the minimum voltage VGL of the display panel as the first voltage V1 under the first condition, and determine the electrostatic discharge low potential voltage ESD_LOW higher than the minimum voltage VGL of the display panel as the first voltage V1 under the second condition.

[0089] In an embodiment, when the display panel is in a display panel test environment, the first condition may be satisfied, and when the display panel is in a user use environment, the second condition may be satisfied. Fig.15As shown in , the first switch element FSE may further include a second electrostatic discharge transistor TD2 that transmits the minimum voltage VGL to the first electrostatic discharge diode FDD based on the second electrostatic discharge gate signal GD2. In this case, the first electrostatic discharge gate signal GD1 and the second electrostatic discharge gate signal GD2 may be output by the driver integrated circuit IC or the flexible circuit board FPC. Under the first condition, the first electrostatic discharge transistor TD1 may be turned off by the first electrostatic discharge gate signal GD1 and the second electrostatic discharge transistor TD2 may be turned on by the second electrostatic discharge gate signal GD2, and the first switch element FSE may transmit the minimum voltage VGL to the first electrostatic discharge diode FDD. Therefore, the performance of the first electrostatic discharge diode FDD to discharge static electricity can be ensured by ensuring the voltage difference between the data voltage VDATA and the first voltage V1. Under the second condition, the first electrostatic discharge transistor TD1 may be turned on by the first electrostatic discharge gate signal GD1 and the second electrostatic discharge transistor TD2 may be turned off by the second electrostatic discharge gate signal GD2, and the first switch element FSE may transmit the electrostatic discharge low potential voltage ESD_LOW to the first electrostatic discharge diode FDD. Therefore, the display panel test circuit IP1 including the open-short test circuit T1 may be effectively prevented from being corroded by reducing the voltage difference between the data voltage VDATA and the first voltage V1.

[0090] Fig.16 is a circuit diagram for illustrating an electrostatic discharge protection circuit 400 according to an embodiment of the present invention.

[0091] refer to Figures 1 to 16 In an embodiment, the electrostatic discharge protection circuit 400 may further include a second switching element SSE, which determines the maximum voltage VGH of the display panel as the second voltage V2 under the first condition, and determines the electrostatic discharge high potential voltage ESD_HIGH lower than the maximum voltage VGH of the display panel as the second voltage V2 under the second condition. In an embodiment, for example, the minimum voltage VGL may be -8 V, and the maximum voltage VGH may be 8 V. The electrostatic discharge high potential voltage ESD_HIGH may be determined as a voltage lower than the maximum voltage VGH.

[0092] In such an embodiment, the display panel test circuit IP1 including the open-short test circuit T1 may be effectively prevented from being corroded by reducing the voltage difference between the data voltage VDATA and the second voltage V2.

[0093] Fig.17 Is used for illustration Figure 7 Circuit diagram of the electrostatic discharge protection circuit.

[0094] refer to Figures 1 to 17In an embodiment, the distance between the first connection line CL1 and the second connection line CL2 may be greater than or equal to the offset distance DOFFSET. The distance between the second connection line CL2 and the third connection line CL3 may be greater than or equal to the offset distance DOFFSET. The offset distance DOFFSET may be the minimum distance between lines for preventing corrosion.

[0095] Although there is a voltage difference between the data voltage VDATA and the first voltage V1, corrosion may occur less when the distance between the lines increases. Therefore, although there is a voltage difference between the data voltage VDATA and the first voltage V1, the display panel test circuit IP1 including the open-short test circuit T1 may be effectively prevented from being corroded by ensuring the distance between the lines.

[0096] Fig.18 is a block diagram for illustrating an electronic device 1000 according to an embodiment of the present invention. Fig.19 It is used to illustrate Fig.18 FIG. 1 is a diagram of an embodiment in which the electronic device is implemented as a smart phone.

[0097] refer to Fig.18 and Fig.19 , an embodiment of the electronic device 1000 may include a processor 1010, a memory device 1020, a storage device 1030, an input / output (I / O) device 1040, a power supply 1050, and a display device 1060. The display device 1060 may be Figure 1 The display device 10. In addition, the electronic device 1000 may further include a plurality of ports for communicating with a video card, a sound card, a memory card, a universal serial bus (USB) device, and other electronic devices.

[0098] In an embodiment, Fig.19 As shown in , the electronic device 1000 may be implemented as a smart phone. However, the electronic device 1000 is not limited thereto. In alternative embodiments, for example, the electronic device 1000 may be implemented as a cellular phone, a video phone, a smart tablet, a smart watch, a tablet personal computer (PC), a car navigation system, a computer monitor, a laptop computer, or a head mounted display (HMD) device, etc.

[0099] The processor 1010 may perform various computing functions. The processor 1010 may be a microprocessor, a central processing unit (CPU), an application processor (AP), etc. The processor 1010 may be connected to other components via an address bus, a control bus, or a data bus, etc. Further, the processor 1010 may be connected to an expansion bus such as a peripheral component interconnect (PCI) bus.

[0100] The memory device 1020 may store data for operation of the electronic device 1000. In an embodiment, for example, the memory device 1020 may include at least one nonvolatile memory device such as an erasable programmable read-only memory (EPROM) device, an electrically erasable programmable read-only memory (EEPROM) device, a flash memory device, a phase change random access memory (PRAM) device, a resistive random access memory (RRAM) device, a nano floating gate memory (NFGM) device, a polymer random access memory (PoRAM) device, a magnetic random access memory (MRAM) device, and a ferroelectric random access memory (FRAM) device, and / or at least one volatile memory device such as a dynamic random access memory (DRAM) device, a static random access memory (SRAM) device, or a mobile DRAM device.

[0101] The storage device 1030 may include a solid state drive (SSD) device, a hard disk drive (HDD) device, a CD-ROM device, or the like.

[0102] I / O devices 1040 may include input devices such as a keyboard, a keypad, a mouse device, a touch pad, and a touch screen, and output devices such as a printer or a speaker, etc. In some embodiments, I / O devices 1040 may include a display device 1060 .

[0103] The power supply 1050 may provide power for the operation of the electronic device 1000 .

[0104] The display device 1060 may be connected to other components via a bus or other communication links.

[0105] The present invention can be applied to any display device and any electronic device including a touch screen panel. In an embodiment, for example, the present invention can be applied to mobile phones, smart phones, tablet computers, digital televisions (TVs), three-dimensional (3D) TVs, PCs, home appliances, laptop computers, personal digital assistants (PDAs), portable multimedia players (PMPs), digital cameras, music players, portable game consoles, navigation devices, etc.

[0106] The present invention should not be interpreted as being limited to the embodiments set forth herein. Instead, these embodiments are provided so that the present disclosure will be thorough and complete, and these embodiments will fully convey the concept of the present invention to those skilled in the art.

[0107] While the invention has been particularly shown and described with reference to embodiments thereof, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit or scope of the invention as defined by the claims.

Claims

1. A display panel, characterized in that: The display panel comprises: A display panel test circuit, comprising an open-short test transistor, the open-short test transistor comprising a gate electrode receiving a test gate signal, a first electrode receiving an open-short test voltage, and a second electrode connected to a data line transmitting a data voltage; and Electrostatic discharge protection circuit, including: a first electrostatic discharge diode including a cathode electrode connected to the data line and an anode electrode receiving a first voltage; a first switching element, which determines a minimum voltage of the display panel as the first voltage under a first condition, and determines an electrostatic discharge low potential voltage higher than the minimum voltage of the display panel as the first voltage under a second condition; and The second electrostatic discharge diode includes a cathode electrode receiving a second voltage and an anode electrode connected to the data line.

2. The display panel according to claim 1, wherein: The first condition is satisfied when the driving integrated circuit is electrically connected to the display panel, and the second condition is satisfied when the driving integrated circuit is not electrically connected to the display panel.

3. The display panel according to claim 1, wherein: The electrostatic discharge low potential voltage is determined based on a minimum gamma reference voltage output from a driving integrated circuit or a flexible circuit board.

4. The display panel according to claim 1, wherein: The display panel further includes a touch screen panel, and The electrostatic discharge low potential voltage is a touch ground voltage electrically connected to a touch ground line of the touch screen panel.

5. The display panel according to claim 1, wherein: The electrostatic discharge low potential voltage is a ground voltage of a driving integrated circuit or a flexible circuit board.

6. The display panel according to claim 1, wherein: A voltage difference between the electrostatic discharge low potential voltage and the data voltage is greater than or equal to an offset voltage.

7. The display panel according to claim 1, wherein: The first switching element includes a first ESD transistor transmitting the ESD low potential voltage to the first ESD diode based on a first ESD gate signal.

8. The display panel according to claim 7, wherein: The first switching element further includes a second ESD transistor transmitting the minimum voltage of the display panel to the first ESD diode based on a second ESD gate signal.

9. The display panel according to claim 8, wherein: When the display panel is in a display panel test environment, the first condition is satisfied, and when the display panel is in a user use environment, the second condition is satisfied.

10. The display panel according to any one of claims 1 to 9, wherein: The minimum voltage of the display panel is a first gate driving voltage corresponding to a low voltage level of a gate signal.

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