Solar cell and photovoltaic module

Abstract

The utility model discloses a solar cell and a photovoltaic module, and belongs to the technical field of cells. The solar cell includes: a silicon substrate; the first quantum well passivation structure is located on the light receiving side of the silicon substrate; the first doped microcrystalline silicon layer is positioned on one side, deviating from the silicon substrate, of the first quantum well passivation structure; the first quantum well passivation structure comprises at least two first silicon oxide passivation layers and at least one first intrinsic microcrystalline silicon layer; the at least two first silicon oxide passivation layers are stacked between the silicon substrate and the first doped microcrystalline silicon layer, and the first intrinsic microcrystalline silicon layer is arranged between any adjacent first silicon oxide passivation layers. According to the invention, the problem of performance degradation of the solar cell induced by ultraviolet light can be relieved, and the separation capability of photon-generated carriers in the solar cell is improved.

Description

Technical Field

[0001] The present application belongs to the field of battery technology, and in particular relates to a solar cell and a photovoltaic module. Background Art

[0002] HJT solar cells show considerable power loss after ultraviolet irradiation. This is mainly due to the fact that under ultraviolet light, the silicon-hydrogen bonds in the intrinsic amorphous silicon passivation layer in the HJT solar cell are broken, resulting in excessive H atom clusters, which intensify carrier recombination, deteriorate the surface passivation of the cell, and cause the performance of the cell to decay. Utility Model Content

[0003] The present application aims to solve at least one of the technical problems existing in the prior art. To this end, the present application proposes a solar cell and a photovoltaic module, which can alleviate the performance degradation problem of solar cells induced by ultraviolet light and improve the separation ability of photogenerated carriers in solar cells.

[0004] In a first aspect, the present application provides a solar cell, comprising:

[0005] Silicon substrate;

[0006] A first quantum well passivation structure is located on the light-receiving side of the silicon substrate;

[0007] A first doped microcrystalline silicon layer is located on a side of the first quantum well passivation structure away from the silicon substrate;

[0008] Among them, the first quantum well passivation structure includes at least two first silicon oxide passivation layers and at least one first intrinsic microcrystalline silicon layer; at least two of the first silicon oxide passivation layers are stacked between the silicon substrate and the first doped microcrystalline silicon layer, and the first intrinsic microcrystalline silicon layer is provided between any adjacent first silicon oxide passivation layers.

[0009] According to the solar cell of the present application, a first quantum well passivation structure is arranged on the light-receiving side of the silicon substrate, and the first quantum well passivation structure includes at least two first silicon oxide passivation layers and at least one first intrinsic microcrystalline silicon layer, and a first intrinsic microcrystalline silicon layer is provided between any two adjacent first silicon oxide passivation layers, which has an excellent passivation effect on the crystalline silicon surface, and an intrinsic amorphous silicon passivation layer is no longer provided on the light-receiving side of the silicon substrate, thereby avoiding the problem of deterioration of the passivation effect of the intrinsic amorphous silicon passivation layer under ultraviolet light irradiation, alleviating the performance degradation problem of the solar cell induced by ultraviolet light, and the first quantum well passivation structure realizes the selective transmission of electrons, thereby improving the separation ability of photogenerated carriers in the solar cell.

[0010] According to an embodiment of the present application, the thickness of the first silicon oxide passivation layer is between 0.5 nm and 1.5 nm, and the thickness of the first intrinsic microcrystalline silicon layer is between 3 nm and 10 nm.

[0011] According to one embodiment of the present application, the solar cell further includes a first conductive layer and a first electrode;

[0012] The first conductive layer is located on a side of the first doped microcrystalline silicon layer away from the first quantum well passivation structure, and the first electrode is located on a side of the first conductive layer away from the first doped microcrystalline silicon layer.

[0013] According to one embodiment of the present application, the first electrode includes a metal electrode, and the metal electrode includes a silver electrode, a silver-clad copper electrode, or an electroplated copper electrode.

[0014] According to one embodiment of the present application, the solar cell further includes a second quantum well passivation structure and a second doped microcrystalline silicon layer;

[0015] The second quantum well passivation structure is located on the backlight side of the silicon substrate, and the second doped microcrystalline silicon layer is located on a side of the second quantum well passivation structure away from the silicon substrate.

[0016] According to one embodiment of the present application, the second quantum well passivation structure includes at least two second silicon oxide passivation layers and at least one second intrinsic microcrystalline silicon layer;

[0017] At least two of the second silicon oxide passivation layers are sequentially stacked between the silicon substrate and the second doped microcrystalline silicon layer, and the second intrinsic microcrystalline silicon layer is located between any adjacent second silicon oxide passivation layers.

[0018] According to one embodiment of the present application, the solar cell further includes an intrinsic amorphous silicon layer and a second doped microcrystalline silicon layer;

[0019] The intrinsic amorphous silicon layer is located on the backlight side of the silicon substrate, and the second doped microcrystalline silicon layer is located on a side of the intrinsic amorphous silicon layer away from the silicon substrate.

[0020] According to one embodiment of the present application, the solar cell further includes a second conductive layer and a second electrode;

[0021] The second conductive layer is located on a side of the second doped microcrystalline silicon layer away from the silicon substrate, and the second electrode is located on a side of the second conductive layer away from the second doped microcrystalline silicon layer.

[0022] According to an embodiment of the present application, the silicon substrate is an n-type silicon substrate, the first doped microcrystalline silicon layer is an n-type doped microcrystalline silicon layer, and the second doped microcrystalline silicon layer is a p-type doped microcrystalline silicon layer.

[0023] In a second aspect, the present application provides a photovoltaic module, comprising the solar cell as described in the first aspect above.

[0024] The above one or more technical solutions in the embodiments of the present application have at least one of the following technical effects:

[0025] A first quantum well passivation structure is arranged on the light-receiving side of the silicon substrate, and the first quantum well passivation structure includes at least two first silicon oxide passivation layers and at least one first intrinsic microcrystalline silicon layer, and a first intrinsic microcrystalline silicon layer is provided between any two adjacent first silicon oxide passivation layers, which has an excellent passivation effect on the crystalline silicon surface, and no intrinsic amorphous silicon passivation layer is provided on the light-receiving side of the silicon substrate, thereby avoiding the problem of deterioration of the passivation effect of the intrinsic amorphous silicon passivation layer under ultraviolet light irradiation, alleviating the performance attenuation problem of solar cells induced by ultraviolet light, and the first quantum well passivation structure realizes selective transmission of electrons, thereby improving the separation capability of photogenerated carriers in solar cells.

[0026] Additional aspects and advantages of the present application will be given in part in the description below, and in part will become apparent from the description below, or will be learned through the practice of the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] The above and / or additional aspects and advantages of the present application will become apparent and easily understood from the description of the embodiments in conjunction with the following drawings, in which:

[0028] Figure 1 This is one of the structural schematic diagrams of the solar cell provided in the embodiment of the present application;

[0029] Figure 2 This is the second structural schematic diagram of the solar cell provided in the embodiment of the present application. DETAILED DESCRIPTION

[0030] The embodiments of the present application are described in detail below, and examples of the embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present application, and cannot be understood as limiting the present application.

[0031] The solar cell and photovoltaic module provided by the embodiments of the present application are described below with reference to the accompanying drawings.

[0032] Figure 1 A schematic diagram of the structure of a solar cell provided in an embodiment of the present application, wherein the solar cell may be a HJT cell.

[0033] like Figure 1As shown, the solar cell provided in the embodiment of the present application includes a silicon substrate 1 , a first quantum well passivation structure 2 and a first doped microcrystalline silicon layer 3 .

[0034] The silicon substrate 1 is doped with ions, such as the silicon substrate 1 may be an n-type silicon substrate. The silicon substrate 1 may include a single crystal silicon wafer. The silicon substrate 1 has a light-receiving side and a backlight side (non-light-receiving side), the light-receiving side of the silicon substrate 1 refers to the side irradiated by ultraviolet light, and the backlight side of the silicon substrate 1 is arranged opposite to the light-receiving side.

[0035] The first quantum well passivation structure 2 is located on the light-receiving side of the silicon substrate 1. The first quantum well passivation structure 2 is a laminated structure, in which the film layer is a passivation film layer, which has an excellent passivation effect on the crystalline silicon surface, and the laminated structure constitutes a quantum well structure to achieve selective transmission of electrons.

[0036] The first doped microcrystalline silicon layer 3 is located on the side of the first quantum well passivation structure 2 away from the silicon substrate 1. The doping type of the first doped microcrystalline silicon layer 3 is the same as the doping type of the silicon substrate 1. For example, if the silicon substrate 1 is an n-type silicon substrate, the first doped microcrystalline silicon layer 3 is an n-type doped microcrystalline silicon layer, and the silicon substrate 1 and the first doped microcrystalline silicon layer 3 can form an n-n heterojunction. The thickness of the first doped microcrystalline silicon layer 3 can be between 10 nm and 30 nm.

[0037] In the manufacturing process of solar cells, a silicon substrate 1 is first provided, and then the light-receiving side and the backlight side of the silicon substrate 1 can be cleaned and textured by a trough-type cleaning and texturing machine. A first quantum well passivation structure 2 is formed on the light-receiving side of the silicon substrate 1. A first doped microcrystalline silicon layer 3 is formed on the side of the first quantum well passivation structure 2 that is away from the silicon substrate 1. For example, a thin film deposition process can be used to deposit the first doped microcrystalline silicon layer 3 on the side of the first quantum well passivation structure 2 that is away from the silicon substrate 1. The thin film deposition process can be physical vapor deposition, chemical vapor deposition, atomic layer deposition, laser-assisted deposition, etc.

[0038] In this embodiment, a first quantum well passivation structure 2 is arranged on the light-receiving side of the silicon substrate 1, which has an excellent passivation effect on the crystalline silicon surface, and the intrinsic amorphous silicon passivation layer is no longer arranged on the light-receiving side of the silicon substrate 1, that is, the first quantum well passivation structure 2 is used to replace the intrinsic amorphous silicon passivation layer on the light-receiving side of the silicon substrate 1, so as to avoid the problem of poor passivation effect on the surface of the battery due to the breakage of the silicon-hydrogen bond in the intrinsic amorphous silicon passivation layer under ultraviolet light irradiation, and alleviate the performance attenuation problem of solar cells induced by ultraviolet light. Moreover, the arrangement of the first quantum well passivation structure 2 realizes the selective transmission of electrons and improves the separation ability of photogenerated carriers in solar cells.

[0039] The first quantum well passivation structure 2 includes at least two first silicon oxide passivation layers 21 and at least one first intrinsic microcrystalline silicon layer 22. At least two first silicon oxide passivation layers 21 are stacked between the silicon substrate 1 and the first doped microcrystalline silicon layer 3, and there is a first intrinsic microcrystalline silicon layer 22 between any adjacent first silicon oxide passivation layers 21.

[0040] The number of the first silicon oxide passivation layer 21 and the first intrinsic microcrystalline silicon layer 22 can be set according to actual needs and is not specifically limited here. For example, the first quantum well passivation structure 2 includes two first silicon oxide passivation layers 21 and one first intrinsic microcrystalline silicon layer 22, and the first intrinsic microcrystalline silicon layer 22 is located between the two first silicon oxide passivation layers 21.

[0041] In some embodiments, the first silicon oxide passivation layer 21 may be a SiOx layer, and the thickness of the first silicon oxide passivation layer 21 is between 0.5 nm and 1.5 nm. The first intrinsic microcrystalline silicon layer 22 may be an i-Si layer, and the thickness of the first intrinsic microcrystalline silicon layer 22 is between 3 nm and 10 nm.

[0042] In the manufacturing process, a first silicon oxide passivation layer 21 is first formed on the light-receiving side of the silicon substrate 1. For example, the light-receiving side of the silicon substrate 1 is thermally oxidized by a vacuum tube furnace to generate the first silicon oxide passivation layer 21. The first silicon oxide passivation layer 21 has an excellent passivation effect on the light-receiving side of the silicon substrate 1, reducing the carrier recombination on the surface of the silicon substrate 1 after texturing.

[0043] Then, a first intrinsic microcrystalline silicon layer 22 is formed on the side of the first silicon oxide passivation layer 21 away from the silicon substrate 1. For example, a thin film deposition process can be used to deposit the first intrinsic microcrystalline silicon layer 22 on the side of the first silicon oxide passivation layer 21 away from the silicon substrate 1. The first intrinsic microcrystalline silicon layer 22 has a low hydrogen content, which prevents the film structure from being destroyed under ultraviolet light.

[0044] Then, another first silicon oxide passivation layer 21 is formed on the side of the first intrinsic microcrystalline silicon layer 22 away from the silicon substrate 1. For example, the first silicon oxide passivation layer 21 is formed by thermally oxidizing the side of the first intrinsic microcrystalline silicon layer 22 away from the silicon substrate 1 in a vacuum tube furnace.

[0045] In this embodiment, the stacked structure of the first silicon oxide passivation layer 21, the first intrinsic microcrystalline silicon layer 22 and the first silicon oxide passivation layer 21 (SiO x / i-Si / SiO x) constitutes a first quantum well passivation structure 2. The first silicon oxide passivation layer 21 in the first quantum well passivation structure 2 has an excellent passivation effect on the crystalline silicon surface of the solar cell, and the first quantum well passivation structure 2 does not have an intrinsic amorphous silicon passivation layer, that is, the light-receiving side of the solar cell does not have an intrinsic amorphous silicon passivation layer, which avoids the problem of the intrinsic amorphous silicon passivation layer on the light-receiving side of the solar cell having a poor passivation effect under ultraviolet irradiation, thereby alleviating the performance degradation problem of the solar cell induced by ultraviolet light. In addition, the first quantum well passivation structure 2 realizes the selective transmission of electrons and improves the separation ability of photogenerated carriers in the solar cell.

[0046] In some embodiments, Figure 1 As shown, the solar cell further comprises an intrinsic amorphous silicon layer 4 and a second doped microcrystalline silicon layer 5. The intrinsic amorphous silicon layer 4 is located on the backlight side of the silicon substrate 1, and the second doped microcrystalline silicon layer 5 is located on the side of the intrinsic amorphous silicon layer 4 away from the silicon substrate 1.

[0047] The doping type of the second doped microcrystalline silicon layer 5 is different from the doping type of the silicon substrate 1 . For example, if the silicon substrate 1 is an n-type substrate and the second doped microcrystalline silicon layer 5 is a p-type doped microcrystalline silicon layer, the silicon substrate 1 and the second doped microcrystalline silicon layer 5 may form a pn heterojunction.

[0048] The thickness of the intrinsic amorphous silicon layer 4 may be between 5 nm and 15 nm, and the thickness of the second doped microcrystalline silicon layer 5 may be between 10 nm and 30 nm.

[0049] In the manufacturing process, while the light-receiving side of the silicon substrate 1 is thermally oxidized to form the first silicon oxide passivation layer 21, the backlight side of the silicon substrate 1 is thermally oxidized to form a silicon oxide layer. Therefore, before forming the intrinsic amorphous silicon layer 4, the silicon oxide layer on the backlight side of the silicon substrate 1 is removed. For example, the silicon oxide layer on the backlight side of the silicon substrate 1 is removed by a chain cleaning machine.

[0050] Then, an intrinsic amorphous silicon layer 4 is formed on the backlight side of the silicon substrate 1. For example, a thin film deposition process can be used to deposit the intrinsic amorphous silicon layer 4 on the backlight side of the silicon substrate 1.

[0051] Then, a second doped microcrystalline silicon layer 5 is formed on the side of the intrinsic amorphous silicon layer 4 away from the silicon substrate. For example, a thin film deposition process can be used to deposit the second doped microcrystalline silicon layer 5 on the side of the intrinsic amorphous silicon layer 4 away from the silicon substrate.

[0052] In this embodiment, an intrinsic amorphous silicon layer 4 may be disposed on the backlight side of the silicon substrate 1. Since the backlight side of the silicon substrate 1 is less exposed to ultraviolet light, no excessive H atom clusters are generated in the intrinsic amorphous silicon layer 4, which will not have much impact on the passivation effect of the crystalline silicon surface.

[0053] In some embodiments, Figure 2As shown, the solar cell further includes a second quantum well passivation structure 6 and a second doped microcrystalline silicon layer 5. The second quantum well passivation structure 6 is located on the backlight side of the silicon substrate 1, and the second doped microcrystalline silicon layer 5 is located on the side of the second quantum well passivation structure 6 away from the silicon substrate 1.

[0054] The second quantum well passivation structure 6 is a stacked structure composed of a passivation film layer. The second quantum well passivation structure 6 can have the same structure as the first quantum well passivation structure 2. The doping type of the second doped microcrystalline silicon layer 5 is different from the doping type of the silicon substrate 1. For example, if the silicon substrate 1 is an n-type substrate, the second doped microcrystalline silicon layer 5 is a p-type doped microcrystalline silicon layer, and the silicon substrate 1 and the second doped microcrystalline silicon layer 5 can form a pn heterojunction.

[0055] In this embodiment, a second quantum well passivation structure 6 is arranged on the backlight side of the silicon substrate 1. The second quantum well passivation structure 6 has an excellent passivation effect on the crystalline silicon surface of the solar cell, and the backlight side of the solar cell does not have an intrinsic amorphous silicon passivation layer, which further alleviates the performance attenuation problem of the solar cell induced by ultraviolet light.

[0056] In some embodiments, the second quantum well passivation structure 6 includes at least two second silicon oxide passivation layers 61 and at least one second intrinsic microcrystalline silicon layer 62. At least two second silicon oxide passivation layers 61 are stacked between the silicon substrate 1 and the second doped microcrystalline silicon layer 5, and there is a second intrinsic microcrystalline silicon layer 62 between any adjacent second silicon oxide passivation layers 61.

[0057] The number of the second silicon oxide passivation layer 61 and the second intrinsic microcrystalline silicon layer 62 can be set according to actual needs and is not specifically limited here. For example, the second quantum well passivation structure 6 includes two second silicon oxide passivation layers 61 and one second intrinsic microcrystalline silicon layer 62, and the second intrinsic microcrystalline silicon layer 62 is located between the two second silicon oxide passivation layers 61.

[0058] In some embodiments, the second silicon oxide passivation layer 61 may be a SiOx layer, and the thickness of the second silicon oxide passivation layer 61 is between 0.5 nm and 1.5 nm. The second intrinsic microcrystalline silicon layer 62 may be an i-Si layer, and the thickness of the second intrinsic microcrystalline silicon layer 62 is between 3 nm and 10 nm.

[0059] In the manufacturing process, while the light-receiving side of the silicon substrate 1 is thermally oxidized to form the first silicon oxide passivation layer 21 , the backlight side of the silicon substrate 1 is thermally oxidized to form a silicon oxide layer, which is a second silicon oxide passivation layer 61 .

[0060] Then, a second intrinsic microcrystalline silicon layer 62 is formed on the side of the second silicon oxide passivation layer 61 away from the silicon substrate 1. For example, the second intrinsic microcrystalline silicon layer 62 can be deposited on the side of the second silicon oxide passivation layer 61 away from the silicon substrate 1 by using a thin film deposition process.

[0061] Then, another second silicon oxide passivation layer 61 is formed on the side of the second intrinsic microcrystalline silicon layer 62 away from the silicon substrate 1. For example, the second silicon oxide passivation layer 61 is formed by thermally oxidizing the side of the second intrinsic microcrystalline silicon layer 62 away from the silicon substrate 1 in a vacuum tube furnace.

[0062] In this embodiment, the stacked structure (SiOx / i-Si / SiOx) of the second silicon oxide passivation layer 61, the second intrinsic microcrystalline silicon layer 62 and the second silicon oxide passivation layer 61 constitutes the second quantum well passivation structure 6. The second silicon oxide passivation layer 61 in the second quantum well passivation structure 6 has an excellent passivation effect on the crystalline silicon surface of the solar cell, and the second quantum well passivation structure 6 does not have an intrinsic amorphous silicon passivation layer, that is, the backlight side of the solar cell does not have an intrinsic amorphous silicon passivation layer, which further alleviates the performance degradation problem of the solar cell induced by ultraviolet light.

[0063] In some embodiments, the solar cell further comprises a first conductive layer 7 and a first electrode 8. The first conductive layer 7 is located on a side of the first doped microcrystalline silicon layer 3 away from the first quantum well passivation structure 2, and the first electrode 8 is located on a side of the first conductive layer 7 away from the first doped microcrystalline silicon layer 3.

[0064] The first conductive layer 7 may be a TCO layer, and the material of the first conductive layer 7 may include ITO, ICO or IWO, etc. The thickness of the first conductive layer 7 may be between 80nm and 100nm. The first electrode 8 may include a metal electrode, and the material of the first electrode 8 may include silver, silver-clad copper or electroplated copper, etc.

[0065] In some embodiments, the solar cell further comprises a second conductive layer 9 and a second electrode 10. The second conductive layer 9 is located on a side of the second doped microcrystalline silicon layer 5 away from the silicon substrate 1, and the second electrode 10 is located on a side of the second conductive layer 9 away from the second doped microcrystalline silicon layer 5.

[0066] The second conductive layer 9 may be a TCO layer, and the material of the second conductive layer 9 may include ITO, ICO or IWO, etc. The thickness of the second conductive layer 9 may be between 80nm and 100nm. The second electrode 10 may include a metal electrode, and the material of the second electrode 10 may include silver, silver-clad copper or electroplated copper, etc.

[0067] In the manufacturing process, a first conductive layer 7 is formed on a side of the first doped microcrystalline silicon layer 3 away from the first quantum well passivation structure 2, and a second conductive layer 9 is formed on a side of the second doped microcrystalline silicon layer 5 away from the silicon substrate 1. For example, the first conductive layer 7 is deposited on a side of the first doped microcrystalline silicon layer 3 away from the first quantum well passivation structure 2, and the second conductive layer 9 is deposited on a side of the second doped microcrystalline silicon layer 5 away from the silicon substrate 1 by magnetron sputtering or RPD.

[0068] Then, a first electrode 8 is formed on a side of the first conductive layer 7 facing away from the first doped microcrystalline silicon layer 3 , and a second electrode 10 is formed on a side of the second conductive layer 9 facing away from the second doped microcrystalline silicon layer 5 .

[0069] The solar cell provided in the embodiment of the present application may be a HJT solar cell. HJT solar cells have many advantages: (1) HJT solar cells can avoid potential induced degradation (PID); (2) HJT solar cells have a better temperature coefficient than PERC and TOPCon cells, and have stable output power; (3) HJT solar cells have a symmetrical structure and a high bifaciality; (4) HJT solar cells are suitable for thin-film development, reducing silicon wafer costs; (5) HJT solar cells have high conversion efficiency; (6) The preparation process of HJT solar cells is short, which is conducive to industrialization.

[0070] In the related art, there are many strategies to alleviate the problem of ultraviolet-induced degradation (UVID) of solar cells. For example, an encapsulation film with ultraviolet cutoff function is used to alleviate UVID. Different ultraviolet absorbers are added to this type of encapsulation film during the synthesis process, such as benzophenone or benzotriazole-based ultraviolet absorbers, which have a characteristic absorption peak wavelength of 280-380nm, and only allow photons with a wavelength greater than 360nm to reach the surface of the battery, thereby reducing ultraviolet light irradiation to the battery. However, the use of ultraviolet light absorbers may cause discoloration of the encapsulation film, which in turn leads to reduced battery performance. In addition, the cost of the absorber, the power loss caused by potential discoloration, and the power loss caused by UVID all need to be considered.

[0071] For another example, in encapsulated photovoltaic modules, specialized glass cover sheets (such as Ce-doped glass) are used to reduce the UVID of solar cells. However, this energy-intensive process, high production costs and poor recyclability have limited its effectiveness.

[0072] Another example is using a photoconversion film with a photoconversion function to mitigate UVID. Particles with a down-conversion function are added to the photoconversion film, which can absorb high-energy ultraviolet photons and convert them into low-energy visible photons for radiation, thereby alleviating the UVID of solar cells while increasing the light absorption of solar cells. However, the cost of this photoconversion film is high, and the UV light irradiation stability of the photoconversion film needs to be considered.

[0073] In this embodiment, a first quantum well passivation structure 2 is arranged on the light-receiving side of the silicon substrate 1. The first quantum well passivation structure 2 includes at least two first silicon oxide passivation layers 21 and at least one first intrinsic microcrystalline silicon layer 22, and there is a first intrinsic microcrystalline silicon layer 22 between any two adjacent first silicon oxide passivation layers 21. The first silicon oxide passivation layer 21 has an excellent passivation effect on the crystalline silicon surface, and the first quantum well passivation structure 2 does not have an intrinsic amorphous silicon passivation layer, thereby avoiding the problem of the passivation effect of the intrinsic amorphous silicon passivation layer being deteriorated under ultraviolet irradiation, alleviating the UVID of the solar cell, and ensuring the conversion efficiency of the solar cell, avoiding the use of an additional functional adhesive film when the solar cell is packaged into a component, and reducing the actual use cost of the solar cell. Moreover, the first quantum well passivation structure 2 realizes the selective transmission of electrons and improves the separation ability of photogenerated carriers in the solar cell.

[0074] Accordingly, the embodiment of the present application further provides a photovoltaic module, including the solar cell in the above embodiment, which will not be described in detail here. The photovoltaic module may include a plurality of solar cell strings, and the solar cell strings include the solar cells in the above embodiment.

[0075] According to the photovoltaic module provided by the embodiment of the present application, a first quantum well passivation structure is arranged on the light-receiving side of the silicon substrate, and the first quantum well passivation structure includes at least two first silicon oxide passivation layers and at least one first intrinsic microcrystalline silicon layer, and a first intrinsic microcrystalline silicon layer is provided between any two adjacent first silicon oxide passivation layers, which has an excellent passivation effect on the crystalline silicon surface, and an intrinsic amorphous silicon passivation layer is no longer provided on the light-receiving side of the silicon substrate, thereby avoiding the problem of deterioration of the passivation effect of the intrinsic amorphous silicon passivation layer under ultraviolet light irradiation, alleviating the performance attenuation problem of solar cells induced by ultraviolet light, and the first quantum well passivation structure realizes selective transmission of electrons, thereby improving the separation ability of photogenerated carriers in solar cells.

[0076] The terms "first", "second", etc. in the specification and claims of this application are used to distinguish similar objects, and are not used to describe a specific order or sequence. It should be understood that the terms used in this way can be interchangeable under appropriate circumstances, so that the embodiments of the present application can be implemented in an order other than those illustrated or described herein, and the objects distinguished by "first", "second", etc. are generally of the same type, and the number of objects is not limited. For example, the first object can be one or more.

[0077] In the description of the present application, “plurality” means two or more.

[0078] In the description of this specification, the description with reference to the terms "one embodiment", "some embodiments", "illustrative embodiments", "examples", "specific examples", or "some examples" means that the specific features, structures, materials, or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present application. In this specification, the schematic representation of the above terms does not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials, or characteristics described may be combined in any one or more embodiments or examples in a suitable manner.

[0079] Although the embodiments of the present application have been shown and described, those skilled in the art will appreciate that various changes, modifications, substitutions and variations may be made to the embodiments without departing from the principles and spirit of the present application, and that the scope of the present application is defined by the claims and their equivalents.

Claims

1. A solar cell, characterized in that: include: Silicon substrate; A first quantum well passivation structure is located on the light-receiving side of the silicon substrate; A first doped microcrystalline silicon layer is located on a side of the first quantum well passivation structure away from the silicon substrate; Among them, the first quantum well passivation structure includes at least two first silicon oxide passivation layers and at least one first intrinsic microcrystalline silicon layer; at least two of the first silicon oxide passivation layers are stacked between the silicon substrate and the first doped microcrystalline silicon layer, and the first intrinsic microcrystalline silicon layer is provided between any adjacent first silicon oxide passivation layers.

2. The solar cell according to claim 1, characterized in that The thickness of the first silicon oxide passivation layer is between 0.5 nm and 1.5 nm, and the thickness of the first intrinsic microcrystalline silicon layer is between 3 nm and 10 nm.

3. The solar cell according to claim 1 or 2, characterized in that: The solar cell further comprises a first conductive layer and a first electrode; The first conductive layer is located on a side of the first doped microcrystalline silicon layer away from the first quantum well passivation structure, and the first electrode is located on a side of the first conductive layer away from the first doped microcrystalline silicon layer.

4. The solar cell according to claim 3, characterized in that: The first electrode comprises a metal electrode, and the metal electrode comprises a silver electrode, a silver-clad copper electrode or an electroplated copper electrode.

5. The solar cell according to claim 1, characterized in that: The solar cell further comprises a second quantum well passivation structure and a second doped microcrystalline silicon layer; The second quantum well passivation structure is located on the backlight side of the silicon substrate, and the second doped microcrystalline silicon layer is located on a side of the second quantum well passivation structure away from the silicon substrate.

6. The solar cell according to claim 5, characterized in that The second quantum well passivation structure includes at least two second silicon oxide passivation layers and at least one second intrinsic microcrystalline silicon layer; At least two of the second silicon oxide passivation layers are sequentially stacked between the silicon substrate and the second doped microcrystalline silicon layer, and the second intrinsic microcrystalline silicon layer is located between any adjacent second silicon oxide passivation layers.

7. The solar cell according to claim 1, characterized in that The solar cell further comprises an intrinsic amorphous silicon layer and a second doped microcrystalline silicon layer; The intrinsic amorphous silicon layer is located on the backlight side of the silicon substrate, and the second doped microcrystalline silicon layer is located on a side of the intrinsic amorphous silicon layer away from the silicon substrate.

8. The solar cell according to any one of claims 5 to 7, characterized in that: The solar cell further comprises a second conductive layer and a second electrode; The second conductive layer is located on a side of the second doped microcrystalline silicon layer away from the silicon substrate, and the second electrode is located on a side of the second conductive layer away from the second doped microcrystalline silicon layer.

9. The solar cell according to claim 7, characterized in that: The silicon substrate is an n-type silicon substrate, the first doped microcrystalline silicon layer is an n-type doped microcrystalline silicon layer, and the second doped microcrystalline silicon layer is a p-type doped microcrystalline silicon layer.

10. A photovoltaic module, characterized in that: The invention comprises a solar cell as claimed in any one of claims 1 to 9.

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