Chip sealing ring structure

Abstract

The utility model provides a chip sealing ring structure, which comprises a first sealing ring arranged around a chip integrated circuit area, the first sealing ring comprises a plurality of dielectric layers arranged in a laminated manner, and metal layers arranged in the dielectric layers and flush with the dielectric layers, through hole strips and through holes which are filled with conductive materials are arranged in the dielectric layer so as to realize the connection among the metal layers, and the through hole strips are curve-shaped. Compared with a linear through hole strip, the curved through hole strip can better resist stress applied to the chip when the chip is cut, the interface between the through hole strip and the metal layer is prevented from being broken when the chip is cut, namely, the sealing ring is prevented from being broken when the chip is cut, so that the phenomenon that the chip is layered and broken is avoided, and the cutting yield is improved.

Description

Technical Field

[0001] The utility model relates to the field of semiconductor manufacturing, in particular to a chip sealing ring structure. Background Art

[0002] In the production of semiconductor chips, a chip sealing ring is set between the scribe line and the chip integrated circuit area to keep the inside of the chip sealed to prevent cracks from extending from the scribe line to the circuit area of ​​the chip when the chip is cut, causing the chip to break. At the same time, since the dielectric layer inside the chip is mostly formed by porous low-dielectric constant materials, under certain conditions, moisture can easily penetrate the low-dielectric constant dielectric layer and reach the circuit area, causing chip damage. By setting a sealing ring, which is formed of metal, the way for moisture to enter the chip circuit area is blocked, and the chemical damage to the chip caused by water vapor penetration and the diffusion of acidic substances, alkaline substances or pollution sources is blocked.

[0003] Traditional sealing rings are generally made of multiple metal layers stacked together, usually a single sealing ring or a double sealing ring. The sealing ring is a continuous metal wire that surrounds the outside of the chip integrated circuit area. Figure 1 This is a cross-sectional view of a chip sealing ring structure in the prior art. Please refer to Figure 1 As shown, the chip sealing ring structure includes a dielectric layer 20 stacked in multiple layers, and a metal layer 30 arranged in the dielectric layer 20 and flush with the dielectric layer, and a through hole 21 filled with a conductive material is arranged in the dielectric layer 20 to achieve connection between the metal layers 30 of each layer. A metal plug 11 connecting the bottom metal layer 30 and the substrate 10 is formed in the dielectric layer 20 of the bottom layer.

[0004] When the existing sealing ring is used for sealing, the mechanical strength and adhesion performance between the through hole 21 in the sealing ring and the upper and lower metal layers 30 are insufficient. During the cutting process, due to the influence of the mechanical stress applied to the substrate 10 or the wafer, the interface between the through hole 21 and the metal layer 30 is broken or split, and the fracture extends to the chip integrated circuit area, causing the chip to be delaminated and broken, affecting the yield of the product after cutting. Utility Model Content

[0005] The utility model aims to provide a chip sealing ring structure, which can prevent the sealing ring from breaking when the chip is cut, avoid the phenomenon of chip delamination and fracture, and improve the cutting yield.

[0006] In order to solve the above technical problems, the utility model provides a chip sealing ring structure, including a first sealing ring arranged around the chip integrated circuit area, the first sealing ring including a plurality of stacked dielectric layers, and a metal layer arranged in the dielectric layer and flush with the dielectric layer, and a through-hole bar and a through-hole filled with a conductive material are arranged in the dielectric layer to realize the connection between each metal layer, wherein the through-hole bar is curved.

[0007] Optionally, the curved through-hole bar forms a plurality of grooves, and the through holes are arranged in the grooves.

[0008] Optionally, the through-hole bars include a plurality of linear first through-hole bars extending along a first direction, a plurality of linear second through-hole bars extending along a second direction, and a plurality of third through-hole bars extending along a third direction, and the extension lines of the plurality of first through-hole bars constitute two parallel lines along the first direction, and the second through-hole bars and the third through-hole bars are located between the two parallel lines and are connected to the first through-hole bar to form a first groove and a second groove with openings facing opposite directions, and the through hole is located in the first groove and / or the second groove.

[0009] Optionally, the angle between the second direction and the first direction is equal to the angle between the third direction and the first direction, and the cross-sections of the first groove and the second groove are isosceles trapezoids.

[0010] Optionally, the bottom surface size of the first groove is not equal to the bottom surface size of the second groove.

[0011] Optionally, the second direction is parallel to the third direction, and the first direction is perpendicular to the second direction, and the cross-sections of the first groove and the second groove are rectangular or square.

[0012] Optionally, adjacent through-hole bars are arranged axially symmetrically, and the through holes are located in the first groove and / or the second groove.

[0013] Optionally, the adjacent through-hole bars are axially symmetrically arranged, and the openings of the first grooves and the second grooves of two adjacent through-hole bars form a third groove relative to each other, and the through hole is located in the third groove.

[0014] Optionally, the via bar is in the form of a wavy line.

[0015] Optionally, the chip sealing ring structure also includes a second sealing ring arranged around the first sealing ring, the second sealing ring includes a dielectric layer stacked in multiple layers, and a metal layer arranged in the dielectric layer and flush with the dielectric layer, and a through-hole bar filled with conductive material is arranged in the dielectric layer to achieve connection between each metal layer, wherein the through-hole bar is curved.

[0016] Compared with the prior art, the chip sealing ring structure provided by the utility model includes a first sealing ring arranged around the chip integrated circuit area, the first sealing ring includes a dielectric layer stacked in multiple layers, and a metal layer arranged in the dielectric layer and flush with the dielectric layer, and a through-hole bar and a through-hole filled with a conductive material are arranged in the dielectric layer to achieve connection between each metal layer, wherein the through-hole bar is curved, and compared with a straight through-hole bar, the curved through-hole bar can better resist the stress applied to the chip when the chip is cut, thereby avoiding the interface between the through-hole bar and the metal layer from being broken when the chip is cut, that is, avoiding the fracture at the sealing ring when the chip is cut, thereby avoiding the phenomenon of delamination and fracture of the chip, and improving the cutting yield.

[0017] Furthermore, the curved via bar forms a plurality of grooves, and the through holes are arranged in the grooves, thereby preventing the via bar from being broken due to stress changes, and further improving the cutting yield. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Those skilled in the art will appreciate that the drawings are provided for a better understanding of the present invention and do not constitute any limitation on the scope of the present invention.

[0019] Figure 1 It is a cross-sectional view of a chip sealing ring structure in the prior art.

[0020] Figure 2 It is a top view of a chip sealing ring structure provided by an embodiment of the utility model.

[0021] Figure 3 It is a partial top view of a chip sealing ring structure provided by an embodiment of the utility model.

[0022] Figure 4 It is a cross-sectional view of a chip sealing ring structure provided by an embodiment of the utility model.

[0023] Figure 5 It is a partial top view of a chip sealing ring structure provided by an embodiment of the utility model.

[0024] Figure 6 It is a partial top view of a chip sealing ring structure provided by an embodiment of the utility model.

[0025] Figure 7 It is a partial top view of a chip sealing ring structure provided by an embodiment of the utility model.

[0026] Figure 8 It is a partial top view of a chip sealing ring structure provided by an embodiment of the utility model.

[0027] Fig. 9It is a partial top view of a chip sealing ring structure provided by an embodiment of the utility model.

[0028] Fig.10 It is a top view of a chip sealing ring structure provided by an embodiment of the utility model.

[0029] Fig.11 It is a top view of a chip sealing ring structure provided by an embodiment of the utility model.

[0030] Fig.12 It is a partial top view of a chip sealing ring structure provided by an embodiment of the utility model.

[0031] Description of reference numerals:

[0032] 1-first sealing ring; 10-substrate; 11-metal plug; 20-dielectric layer; 30-metal layer; 21-through hole; 22-through hole bar; 221-first through hole bar; 222-second through hole bar; 223-third through hole bar; 224-first groove; 225-second groove; 226-third groove; 2-integrated circuit area; 3-second sealing ring. DETAILED DESCRIPTION

[0033] In order to make the purpose, advantages and features of the utility model clearer, the utility model is further described in detail below in conjunction with the accompanying drawings and specific embodiments. It should be noted that the drawings are all in a very simplified form and are not drawn to scale, and are only used to conveniently and clearly assist in explaining the purpose of the embodiments of the utility model. In addition, the structure shown in the drawings is often a part of the actual structure. In particular, the emphasis of each drawing is different, and sometimes different scales are used.

[0034] As used in the present invention, the singular forms "one", "an", and "the" include plural objects, unless the content clearly indicates otherwise. As used in the present invention, the term "or" is generally used in a sense that includes "and / or", unless the content clearly indicates otherwise. As used in the present invention, the term "several" is generally used in a sense that includes "at least one", unless the content clearly indicates otherwise. As used in the present invention, the term "at least two" is generally used in a sense that includes "two or more", unless the content clearly indicates otherwise. In addition, the terms "first", "second", and "third" are used only for descriptive purposes and cannot be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Therefore, the features defined as "first", "second", and "third" may explicitly or implicitly include one or at least two of the features.

[0035] Figure 2is a top view of a chip sealing ring structure provided by an embodiment of the utility model, Figure 3 This is a partial top view of a chip sealing ring structure provided by an embodiment of the utility model. Figure 4 is a cross-sectional view of a chip sealing ring structure provided by an embodiment of the present invention, wherein Figure 3 yes Figure 2 The enlarged image of the dotted box, Figure 4 yes Figure 3 Cross-section at the dotted line. Please refer to Figure 2 , Figure 3 and Figure 4 As shown, the chip sealing ring structure provided by the embodiment of the utility model includes a first sealing ring 1 arranged around the chip integrated circuit area 2, the first sealing ring 1 includes a dielectric layer 20 stacked in multiple layers, and a metal layer 30 arranged in the dielectric layer 20 and flush with the dielectric layer 20, and a through-hole bar 22 and a through-hole 21 filled with a conductive material are arranged in the dielectric layer 20 to achieve connection between each metal layer 30, wherein the through-hole bar 22 is curved.

[0036] In the utility model, compared with the straight-line via bar, the curved via bar 22 can better resist the stress applied to the chip when the chip is cut, thereby avoiding the interface between the via bar 22 and the metal layer 30 from being broken when the chip is cut, that is, avoiding the sealing ring from being broken when the chip is cut, thereby avoiding the phenomenon of delamination and fracture of the chip and improving the cutting yield.

[0037] In an embodiment of the present invention, the curved through-hole bar 22 forms a plurality of grooves, and the through-holes 21 are disposed in the grooves, thereby preventing the through-hole bar 22 from being broken due to stress changes, and further improving the cutting yield. In this embodiment, the through-holes 21 refer to discrete through-holes.

[0038] The via bars 22 are curved, and can be any curve known to those skilled in the art. Multiple via bars 22 can be formed in each dielectric layer 20, and the multiple via bars 22 can be arranged regularly. In the embodiment of the utility model, three via bars 22 are provided in the dielectric layer 20 for illustration, but the number of via bars 22 is not limited thereto.

[0039] The specific curve shape of the via bar 22 is illustrated in the following embodiments.

[0040] First, please refer to Figure 3As shown, the through-hole bar 22 is of a zigzag type, and the through-hole bar 22 includes a plurality of linear first through-hole bars 221 extending along a first direction, a plurality of linear second through-hole bars 222 extending along a second direction, and a plurality of linear third through-hole bars 223 extending along a third direction. The extension lines of the plurality of first through-hole bars 221 form two parallel lines along the first direction. The second through-hole bar 222 and the third through-hole 223 are located between the two parallel lines, and are connected with the first through-hole bar 221 to form a first groove 224 and a second groove 225 with openings facing opposite directions. The through-hole 21 is located in the first groove 224 and / or the second groove 225. In this embodiment, the first through-hole bar 221, the second through-hole bar 222, the first through-hole bar 221, and the third through-hole bar 223 are repeatedly connected in sequence to form the first groove 224 and the second groove 225. In this embodiment, the through hole 21 is located in the first groove 224 . In other embodiments, the through hole 21 may be located in the second groove 225 , or the through hole 21 may be located in both the first groove 224 and the second groove 225 .

[0041] In this embodiment, the angle α between the second through-hole bar 222 and the first through-hole bar 221 and the angle β between the third through-hole bar 223 and the first through-hole bar 221 are equal, that is, the second direction and the third direction rotate at the same angle relative to the first direction and in opposite directions. The opening direction of the first groove 224 is vertically upward, and the opening direction of the second groove 225 is vertically downward. The opening directions of the first groove 224 and the second groove 225 are perpendicular to the first direction. The lengths of the second through-hole bar 222 and the third through-hole bar 223 are equal, and the cross-sections of the first groove 224 and the second groove 225 are isosceles trapezoids.

[0042] In one embodiment of the utility model, the bottom size of the first groove 224 is not equal to the bottom size of the second groove 225, that is, the length of the first through-hole bar 221 constituting the first groove 224 is not equal to the length of the first through-hole bar 221 constituting the second groove 225, that is, the first through-hole bar 221 has two lengths. In another embodiment, the bottom size of the first groove 224 is equal to the bottom size of the second groove 225, that is, the size of the first groove 224 and the second groove 225 are exactly the same, and in this case, the first through-hole bar 221 has only one length.

[0043] Figure 5 This is a partial top view of a chip sealing ring structure provided by an embodiment of the present invention. Figure 5As shown, based on the previous embodiment, the second direction is parallel to the third direction, and the first direction is perpendicular to the second direction. The following description will take the second direction and the third direction as an example.

[0044] In this embodiment, the through-hole bar 22 includes a plurality of first through-hole bars 221 extending along a first direction X and a plurality of second through-hole bars 222 extending along a second direction Y, the first direction X is perpendicular to the second direction Y, the extension lines of the plurality of first through-hole bars 221 form two parallel lines along the first direction X, the second through-hole bar 222 is located between the two parallel lines, and is connected with the first through-hole bar 221 to form a first groove 224 and a second groove 225 with openings facing opposite directions. The cross-sections of the first groove 224 and the second groove 225 may be square or rectangular, and the sizes of the first groove 224 and the second groove 225 may be equal or unequal. When the sizes of the first groove 224 and the second groove 225 are equal, the first through-hole bar 221 has a length, and when the sizes of the first groove 224 and the second groove 225 are unequal, that is, the sizes of the first through-hole bar 221 forming the first groove 224 and the first through-hole bar 221 forming the second groove 225 are unequal.

[0045] In this embodiment, the through hole 21 is located in the first groove 224. In another embodiment of the present invention, the through hole 21 may be located in the second groove 225.

[0046] Figure 6 This is a partial top view of a chip sealing ring structure provided by an embodiment of the present invention. Figure 6 As shown, this embodiment and Figure 5 The difference of the illustrated embodiment is that the through hole 21 is located in the first groove 224 and the second groove 225 .

[0047] Figure 7 This is a partial top view of a chip sealing ring structure provided by an embodiment of the present invention. Figure 7 As shown, the through-hole bar 22 includes a plurality of first through-hole bars 221 extending along the first direction X and a plurality of second through-hole bars 222 extending along the second direction Y, wherein the first through-hole bars 221 and the second through-hole bars 222 are sequentially connected and arranged. The through-hole bar 22 is formed with an opening facing the positive direction in the second direction Y (i.e. Figure 7 The first groove 224 and the opening are oriented in the opposite direction of the second direction Y (i.e. Figure 7 In addition, in this embodiment, the adjacent through-hole bars 22 are axially symmetrically arranged, and the axis of symmetry is a straight line between the adjacent through-hole bars 22. For example, please refer to Figure 7 In the first through hole bar 22, the first groove formed by the first through hole bar 221 and the two second through hole bars 222 from left to right is a first groove 224 with an opening facing upward, and the first groove formed by the first through hole bar 221 and the two second through hole bars 222 from left to right is a second groove 225 with an opening facing downward, and the shape of the third through hole bar 22 can be the same as that of the first through hole bar 22. That is, the two through hole bars 22 are arranged at intervals in an axisymmetric manner. The through hole 21 is located in the first groove 224 formed by each of the through hole bars 22. Of course, in another embodiment, the through hole 21 is located in the second groove 225 formed by each of the through hole bars 22.

[0048] In another embodiment, the shape of the third via bar 22 may be the same as the shape of the second via bar 22 , that is, two adjacent via bars 22 are axially symmetrically arranged to form a via bar pair, and adjacent via bar pairs may also be axially symmetrically arranged.

[0049] Figure 8 This is a partial top view of a chip sealing ring structure provided by an embodiment of the present invention. Figure 7 As shown, the through-hole bar 22 includes a plurality of first through-hole bars 221 extending along the first direction X and a plurality of second through-hole bars 222 extending along the second direction Y, wherein the first through-hole bars 221 and the second through-hole bars 222 are sequentially connected and arranged. The through-hole bar 22 is formed with an opening facing the positive direction in the second direction Y (i.e. Figure 7 The first groove 224 and the opening are oriented in the opposite direction of the second direction Y (i.e. Figure 7 In addition, in the present embodiment, the adjacent through-hole bars 22 are axially symmetrically arranged, and the axis of symmetry is a straight line between the adjacent through-hole bars 22. The openings of the first groove 224 and the second groove 225 of two adjacent through-hole bars 22 are opposite to each other to form a third groove 226, and the through hole is located in the third groove 226. Specifically, the second groove 225 of the first through-hole bar 22 and the opening of the first groove 224 of the second through-hole bar 22 are opposite to each other to form the third groove 226, and the second groove 225 of the second through-hole bar 22 and the opening of the first groove 224 of the third through-hole bar 22 are opposite to each other to form the third groove 226, and the through hole 21 is arranged in the third groove 226.

[0050] Fig. 9 This is a partial top view of a chip sealing ring structure provided by an embodiment of the present invention. Fig. 9As shown, the through hole bar 22 is wavy, and the wavy through hole bar 22 also forms a first groove 224 and a second groove 225 with openings facing opposite directions, and the through hole 21 is disposed in the first groove 224. In another embodiment, the through hole 21 can also be disposed in the second groove 225, or in both the first groove 224 and the second groove 225.

[0051] Fig.10 1 is a top view of a chip sealing ring structure provided by an embodiment of the present invention. The shape of the first sealing ring 1 can be square, please refer to Figure 2 The shape of the first sealing ring 1 can also be octagonal, please refer to Fig.10 In other embodiments, the first sealing ring 1 may also be in other shapes known to those skilled in the art.

[0052] When the first sealing ring 1 is octagonal or in other shapes, the shape of the via bar 22 can be Figure 3 , Figures 5 to 9 Of course, it can also be any other curve shape.

[0053] Fig.11 This is a top view of a chip sealing ring structure provided by an embodiment of the present invention. Fig.11 As shown, the chip sealing ring structure includes a first sealing ring 1 arranged around a chip integrated circuit region 2, and a second sealing ring 3 arranged around the first sealing ring 1. The first sealing ring 1 and the second sealing ring 3 can be square, octagonal or other known shapes. The via bar 22 in the first sealing ring 1 can be any of the curved shapes in the above embodiments.

[0054] Fig.12 This is a partial top view of a chip sealing ring structure provided by an embodiment of the utility model. Fig.12 yes Fig.11 Please refer to the enlarged view of the dotted line frame. Fig.12 As shown, the second sealing ring 3 includes a dielectric layer 20 stacked in multiple layers, and a metal layer arranged in the dielectric layer 20 and flush with the dielectric layer 20, and a through-hole bar 22 filled with conductive material is arranged in the dielectric layer 20 to achieve connection between the metal layers, wherein the through-hole bar 22 is curved.

[0055] In this embodiment, the through hole 21 may not be provided in the groove formed by the through hole bar 22, and the through hole bar 22 may be any shape in the above embodiments. In another embodiment, in the second sealing ring 3, the through hole bar 22 and the through hole 21 filled with conductive material may also be provided in the dielectric layer 20 to achieve connection between the metal layers 30, and the shape of the through hole bar 22 and the positional relationship between the through hole bar 22 and the through hole 21 may be any one of the above embodiments.

[0056] The shapes of the via bars 22 in the first sealing ring 1 and the second sealing ring may be the same or different. The shapes of the via bars 22 in the first sealing ring 1 or the second sealing ring 3 but in different dielectric layers 20 may be the same or different.

[0057] Please refer to Figure 4 As shown, it should be noted that a metal plug 11 is formed in the bottom dielectric layer 20 (the dielectric layer at the bottom) to connect the bottom metal layer 30 (the metal layer at the bottom) with the device in the substrate 10, and through-hole bars 22 and through-holes 21 filled with conductive materials are formed in the remaining dielectric layers 20 to achieve connection between each metal layer 30.

[0058] In summary, the chip sealing ring structure provided by the utility model includes a first sealing ring arranged around the chip integrated circuit area, the first sealing ring includes a dielectric layer stacked in multiple layers, and a metal layer arranged in the dielectric layer and flush with the dielectric layer, and a through-hole bar and a through-hole filled with a conductive material are arranged in the dielectric layer to achieve connection between each metal layer, wherein the through-hole bar is curved, and compared with a straight through-hole bar, the curved through-hole bar can better resist the stress applied to the chip when the chip is cut, thereby avoiding the interface between the through-hole bar and the metal layer from being broken when the chip is cut, that is, avoiding the fracture at the sealing ring when the chip is cut, thereby avoiding the phenomenon of delamination and fracture of the chip, and improving the cutting yield.

[0059] Furthermore, the curved via bar forms a plurality of grooves, and the through holes are arranged in the grooves, thereby preventing the via bar from being broken due to stress changes, and further improving the cutting yield.

[0060] The above description is only a description of the preferred embodiment of the utility model, and is not any limitation on the scope of rights of the utility model. Any technical personnel in this field can make possible changes and modifications to the technical solution of the utility model by using the methods and technical contents disclosed above without departing from the spirit and scope of the utility model. Therefore, any simple modifications, equivalent changes and modifications made to the above embodiments based on the technical essence of the utility model without departing from the content of the technical solution of the utility model are within the protection scope of the technical solution of the utility model.

Claims

1. A chip sealing ring structure, comprising a first sealing ring arranged around a chip integrated circuit region, characterized in that: The first sealing ring includes a dielectric layer stacked in multiple layers, and a metal layer arranged in the dielectric layer and flush with the dielectric layer, wherein via bars and through holes filled with conductive materials are arranged in the dielectric layer to achieve connection between the metal layers, wherein the via bars are curved.

2. The chip sealing ring structure according to claim 1, characterized in that: The curved through-hole bar forms a plurality of grooves, and the through holes are arranged in the grooves.

3. The chip sealing ring structure according to claim 2, characterized in that: The through-hole bars include a plurality of linear first through-hole bars extending along a first direction, a plurality of linear second through-hole bars extending along a second direction, and a plurality of third through-hole bars extending along a third direction. The extension lines of the plurality of first through-hole bars constitute two parallel lines along the first direction. The second through-hole bar and the third through-hole bar are located between the two parallel lines and are connected with the first through-hole bar to form a first groove and a second groove with openings facing opposite directions. The through hole is located in the first groove and / or the second groove.

4. The chip sealing ring structure according to claim 3, characterized in that: The included angle between the second direction and the first direction is equal to the included angle between the third direction and the first direction, and the cross-sections of the first groove and the second groove are isosceles trapezoids.

5. The chip sealing ring structure according to claim 4, characterized in that: The bottom surface size of the first groove is not equal to the bottom surface size of the second groove.

6. The chip sealing ring structure according to claim 3, characterized in that: The second direction is parallel to the third direction, and the first direction is perpendicular to the second direction. The cross-sections of the first groove and the second groove are rectangular or square.

7. The chip sealing ring structure according to claim 6, characterized in that: The adjacent through-hole bars are arranged axially symmetrically, and the through holes are located in the first groove and / or the second groove.

8. The chip sealing ring structure according to claim 6, characterized in that: The adjacent through-hole bars are arranged axially symmetrically, and the openings of the first grooves and the second grooves of two adjacent through-hole bars form a third groove opposite to each other, and the through hole is located in the third groove.

9. The chip sealing ring structure according to claim 1, characterized in that: The via bar is in the form of a wavy line.

10. The chip sealing ring structure according to claim 1, characterized in that: The chip sealing ring structure also includes a second sealing ring arranged around the first sealing ring, the second sealing ring includes a dielectric layer stacked in multiple layers, and a metal layer arranged in the dielectric layer and flush with the dielectric layer, and a through-hole bar filled with conductive material is arranged in the dielectric layer to achieve connection between each metal layer, wherein the through-hole bar is curved.

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