Chip packaging structure and chip module

Abstract

The utility model discloses a chip packaging structure and a chip module, and the structure comprises a lower layer frame which comprises a lower layer bearing surface and a plurality of first pins, and the lower layer bearing surface is provided with a plurality of first connection points; the lower layer chip is arranged on the lower layer bearing surface and is bonded with the first connecting point; the upper-layer frame is arranged on the lower-layer chip, and the upper-layer frame comprises a lower-layer connecting surface, an upper-layer bearing surface and a plurality of second pins; a plurality of second connecting points are arranged on the lower-layer connecting surface, and one surface, far away from the lower-layer bearing surface, of the lower-layer chip is bonded with the second connecting points; a plurality of third connecting points are arranged on the upper bearing surface; and the upper-layer chip is arranged on the upper-layer bearing surface and is bonded with the third connecting point. According to the invention, the problems of large loss in a signal transmission process and complex whole processing flow caused by increase of parasitic and connection loss due to long lead connection during chip packaging in the prior art are solved.

Description

Technical Field

[0001] The present application relates to the field of chip packaging technology, and in particular to a chip packaging structure and a chip module. Background Art

[0002] There are multiple packaging forms in chip packaging. Currently, the more commonly used packaging form is to connect the chip to the pins through copper wires or copper sheets. This connection method makes the lead connection longer, increases parasitic and connection losses, causes greater losses during signal transmission, and the entire processing flow is more complicated. Utility Model Content

[0003] The main purpose of the present application is to provide a chip packaging structure and a chip module to solve the problem in the related art that the lead connection is long during chip packaging, which increases parasitic and connection losses, leads to large losses during signal transmission, and the entire processing flow is relatively complicated.

[0004] In order to achieve the above objectives, the present application provides a chip packaging structure, including:

[0005] A lower frame, comprising a lower bearing surface and a plurality of first pins, wherein a plurality of first connection points are arranged on the lower bearing surface;

[0006] A lower chip is disposed on the lower bearing surface and bonded to the first connection point, so that a part of the signal channel of the lower chip is connected to the first pin;

[0007] An upper frame is arranged on the lower chip, and the upper frame comprises a lower connection surface, an upper bearing surface and a plurality of second pins;

[0008] A plurality of second connection points are arranged on the lower connection surface, and a side of the lower chip away from the lower bearing surface is bonded to the second connection points, so that part of the signal channel of the lower chip is connected to part of the second pins; a plurality of third connection points are arranged on the upper bearing surface;

[0009] An upper chip is disposed on the upper bearing surface and bonded to the third connection point, so that a signal channel of the upper chip is connected to a portion of the second pins.

[0010] Furthermore, it also includes a plastic package, which packages the lower frame, the lower chip, the upper frame and the upper chip as a whole.

[0011] Furthermore, the plastic package is exposed on a side of the upper chip away from the upper bearing surface.

[0012] Furthermore, one end of the second pin away from the upper bearing surface extends to be in the same plane as the second pin.

[0013] Furthermore, the second pin includes an inner pin, an outer pin and a bending portion, and the inner pin and the outer pin are connected through the bending portion so that the outer pin extends to be in the same plane as the first pin;

[0014] The inner pins and the outer pins are arranged horizontally.

[0015] Furthermore, the first connection point, the second connection point and the third connection point are all tin connection points.

[0016] Furthermore, at least one of the plurality of the first pins is used for outputting a large current signal, and at least one of the first pins is used for outputting a ground signal.

[0017] Further, the lower chip is set as a MOS chip, the lower chip includes an upper signal channel and a lower signal channel, and the lower signal channel is connected to the corresponding first pin through the first connection point;

[0018] Some of the second pins among the plurality of second pins correspond to the upper signal channel and are connected to the upper signal channel through the second connection point.

[0019] Furthermore, the upper chip is configured as an integrated chip of a driver and a MOSFET, and some of the second pins among the plurality of the second pins correspond to signal channels of the upper chip and are connected to the corresponding signal channels through the third connection points.

[0020] According to another aspect of the present application, a chip module is provided, comprising the above-mentioned chip packaging structure.

[0021] In the embodiment of the present application, a lower frame is provided, including a lower bearing surface and a plurality of first pins, and a plurality of first connection points are provided on the lower bearing surface; a lower chip is provided on the lower bearing surface and bonded to the first connection points, so that part of the signal path of the lower chip is connected to the first pins; an upper frame is provided on the lower chip, and the upper frame includes a lower connection surface, an upper bearing surface and a plurality of second pins; a plurality of second connection points are provided on the lower connection surface, and a side of the lower chip away from the lower bearing surface is bonded to the second connection points, so that part of the signal path of the lower chip is connected to part of the second pins; a plurality of third connection points are provided on the upper bearing surface; and the upper chip is provided on the upper layer. The support surface is bonded to the third connection point so that the signal channel of the upper chip is connected to part of the second pin, so that the lower chip and the upper frame, and the upper frame are all fusion-welded and bonded through the corresponding connection points, and the upper chip and the upper frame are also fusion-welded and bonded through the corresponding connection points, so that the connection between the pins on the frame and the chip is as short as possible, thereby achieving the technical effect of making the chip packaging simpler and easier to implement, and after shortening the connection, it is easy to reduce parasitic and connection losses, thereby solving the problem in the related technology that the lead connection is long during chip packaging, which increases parasitic and connection losses, resulting in large losses during signal transmission and the entire processing flow is relatively complicated. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] The drawings constituting a part of this application are used to provide a further understanding of this application, so that other features, purposes and advantages of this application become more obvious. The schematic embodiment drawings and their descriptions of this application are used to explain this application and do not constitute an improper limitation on this application. In the drawings:

[0023] Figure 1 is a schematic diagram of a packaging structure according to an embodiment of the present application;

[0024] Figure 2 This is a schematic diagram of the structure after being packaged with a plastic package according to an embodiment of the present application;

[0025] Figure 3 It is a schematic diagram of an exploded structure encapsulated by a plastic package according to an embodiment of the present application;

[0026] Figure 4 is a schematic diagram of a top view of the structure of the lower frame according to an embodiment of the present application;

[0027] Figure 5 is a schematic diagram of the side structure of the lower frame according to an embodiment of the present application;

[0028] Figure 6 is a schematic diagram of a side view structure in which a lower chip is connected to a lower frame according to an embodiment of the present application;

[0029] Figure 7is a schematic diagram of a top view of a structure in which a lower chip is connected to a lower frame according to an embodiment of the present application;

[0030] Figure 8 is a schematic diagram of a top view of the structure of an upper frame according to an embodiment of the present application;

[0031] Fig. 9 is a schematic diagram of the side structure of the upper frame according to an embodiment of the present application;

[0032] Fig.10 is a schematic diagram of a side view structure of the connection between the upper frame and the lower chip according to an embodiment of the present application;

[0033] Fig.11 is a schematic diagram of a top view of the structure of the connection between the upper frame and the lower chip according to an embodiment of the present application;

[0034] Fig.12 is a schematic diagram of a side view structure of the connection between the upper frame and the upper chip according to an embodiment of the present application;

[0035] Fig.13 It is a schematic diagram of the top view structure of the connection between the upper frame and the upper chip in an embodiment of the present application.

[0036] Among them, 1 is a lower frame, 101 is a lower bearing surface, 2 is a first connection point, 3 is a first pin, 4 is a lower chip, 5 is an upper frame, 501 is an upper bearing surface, 502 is a lower connection surface, 6 is a third connection point, 7 is a second pin, 701 is an inner pin, 702 is a bending part, 703 is an outer pin, 8 is a second connection point, 9 is an upper chip, and 10 is a plastic package. DETAILED DESCRIPTION

[0037] In order to enable those skilled in the art to better understand the solution of the present application, the technical solution in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of the present application.

[0038] It should be noted that the terms "first", "second", etc. in the specification and claims of the present application and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the numbers used in this way can be interchanged where appropriate, so as to describe the embodiments of the present application described herein.

[0039] In this application, the terms "upper", "lower", "inner", etc. indicate positions or positional relationships based on the positions or positional relationships shown in the drawings. These terms are mainly used to better describe the present application and its embodiments, and are not used to limit the indicated devices, elements or components to have a specific orientation, or to be constructed and operated in a specific orientation.

[0040] In addition, some of the above terms may be used to express other meanings in addition to indicating orientation or positional relationship. For example, the term "on" may also be used to express a certain dependency or connection relationship in some cases. For those of ordinary skill in the art, the specific meanings of these terms in this application can be understood according to specific circumstances.

[0041] In addition, the terms "disposed", "provided with", "connected", "fixed" and the like should be understood in a broad sense. For example, "connected" can be a fixed connection, a detachable connection, or an integral structure; it can be a mechanical connection, or an electrical connection; it can be a direct connection, or an indirect connection through an intermediate medium, or it can be an internal connection between two devices, elements or components. For those of ordinary skill in the art, the specific meanings of the above terms in this application can be understood according to the specific circumstances.

[0042] In addition, the term "plurality" shall mean two or more.

[0043] It should be noted that, in the absence of conflict, the embodiments and features in the embodiments of the present application can be combined with each other. The present application will be described in detail below with reference to the accompanying drawings and in combination with the embodiments.

[0044] There are multiple packaging forms in the chip packaging. Currently, the more commonly used packaging form is to connect the chip and the pin through copper wire or copper sheet. Taking MOSFET chip packaging as an example, the chip is fixed on the base island with adhesive material (conductive glue or solder paste) so that the drain of the MOSFET chip is connected to the base island, and then a bonding machine is used to perform bonding operations, and the source area of ​​the MOSFET chip is connected to the source pin through copper wire or copper sheet, and the gate area of ​​the MOSFET chip is connected to the gate pin, and then after plastic sealing, electroplating and singulation processes, a single package structure is formed.

[0045] Obviously, this connection method makes the lead connection longer, increases parasitic and connection losses, leads to greater losses during signal transmission, and the entire processing flow is more complicated.

[0046] To solve the above technical problems, Figures 1 to 13 As shown, an embodiment of the present application provides a chip packaging structure, including:

[0047] The lower frame 1 comprises a lower bearing surface 101 and a plurality of first pins 3, and a plurality of first connection points 2 are arranged on the lower bearing surface 101;

[0048] The lower chip 4 is disposed on the lower bearing surface 101 and bonded to the first connection point 2, so that part of the signal channel of the lower chip 4 is connected to the first pin 3;

[0049] The upper frame 5 is arranged on the lower chip 4, and the upper frame 5 comprises a lower connection surface 502, an upper bearing surface 501 and a plurality of second pins 7;

[0050] A plurality of second connection points 8 are arranged on the lower connection surface 502, and a surface of the lower chip 4 away from the lower bearing surface 101 is bonded to the second connection point 8, so that part of the signal channel of the lower chip 4 is connected to part of the second pins 7; a plurality of third connection points 6 are arranged on the upper bearing surface 501;

[0051] The upper chip 9 is disposed on the upper bearing surface 501 and bonded to the third connection point 6 , so that the signal channel of the upper chip 9 is connected to part of the second pins 7 .

[0052] In this embodiment, the chip packaging structure includes an upper chip 9 and a lower chip 4 stacked up and down, and accordingly has a lower frame 1 corresponding to the lower chip 4, and an upper frame 5 corresponding to the upper chip 9. In this embodiment, the upper frame 5 and the lower frame 1 are both lead metal frames, and their specific structures and pin distributions need to be designed according to the signal channels corresponding to the lower chip 4 and the upper chip 9. According to the conventional chip structure, the upper frame 5 and the lower frame 1 both include at least one base island and a number of pins (i.e., the first pins 3) distributed around the base island, and some of the pins are disconnected from the base island.

[0053] like Figures 4 to 7 As shown, the lower frame 1 is used as the bottom structure, and its upper surface has a lower bearing surface 101, which is a relatively flat plane. The lower bearing surface 101 includes the upper surface of the base island in the lower frame 1 and the upper surface of some pins. A plurality of first connection points 2 are distributed on the lower bearing surface 101, and the lower chip 4 is arranged on the lower bearing surface 101 and is welded and bonded to the first connection points 2, so that some signal channels in the lower chip 4 can be connected to the first pins 3.

[0054] like Figures 8 to 13 As shown, the upper frame 5 is located above the lower frame 1, and its upper surface has an upper bearing surface 501, and its lower surface has a lower connection surface 502. The upper frame 5, as a lead metal frame, also includes a base island and pins (i.e., second pins 7) distributed around the base island, and some pins are also disconnected from the base island. Fig. 9As shown, in this embodiment, both the upper bearing surface 501 and the lower connection surface 502 are flat surfaces. The lower connection surface 502 needs to be connected to the upper surface of the lower chip 4. Accordingly, a plurality of second connection points 8 are arranged on the lower connection surface 502. The upper surface of the lower chip 4 is welded and bonded to the second connection points 8, so that part of the signal channels in the lower chip 4 can be connected to part of the second pins 7. In one embodiment, the second connection points 8 are only arranged on the lower surface of the base island of the upper frame 5, that is, the upper surface of the lower chip 4 is only connected to the base island portion of the upper frame 5.

[0055] The upper bearing surface 501 in the upper frame 5 is used to arrange the upper chip 9, and the upper bearing surface 501 includes the upper surface of the base island in the upper frame 5 and the upper surface of some pins. A plurality of third connection points 6 are distributed on the upper bearing surface 501, and the lower surface of the upper chip 9 is welded and bonded to the third connection points 6, so that some signal channels in the upper chip 9 can be connected to some second pins 7.

[0056] This embodiment achieves the purpose of making the lower chip 4 and the upper frame 5, and the upper frame 5 are all welded and bonded through corresponding connection points, and the upper chip 9 and the upper frame 5 are also welded and bonded through corresponding connection points, so that the connection between the pins on the frame and the chip is as short as possible, thereby achieving the technical effect of making the chip packaging simpler and easier to implement, and after shortening the connection, it is easy to reduce parasitic and connection losses, thereby solving the problem in the related art that the lead connection is long during chip packaging, which increases parasitic and connection losses, resulting in large losses during signal transmission and a relatively complicated entire processing flow.

[0057] To facilitate packaging, the first connection point 2, the second connection point 8 and the third connection point 6 are all tin connection points. It is understandable that the first connection point 2, the second connection point 8 and the third connection point 6 can also be made of other conductive materials that can meet the fusion welding process, and the description of this embodiment here is not restrictive.

[0058] To realize the overall packaging of the upper and lower frames 1 and the upper and lower chips 4, as shown in FIG. Figure 2 and Figure 3 As shown, the packaging structure in this embodiment further includes a plastic packaging member 10, and the plastic packaging member 10 integrally packages the lower frame 1, the lower chip 4, the upper frame 5 and the upper chip 9 together.

[0059] In this embodiment, the upper chip 9 is a flip chip, the upper surface of which is a flat surface and does not need to be connected to other devices. Therefore, in order to facilitate the heat dissipation of the chip, Figure 2 As shown, in this embodiment, the plastic package 10 is exposed on the side of the upper chip 9 away from the upper bearing surface 501, so that it can be easily connected to the heat sink to improve the heat dissipation effect.

[0060] Since the upper frame 5 and the lower frame 1 are arranged vertically in this embodiment, in order to facilitate the processing of the upper pins and the lower pins during the plastic packaging process, as shown in FIG. Figures 1 to 3 As shown, in this embodiment, the end of the second pin 7 away from the upper bearing surface 501 extends to be in the same plane as the first pin 3. In a specific embodiment, as Fig. 9 As shown, the second pin 7 includes an inner pin 701, an outer pin 703 and a bending portion 702, and the inner pin 701 and the outer pin 703 are connected through the bending portion 702 so that the outer pin 703 extends to be in the same plane as the first pin.

[0061] Specifically, it should be noted that, in this embodiment, the inner pin 701 and the outer pin 703 of the second pin 7 are both arranged in the horizontal direction, and the bending portion 702 is arranged in an inclined outward direction, so that the outer pin 703 is lower in height than the inner pin 701, so that it can extend to the same plane as the end of the first pin 3, thereby facilitating subsequent processing.

[0062] In an implementation manner of the lower frame 1 , at least one first pin 3 among the plurality of first pins 3 on the lower frame 1 is used for high current signal output, and at least one first pin 3 is used for ground signal output.

[0063] In one embodiment of the lower chip 4, the lower chip 4 is configured as a simple MOS chip, and the lower chip includes an upper signal channel and a lower signal channel, and the lower signal channel is connected to the corresponding first pin 3 through the first connection point 2;

[0064] Some of the second pins 7 among the plurality of second pins 7 correspond to the upper layer signal channel and are connected to the upper layer signal channel through the second connection point 8 .

[0065] In this embodiment, the upper signal channel is only for high current output, and the lower signal channel is for high current signal and ground signal channel.

[0066] In one embodiment of the upper chip 9, the upper chip 9 is configured as an integrated chip of a driver and a Mosfet, and some of the second pins 7 correspond to signal channels of the upper chip 9 and are connected to the corresponding signal channels through the third connection point 6.

[0067] Specifically, the upper chip 9 is an integrated chip of a driver and a MOSFET using a Filp planar process, which needs to lead out ten separate control signals, as well as a high current signal and a ground signal. Correspondingly, ten control signals, as well as a power supply and a ground signal need to be led out through the second pin 7 in the upper frame 5.

[0068] When preparing the lower frame 1 and the upper frame 5, the lower frame 1 can be processed by etching, and the first connection point 2 can be made by steel screen printing. The upper frame 5 can be processed by etching and stamping, and the second connection point 8 can also be made by steel screen printing. After the upper frame 5 is stamped, the flatness of the lower connection surface 502 and the upper bearing surface 501 needs to be ensured. When assembling the packaging structure in this application, the lower chip 4 can be first welded on the lower bearing surface 101 of the lower frame 1 and reflowed, and then the upper frame 5 can be welded by the lower connection surface and reflowed, and then the upper chip 9 can be welded on the upper bearing surface 501 of the upper frame 5 and then returned, and finally the whole is plastic-sealed, and the upper surface of the upper chip 9 is exposed during plastic sealing, and finally cut and formed.

[0069] According to another aspect of the present application, a chip module is provided, comprising the above-mentioned chip packaging structure.

[0070] The above description is only the preferred embodiment of the present application and is not intended to limit the present application. For those skilled in the art, the present application may have various modifications and variations. Within the spirit and principle of the present application, any modification, equivalent replacement, improvement, etc. made shall be included in the protection scope of the present application.

Claims

1. A chip packaging structure, characterized in that: include: A lower frame, comprising a lower bearing surface and a plurality of first pins, wherein a plurality of first connection points are arranged on the lower bearing surface; A lower chip is disposed on the lower bearing surface and bonded to the first connection point, so that a part of the signal channel of the lower chip is connected to the first pin; An upper frame is arranged on the lower chip, and the upper frame comprises a lower connection surface, an upper bearing surface and a plurality of second pins; A plurality of second connection points are arranged on the lower connection surface, and a side of the lower chip away from the lower bearing surface is bonded to the second connection points, so that part of the signal channel of the lower chip is connected to part of the second pins; a plurality of third connection points are arranged on the upper bearing surface; An upper chip is disposed on the upper bearing surface and bonded to the third connection point, so that a signal channel of the upper chip is connected to a portion of the second pins.

2. The chip packaging structure according to claim 1, characterized in that: It also includes a plastic package, which packages the lower frame, the lower chip, the upper frame and the upper chip as a whole.

3. The chip packaging structure according to claim 2, characterized in that: The plastic package is exposed on a side of the upper chip away from the upper bearing surface.

4. The chip packaging structure according to claim 1, characterized in that: One end of the second pin away from the upper bearing surface extends to be in the same plane as the second pin.

5. The chip packaging structure according to claim 4, characterized in that: The second pin comprises an inner pin, an outer pin and a bending portion, wherein the inner pin and the outer pin are connected via the bending portion so that the outer pin extends to be in the same plane as the first pin; The inner pins and the outer pins are arranged horizontally.

6. The chip packaging structure according to claim 5, characterized in that: The first connection point, the second connection point and the third connection point are all solder connection points.

7. The chip packaging structure according to claim 1, characterized in that: At least one of the plurality of first pins is used for outputting a large current signal, and at least one of the first pins is used for outputting a ground signal.

8. The chip packaging structure according to claim 7, characterized in that: The lower chip is set as a MOS chip, the lower chip includes an upper signal channel and a lower signal channel, and the lower signal channel is connected to the corresponding first pin through the first connection point; Some of the second pins among the plurality of second pins correspond to the upper signal channel and are connected to the upper signal channel through the second connection point.

9. The chip packaging structure according to claim 1, characterized in that: The upper chip is configured as an integrated chip of a driver and a MOSFET, and some of the second pins correspond to signal channels of the upper chip and are connected to the corresponding signal channels through the third connection points.

10. A chip module, characterized in that: The invention comprises a chip packaging structure as claimed in any one of claims 1 to 9.

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