Light emitting diode with vertical structure

Abstract

The utility model provides a light-emitting diode with a vertical structure, which comprises an epitaxial layer at least comprising a first semiconductor layer, a light-emitting layer and a second semiconductor layer which are sequentially stacked from top to bottom, and the epitaxial layer comprises a first surface and a second surface which are opposite to each other; the at least one first hole penetrates through the second semiconductor layer and the light-emitting layer and exposes the first semiconductor layer; and a boss located on the first surface of the epitaxial layer, wherein the projection of the boss on the first semiconductor layer covers the bottom of the first opening. The boss is arranged on the epitaxial layer above the first hole to compensate the thickness difference of the epitaxial layer in different areas, so that the problems of epitaxial defect aggravation caused by the film thickness difference of the epitaxial layer and epitaxial layer defect aggravation caused by thermal stress and heat conduction are reduced, and the reliability of the light-emitting diode is improved. Meanwhile, the thickness of the epitaxial layer is obviously reduced compared with the total thickness of the epitaxial layer growing on the heterogeneous substrate, so that the absorption of emergent light is reduced, and the brightness of the light-emitting diode is further improved.

Description

Technical Field

[0001] The utility model relates to the technical field of semiconductor manufacturing, in particular to a vertical structure light emitting diode. Background Art

[0002] With the in-depth expansion of light emitting diodes (LEDs) in application fields such as stage lights, projectors, and automotive lighting, the pursuit of single-chip ultra-large current density and higher brightness has become the most cutting-edge technology development direction for high-performance vertical structure light emitting diodes. However, with the continuous increase in current density, the reliability of high-performance light emitting diodes has brought more severe technical challenges.

[0003] LEDs with internal ultra-high reflectivity ODR structures and surface high-transmittance dielectric films have become the most important technical improvement solution. Although the extreme pursuit of reflection and light extraction can only improve optical performance, the complex film design scheme has a more prominent impact on the reliability of LEDs, especially the failure caused by stress matching between film layers and heat conduction in LEDs. Stress mismatch and poor heat conduction will cause irreversible defects in the epitaxial materials of LEDs, and their ability to maintain photoelectric performance will be weakened. Since LEDs need to etch steps or through-hole structures in the epitaxial layer, the height difference ranges from about 700nm to 1500nm. For vertical structure LEDs, the difference in film thickness in this area will produce more significant current density differences and stress concentration, becoming a weak point in the LED.

[0004] On the other hand, due to the large difference in refractive index between GaN and air, although it can be improved by using a single layer of SiO2 with a refractive index between GaN and air, a better light-emitting surface transmission effect has not yet been achieved. Therefore, the pursuit of ultimate light extraction and reduction of light absorption has become one of the key technical issues at present. Utility Model Content

[0005] The utility model aims to provide a vertical structure light emitting diode, which can improve the brightness and reliability of the vertical structure light emitting diode under ultra-large current density without affecting its photoelectric performance.

[0006] In order to solve the above technical problems, the utility model provides a vertical structure light emitting diode, comprising:

[0007] An epitaxial layer, the epitaxial layer at least comprising a first semiconductor layer, a light-emitting layer and a second semiconductor layer stacked in sequence from top to bottom, the epitaxial layer comprising a first surface and a second surface opposite to each other, the second surface of the epitaxial layer being a side surface of the second semiconductor layer away from the light-emitting layer;

[0008] at least one first opening, wherein the first opening penetrates the second semiconductor layer and the light emitting layer and exposes the first semiconductor layer;

[0009] A boss is located on the first surface of the epitaxial layer, wherein a projection of the boss on the first semiconductor layer covers a bottom of the first opening, and the bottom of the first opening is a surface close to one side of the first semiconductor layer.

[0010] Optionally, a projection of the boss on the first semiconductor layer does not exceed twice the size of an opening of the first opening, and the opening of the first opening is an opening of the first opening on the second surface of the epitaxial layer.

[0011] Optionally, the thickness d1 of the boss is 50% to 120% of the depth d4 of the first opening, wherein the depth of the first opening is the distance from the second surface of the epitaxial layer to the bottom of the first opening.

[0012] Optionally, the thickness from the bottom of the first opening to the surface of the boss is a first thickness d5, the total thickness of the first semiconductor layer, the light-emitting layer and the second semiconductor layer is a second thickness d2, and the first thickness d5 is 50% to 100% of the second thickness d2.

[0013] Optionally, the first thickness d5 is ±10% of the depth d4 of the first opening.

[0014] Optionally, the thickness of the boss is in the range of 0.35 μm to 1.8 μm.

[0015] Optionally, a plurality of the first opening arrays are arranged in the epitaxial layer.

[0016] Optionally, the first opening includes a through hole and / or a groove.

[0017] Optionally, the first surface is a surface of the first semiconductor layer, and the boss is located on the first semiconductor layer.

[0018] Optionally, the epitaxial layer further includes a first ohmic contact layer located on the first semiconductor layer, the first surface is a surface of the first ohmic contact layer, and the boss is located on the first ohmic contact layer.

[0019] Optionally, the epitaxial layer further includes a first ohmic contact layer and an unintentional doping layer stacked in sequence from bottom to top on the first semiconductor layer, the first surface is the surface of the unintentional doping layer, and the boss is located on the unintentional doping layer.

[0020] Optionally, the boss is an unintentionally doped layer.

[0021] Optionally, the boss is a first ohmic contact layer and an unintentionally doped layer stacked in sequence from bottom to top.

[0022] Optionally, the vertical structure light emitting diode further includes:

[0023] A second ohmic contact layer, wherein the second ohmic contact layer is located on a surface of a portion of the second semiconductor layer away from the first semiconductor layer;

[0024] an insulating reflective layer, wherein the insulating reflective layer covers the second ohmic contact layer and the second semiconductor layer, and covers a side wall of the first opening;

[0025] a plurality of second openings, wherein the second openings penetrate the insulating reflective layer and expose a portion of the second ohmic contact layer;

[0026] a metal reflective layer, the metal reflective layer being located on a surface of a portion of the insulating reflective layer away from the second semiconductor layer and covering at least a sidewall and a bottom of the second opening; and

[0027] a second current spreading layer, the second current spreading layer being located on a surface of the metal reflective layer away from the epitaxial layer;

[0028] an isolation dielectric layer, the isolation dielectric layer covering the metal reflection layer, the second current spreading layer and the insulating reflection layer, and covering the side wall of the first opening;

[0029] A first current spreading layer is located on a surface of the isolation dielectric layer away from the epitaxial layer and fills the first opening.

[0030] Optionally, the light emitting diode further includes:

[0031] A bonding layer, located on a side of the first current spreading layer away from the isolation dielectric layer;

[0032] a substrate, located on a side of the bonding layer away from the first current spreading layer;

[0033] A first electrode, located on a side of the substrate away from the bonding layer;

[0034] a step, located at the periphery of the epitaxial layer, penetrating the epitaxial layer and the insulating reflective layer and exposing the second current spreading layer; and

[0035] The second electrode is located on the step and is electrically connected to the second current spreading layer.

[0036] Optionally, the vertical structure light emitting diode further comprises a composite structure passivation layer covering at least a portion of the surface of the epitaxial layer, and the refractive index of the composite structure passivation layer gradually decreases from the epitaxial layer to the air.

[0037] Optionally, the composite structure passivation layer covers the side walls of the epitaxial layer, the first surface of the epitaxial layer, and the side walls and top of the boss; or, the composite structure passivation layer covers the side walls of the epitaxial layer, the side walls and top of the boss; or, the composite structure passivation layer covers the side walls of the epitaxial layer, the side walls of the boss, and part of the epitaxial layer surface around the side walls of the boss and part of the top of the boss, and the coverage width of the part of the epitaxial layer surface and the part of the top of the boss is in the range of 5μm to 10μm.

[0038] Compared with the prior art, in the vertical structure light emitting diode provided by the utility model, the epitaxial layer at least includes a first semiconductor layer, a light emitting layer and a second semiconductor layer stacked in sequence from top to bottom, the epitaxial layer includes a first surface and a second surface opposite to each other, the second surface of the epitaxial layer is a side surface of the second semiconductor layer away from the light emitting layer, at least one first opening penetrating the second semiconductor layer and the light emitting layer and exposing the first semiconductor layer is formed in the epitaxial layer, a boss is formed on the first surface of the epitaxial layer, the projection of the boss on the first semiconductor layer covers the bottom of the first opening, and the bottom of the first opening is the surface close to the first semiconductor layer. The utility model provides a boss on the epitaxial layer above the first opening to compensate for the thickness difference of the epitaxial layer in different regions, reduces the problem of epitaxial defects aggravated due to the difference in the thickness of the epitaxial layer, and the problem of epitaxial defects aggravated due to thermal stress and heat conduction, and improves the reliability of the light emitting diode. At the same time, because the epitaxial layer includes the first semiconductor layer, the light emitting layer and the second semiconductor layer, the total thickness of the epitaxial layer of the vertical structure light emitting diode is significantly reduced compared with that grown on a foreign substrate, thereby reducing the absorption of the light output and further improving the brightness of the light emitting diode.

[0039] In addition, the light-emitting diode also includes a composite structure passivation layer covering the epitaxial layer. The refractive index of the composite structure passivation layer gradually decreases from the epitaxial layer to the air direction, so that it has higher light transmittance enhancement performance. At the same time, the electrical breakdown resistance and environmental resistance of the composite structure passivation layer are significantly improved, and finally a high-reliability and high-performance vertical structure light-emitting diode for ultra-large current density is realized. BRIEF DESCRIPTION OF THE DRAWINGS

[0040] Those skilled in the art will appreciate that the drawings are provided for a better understanding of the present invention and do not constitute any limitation on the scope of the present invention.

[0041] Figure 1It is a structural schematic diagram of a vertical structure light emitting diode provided in the first embodiment of the utility model.

[0042] Figures 2 to 15 It is a schematic structural diagram of each step of a method for manufacturing a vertical structure light emitting diode provided by an embodiment of the utility model.

[0043] Fig.16 It is a schematic diagram of the distribution of the first openings in the epitaxial layer provided in one embodiment of the utility model.

[0044] Description of reference numerals:

[0045] 100-first substrate; 200-epitaxial layer; 200a-first opening; 200b-step; 210-buffer layer; 220-unintentionally doped layer; 230-first semiconductor layer; 240-light-emitting layer; 250-second semiconductor layer; 260-boss; 310-second ohmic contact layer; 320-insulating reflective layer; 320a-second opening; 330-metal reflective layer; 340-second current spreading layer; 350-isolating dielectric layer; 350a-through hole; 360-first current spreading layer; 400-second substrate; 410-bonding layer; 500-composite structure passivation layer; 610-second electrode; 620-first electrode. DETAILED DESCRIPTION

[0046] In order to make the purpose, advantages and features of the utility model clearer, the utility model is further described in detail below in conjunction with the accompanying drawings and specific embodiments. It should be noted that the drawings are all in a very simplified form and are not drawn to scale, and are only used to conveniently and clearly assist in explaining the purpose of the embodiments of the utility model. In addition, the structure shown in the drawings is often a part of the actual structure. In particular, the emphasis of each drawing is different, and sometimes different scales are used.

[0047] As used in the present invention, the singular forms "one", "an", and "the" include plural objects, unless the content clearly indicates otherwise. As used in the present invention, the term "or" is generally used in a sense that includes "and / or", unless the content clearly indicates otherwise. As used in the present invention, the term "several" is generally used in a sense that includes "at least one", unless the content clearly indicates otherwise. As used in the present invention, the term "at least two" is generally used in a sense that includes "two or more", unless the content clearly indicates otherwise. In addition, the terms "first", "second", and "third" are used only for descriptive purposes and cannot be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Therefore, the features defined as "first", "second", and "third" may explicitly or implicitly include one or at least two of the features.

[0048] Figure 1 It is a structural schematic diagram of a vertical structure light emitting diode provided in the first embodiment of the utility model.

[0049] Please refer to Figure 1 As shown, the vertical structure light emitting diode comprises:

[0050] An epitaxial layer 200, wherein the epitaxial layer 200 at least comprises a first semiconductor layer 230, a light emitting layer 240 and a second semiconductor layer 250 stacked in sequence from top to bottom, wherein the epitaxial layer 200 comprises a first surface S1 and a second surface S2 opposite to each other, wherein the second surface S2 of the epitaxial layer 200 is a side surface of the second semiconductor layer 250 away from the light emitting layer 240;

[0051] at least one first opening 200 a , wherein the first opening 200 a penetrates the second semiconductor layer 250 and the light emitting layer 240 and exposes the first semiconductor layer 230 ;

[0052] The projection 260 is located on the first surface S1 of the epitaxial layer 200 , and the projection of the projection 260 on the first semiconductor layer 230 covers the bottom of the first opening 200 a . The bottom of the first opening 200 a is a surface close to one side of the first semiconductor layer 230 .

[0053] In this embodiment, the boss 260 is provided on the epitaxial layer 200 above the first opening 200a to compensate for the thickness difference of the epitaxial layer 200 in different regions, reduce the problem of epitaxial defects aggravated due to the thickness difference of the epitaxial layer 200, and the problem of epitaxial layer defects aggravated due to thermal stress and heat conduction, and improve the reliability of the light-emitting diode. At the same time, since the epitaxial layer 200 includes the first semiconductor layer 230, the light-emitting layer 240 and the second semiconductor layer 250, the thickness of the epitaxial layer 200 of the vertical structure light-emitting diode is significantly reduced compared with the total thickness of the epitaxial layer 200 grown on the heterogeneous substrate, thereby reducing the absorption of the light, and further improving the brightness of the light-emitting diode.

[0054] The bottom of the first opening 200a (ie, the surface close to the first semiconductor layer 230) may be located at the interface between the light emitting layer 240 and the first semiconductor layer 230 (eg, Figure 1 As shown in FIG. 2 ), it may also extend into the first semiconductor layer 230 .

[0055] In one embodiment of the utility model, the projection size of the boss 260 on the first semiconductor layer 230 does not exceed twice the opening size of the first opening 200a, and the opening of the first opening 200a is the opening of the first opening 200a on the second surface S2 of the epitaxial layer 200.

[0056] Please refer to Figure 1 As shown, the thickness of the boss 260 is d1, the total thickness of the first semiconductor layer 230, the light emitting layer 240 and the second semiconductor layer 250 is d2, the thickness from the bottom of the first opening 200a to the first surface S1 of the epitaxial layer 200 is d3, the depth of the first opening 200a (that is, the distance from the second surface S2 of the epitaxial layer 200 to the bottom of the first opening 200a) is d4, and the thickness from the bottom of the first opening 200a to the surface of the boss 260 is d5.

[0057] In one embodiment of the utility model, the thickness d1 of the boss 260 is 50% to 120% of the depth d4 of the first opening 200a; the thickness d5 from the bottom of the first opening 200a to the surface of the boss 260 is set to a first thickness, and the total thickness d2 of the first semiconductor layer 230, the light-emitting layer 240 and the second semiconductor layer 250 is set to a second thickness, and the first thickness is 50% to 100% of the second thickness.

[0058] In an embodiment of the present invention, the first thickness d5 is ±10% of the depth d4 of the first opening 200a.

[0059] Exemplarily, the thickness d1 of the boss 260 is in the range of 0.35 μm to 1.8 μm, but is not limited thereto.

[0060] In one embodiment of the present invention, the first semiconductor layer 230 is an N-type semiconductor layer, and the second semiconductor layer 250 is a P-type semiconductor layer. The first semiconductor layer 230 is, for example, a heavily doped N-type GaN (gallium nitride) layer, the second semiconductor layer 250 is, for example, a P-type GaN layer, and the light-emitting layer 240 is a multi-quantum well layer (MQW), which can be a combination of any two of GaN / InGaN (indium gallium nitride) / AlGaN (aluminum gallium nitride), and the corresponding wavelength range is 360nm to 560nm, but is not limited thereto.

[0061] In one embodiment of the present invention, a plurality of first openings 200a are arranged in an array in the epitaxial layer 200. The first openings 200a may include through holes and / or grooves. Fig.16 As shown, the first opening 200a includes a through hole and a groove.

[0062] In one embodiment of the present utility model, please refer to Figure 1As shown, the epitaxial layer 200 includes a second semiconductor layer 250 , a light emitting layer 240 and the first semiconductor layer 230 stacked in sequence from bottom to top. The first surface S1 of the epitaxial layer 200 is the surface of the first semiconductor layer 230 , and the boss 260 is located on the first semiconductor layer 230 .

[0063] In another embodiment of the present invention, the epitaxial layer 200 further includes a first ohmic contact layer (not shown) located on the first semiconductor layer 230 , the first surface S1 is a surface of the first ohmic contact layer, and the boss 260 is located on the first ohmic contact layer.

[0064] In another embodiment of the present invention, the epitaxial layer 200 also includes a first ohmic contact layer and an unintentional doping layer (not shown) stacked in sequence from bottom to top on the first semiconductor layer 230, the first surface S1 is the surface of the unintentional doping layer, and the boss 260 is located on the unintentional doping layer.

[0065] In an embodiment of the present invention, when the first surface S1 is the surface of the first semiconductor layer 230 , the surface of the first ohmic contact layer, or the surface of the unintentionally doped layer, the boss 260 is an unintentionally doped layer.

[0066] In another embodiment of the present invention, when the first surface S1 is the surface of the first semiconductor layer 230 or the surface of the first ohmic contact layer, the boss 260 is a first ohmic contact layer and an unintentionally doped layer stacked sequentially from bottom to top.

[0067] In the above embodiment, the material of the unintentionally doped layer and the first ohmic contact layer may be GaN, but is not limited thereto.

[0068] Please continue to refer to Figure 1As shown, the vertical structure light emitting diode further includes: a second ohmic contact layer 310, the second ohmic contact layer 310 is located on a surface of a portion of the second semiconductor layer 250 away from the first semiconductor layer 230; an insulating reflective layer 320, the insulating reflective layer 320 covers the second ohmic contact layer 310 and the second semiconductor layer 250, and covers the sidewall of the first opening 200a; a plurality of second openings 320a, the second openings 320a penetrate the insulating reflective layer 320 and expose a portion of the second ohmic contact layer 310; a metal reflective layer 330, the metal reflective layer 330 is located on a surface of a portion of the insulating reflective layer 320 away from the second semiconductor layer 250, and At least covering the sidewalls and the bottom of the second opening 320a so as to contact the second ohmic contact layer 310; a second current spreading layer 340, the second current spreading layer 340 is located on the surface of the metal reflective layer 330 away from the epitaxial layer 200; an isolation dielectric layer 350, the isolation dielectric layer 350 covers the metal reflective layer 330, the second current spreading layer 340 and the insulating reflective layer 320, and covers the sidewalls of the first opening 200a; and a first current spreading layer 360, the first current spreading layer 360 is located on the surface of the isolation dielectric layer 350 away from the epitaxial layer 200 and fills the first opening 200a so as to contact the first semiconductor layer 230.

[0069] In this embodiment, the material of the second ohmic contact layer 310 is preferably a transparent conductive oxide, such as ITO (indium tin oxide), but not limited thereto. The insulating reflective layer 320 is a low refractive index dielectric reflective layer, and its material is preferably SiO2. The thickness of the insulating reflective layer 320 is k*λ / 4n (k is a positive integer, and n is the refractive index of the insulating reflective layer 320 corresponding to the light emission wavelength of the light emitting layer 240). For example, k=4, the refractive index corresponding to the wavelength of 460nm is about 1.47, and the corresponding film thickness is about 313nm. The metal reflective layer 330 can be a stack of Ag layer, Pt layer and Ti layer, and its thickness can be respectively as well as The isolation dielectric layer 350 includes a SiO2 layer, a silicon oxynitride layer, a SiN x The second current spreading layer 340 includes a stacked structure consisting of a Ti layer, an Au layer, a Pt layer and a Cr layer, and the thicknesses thereof can be respectively as well as The first current spreading layer 360 includes a stacked structure consisting of a Ti layer, an Al layer, a Pt layer and a Ti layer, and the thicknesses thereof can be as well as

[0070] Please continue to refer to Figure 1 As shown, the vertical structure light-emitting diode also includes: a bonding layer 410 and a second substrate 400, wherein the bonding layer 410 is located on a side of the first current spreading layer 360 away from the isolation dielectric layer 350, and the second substrate 410 is located on a side of the bonding layer 410 away from the first current spreading layer 360, that is, the bonding layer 410 is located between the first current spreading layer 360 and the second substrate 400; a first electrode 620, located on a side of the substrate 400 away from the bonding layer 410; a step 200b, located on the periphery of the epitaxial layer 200, penetrating the epitaxial layer 200 and the insulating reflective layer 330 and exposing the second current spreading layer 340; and a second electrode 610, located on the step 200b and electrically connected to the second current spreading layer 340.

[0071] In this embodiment, the second substrate 400 is a conductive substrate, such as a metal substrate or a silicon substrate, etc. The material of the second electrode 610 is preferably TiNiAu, and the material of the first electrode 620 is preferably TiPtAu.

[0072] Please continue to refer to Figure 1 As shown, the vertical structure light emitting diode also includes: a composite structure passivation layer 500 covering the epitaxial layer 200, and the refractive index of the composite structure passivation layer 500 gradually decreases from the epitaxial layer 200 to the air direction, so that it has higher light transmittance enhancement performance. At the same time, the composite structure passivation layer 500 adopts a high-k value transparent dielectric material, and its resistance to electrical breakdown and environmental resistance are significantly improved, ultimately realizing a high-reliability and high-performance vertical structure light emitting diode for ultra-large current density.

[0073] The composite structure passivation layer 500 includes an AlN layer, a SiN x At least three layers of the epitaxial layer 200 include, but are not limited to, a silicon oxynitride layer, an Al2O3 layer, a SiO2 layer, a MgF2 layer, and a silicon oxynitride layer. For example, the composite structure passivation layer 500 includes a stack of silicon oxynitride layers, an Al2O3 layer, and a SiO2 layer, wherein the silicon oxynitride layer is close to the epitaxial layer 200.

[0074] In one embodiment of the present utility model, please refer to Figure 1 As shown, the composite structure passivation layer 500 covers the sidewalls of the epitaxial layer 200 , the first surface S1 of the epitaxial layer 200 , and the sidewalls and top of the boss 260 .

[0075] In another embodiment of the present invention, please refer to Fig.14As shown, the composite structure passivation layer 500 covers the sidewalls of the epitaxial layer 200, the sidewalls of the boss 260, and part of the epitaxial layer surface and part of the boss top around the sidewall of the boss 260. The coverage width of the part of the epitaxial layer surface and the part of the boss top is in the range of 5 μm to 10 μm, but is not limited thereto.

[0076] In another embodiment of the present invention, please refer to Fig.15 As shown, the composite structure passivation layer 500 covers the sidewalls of the epitaxial layer 200 and the top and sidewalls of the boss 260 .

[0077] In the vertical structure light-emitting diode provided by the utility model, the epitaxial layer 200 at least includes a first semiconductor layer 230, a light-emitting layer 240 and a second semiconductor layer 250 stacked in sequence from top to bottom, the epitaxial layer 200 includes a first surface S1 and a second surface S2 opposite to each other, at least one first opening 200a penetrating the second semiconductor layer 250 and the light-emitting layer 240 and exposing the first semiconductor layer 230 is formed in the epitaxial layer 200, a boss 260 is formed on the first surface S1 of the epitaxial layer 200, the projection of the boss 260 on the first semiconductor layer 230 covers the bottom of the first opening 200a, and the bottom of the first opening 200a is the surface close to the side of the first semiconductor layer 230. The utility model provides a boss 260 on the epitaxial layer 200 above the first opening 200a to compensate for the thickness difference of the epitaxial layer 200 in different regions, thereby reducing the problem of epitaxial defects aggravated due to the thickness difference of the epitaxial layer 200 and the problem of epitaxial layer defects aggravated due to thermal stress and heat conduction, thereby improving the reliability of the light-emitting diode. At the same time, since the epitaxial layer 200 includes the first semiconductor layer 230, the light-emitting layer 240 and the second semiconductor layer 250, the thickness of the epitaxial layer 200 of the vertical structure light-emitting diode is significantly reduced compared with the total thickness of the epitaxial layer 200 grown on the heterogeneous substrate, thereby reducing the absorption of the light output, and further improving the reliability of the light-emitting diode.

[0078] In addition, the light-emitting diode also includes a composite structure passivation layer 500 covering the epitaxial layer 200. The refractive index of the composite structure passivation layer 500 gradually decreases from the epitaxial layer 200 to the air direction, so that it has higher light transmittance enhancement performance. At the same time, the electrical breakdown resistance and environmental resistance of the composite structure passivation layer 500 are significantly improved, ultimately realizing a high-reliability and high-performance vertical structure light-emitting diode for application in ultra-large current density.

[0079] Figures 2 to 15 It is a schematic structural diagram of each step of a method for manufacturing a vertical structure light emitting diode provided by an embodiment of the utility model.

[0080] The method for manufacturing the vertical structure light emitting diode comprises the following steps:

[0081] Step S1: providing a first substrate, and forming an epitaxial layer on the first substrate, wherein the epitaxial layer at least comprises a first semiconductor layer, a light-emitting layer, and a second semiconductor layer stacked in sequence from bottom to top, wherein the epitaxial layer comprises a first surface and a second surface opposite to each other, and the second surface of the epitaxial layer is a side surface of the second semiconductor layer away from the light-emitting layer;

[0082] Step S2: forming at least one first opening, wherein the first opening penetrates the second semiconductor layer and the light-emitting layer and exposes the first semiconductor layer; forming a boss on the first surface of the epitaxial layer, wherein the projection of the boss on the first semiconductor layer covers the bottom of the first opening, and the bottom of the first opening is the surface close to the first semiconductor layer.

[0083] Next, we will combine Figure 1 and Figures 2 to 15 The method for manufacturing the vertical structure light emitting diode provided by the embodiment of the utility model is described in detail.

[0084] In step S1, refer to Figure 2 As shown, a first substrate 100 (heterogeneous substrate) is provided, and an epitaxial layer 200 is formed on the first substrate 100. The epitaxial layer 200 at least includes a first semiconductor layer 230, a light-emitting layer 240, and a second semiconductor layer 250 stacked in sequence from bottom to top. The epitaxial layer 200 includes a first surface S1 and a second surface S2 opposite to each other, and the second surface S2 of the epitaxial layer 200 is a side surface of the second semiconductor layer 250 away from the light-emitting layer 240. The first substrate 100 includes but is not limited to a sapphire substrate, a silicon substrate, an AlN substrate, or a SiC substrate having micron- or nanometer-scale patterned features. In this embodiment, the first substrate 100 is a micron-scale patterned silicon substrate.

[0085] In this embodiment, a first semiconductor layer 230, a light emitting layer 240 and a second semiconductor layer 250 are sequentially formed on the first substrate 100. Before forming the first semiconductor layer 230, a buffer layer 210 and an unintentionally doped layer 220 may be formed on the first substrate 100, and a first ohmic contact layer (not shown) may be formed after forming the unintentionally doped layer 220. The buffer layer 210, the unintentionally doped layer 220, the first ohmic contact layer, the first semiconductor layer 230, the light emitting layer 240 and the second semiconductor layer 250 may be prepared by metal organic chemical vapor deposition (MOCVD), laser assisted molecular beam epitaxy (MBE), pulsed laser deposition (PLD) or hydride vapor phase epitaxy (HVPE).

[0086] In step S2, please continue to refer to Figures 2 to 15 As shown, at least one first opening 200a is formed, and the first opening 200a penetrates the second semiconductor layer 250 and the light-emitting layer 240 and exposes the first semiconductor layer 230; a boss 260 is formed on the first surface S1 of the epitaxial layer 200, and the projection of the boss 260 on the first semiconductor layer 230 covers the bottom of the first opening 200a, and the bottom of the first opening 200a is the surface close to the first semiconductor layer 230.

[0087] First, please refer to Figure 2 As shown, the second semiconductor layer 250 and the light emitting layer 240 are sequentially etched until the first semiconductor layer 230 is exposed to form a plurality of first openings 200a. Exemplarily, the first openings 200a are formed in the second semiconductor layer 250 and the light emitting layer 240 using photolithography and dry etching processes. The first openings 200a are distributed in an array, and the spacing between the centers of adjacent first openings 200a is 100μm to 200μm. The diameter of the first openings 200a ranges from 20μm to 60μm, and the depth of the first openings 200a ranges from 700nm to 1500nm. For example, in this embodiment, the depth of the first openings 200a is 1μm. Please refer to Fig.16 As shown, the first opening 200a may include a through hole and a groove.

[0088] Next, please refer to Figure 3 As shown, a second ohmic contact layer 310 is formed on the second semiconductor layer 250. Exemplarily, a 15 nm thick ITO material layer is formed on the second semiconductor layer 250 by sputtering deposition technology, and a rapid thermal annealing (RTA) process is performed, and then the second ohmic contact layer 310 is patterned.

[0089] Please continue to refer to Figure 3 As shown, an insulating reflective layer 320 is formed on the second ohmic contact layer 310, and the insulating reflective layer 320 covers the second ohmic contact layer 310 and the second semiconductor layer 250, and covers the sidewalls and the bottom of the first opening 200a. Exemplarily, the insulating reflective layer 320 is a SiO2 low refractive index reflective layer, and the insulating reflective layer 320 can be formed by a CVD or PVD process. The insulating reflective layer 320 is a low refractive index medium reflective layer, and its material is preferably SiO2. The thickness of the insulating reflective layer 320 is 4*λ / 4n (n is the refractive index of the insulating reflective layer 320 corresponding to the light emitting wavelength of the light emitting layer 230). In other embodiments, the insulating reflective layer 320 can also be a distributed Bragg reflector layer (DBR).

[0090] Next, please refer to Figure 4As shown, the insulating reflective layer 320 is etched to form a plurality of second openings 320a exposing the second ohmic contact layer 310. Exemplarily, the second openings 320a distributed in an array are formed by photolithography and etching techniques so that the subsequently formed metal reflective layer 330 and the second ohmic contact layer 310 are electrically connected and current is transmitted.

[0091] Next, please refer to Figure 5 As shown, a metal reflective layer 330 is formed, and the metal reflective layer 330 covers a portion of the insulating reflective layer 320 and fills the second opening 320a. The metal reflective layer 330 does not cover the insulating reflective layer 320 in the first opening 200a. Exemplarily, the metal reflective layer 330 is formed by photolithography and PVD technology, and the metal reflective layer 330 can be a stack of Ag layer, Pt layer and Ti layer, and the thickness can be respectively as well as

[0092] Then, please refer to Figure 6 As shown, a second current spreading layer 340 is formed on the metal reflective layer 330, and the second current spreading layer 340 covers a portion of the surface of the metal reflective layer 330 and the insulating reflective layer 320 at the position of the step 200b to be formed later. Exemplarily, the second current spreading layer 340 is formed by photolithography and PVD technology, and the second current spreading layer 340 can be a stack of Ti layer, Au layer, Pt layer and Cr layer, and the thicknesses thereof are respectively as well as In other embodiments, the metal reflective layer 330 may not fill up the second opening 320 a , but only covers the sidewall and the bottom of the second opening 320 a , and the second current spreading layer 340 fills up the second opening 320 a .

[0093] Please refer to Figure 7 As shown, an isolation dielectric layer 350 is formed, and the isolation dielectric layer 350 covers the second current spreading layer 340, the metal reflective layer 330 and the insulating reflective layer 320, and fills the first opening 200a. Exemplarily, the isolation dielectric layer 350 is a stacked layer composed of a SiO2 layer and a silicon oxynitride layer, and the total thickness of the isolation 350 is 600nm. The isolation dielectric layer 350 can be formed by PECVD technology. Then, the isolation dielectric layer 350 and the insulating reflective layer 320 in the first opening 200a are etched to form a through hole 350a to expose the first semiconductor layer 230 at the bottom of the first opening 200a. Exemplarily, the isolation dielectric layer 350 and the insulating reflective layer 320 are etched by photolithography and F-fluorine-based and Cl-chlorine-based dry etching technology until the surface of the first semiconductor layer 230 is exposed.

[0094] Then, please refer to Figure 8 As shown, a first current spreading layer 360 is formed, and the first current spreading layer 360 covers the isolation dielectric layer 350 and fills the first opening 200a to contact the first semiconductor layer 230 exposed by the through hole 350a. Exemplarily, the first current spreading layer 360 includes a stack of a Ti layer, an Al layer, a Pt layer, and a Ti layer, and the thicknesses thereof are respectively as well as The first current spreading layer 360 may be formed by using PVD technology.

[0095] Next, please refer to Fig. 9 As shown, the second substrate 400 is bonded to the side of the first substrate 100 where the first current spreading layer 360 is formed. Exemplarily, first, a bonding layer 410 is formed on the first current spreading layer 360 and the second substrate 400, and then the first current spreading layer 360 is bonded to the second substrate 400 by a bonding technology. For example, the bonding layer 410 can be formed by electron beam evaporation technology, and the material of the bonding layer 410 is preferably NiSn. The second substrate 400 is a conductive substrate. In this embodiment, the second substrate 400 is a conductive silicon substrate, and the thickness of the second substrate 400 can be 1 mm. In other embodiments, the bonding layer 410 can also be formed only on the first current spreading layer 360 or the second substrate 400.

[0096] Please refer to Fig.10 As shown, the first substrate 100 is removed. Exemplarily, the first substrate 100 is removed by thinning and wet etching technology.

[0097] Please refer to Fig.11 As shown, the buffer layer 210 and part of the unintentional doping layer 220 are removed, and a part of the thickness of the unintentional doping layer is retained as a boss 260. Exemplarily, first, the buffer layer 210 and the unintentional doping layer 220 are etched by Cl-based dry etching technology until 1 μm is left, so as to reduce the influence of the film layer with high defects on the surface on the absorption of light and the electrical characteristics of the light-emitting diode; then, the unintentional doping layer 220 in the light-emitting area (the area outside the first opening 200a) is removed by photolithography and Cl-based dry etching technology, and only the unintentional doping layer 220 above the first opening 200a is retained as a boss 260.

[0098] By providing a boss 260 on the epitaxial layer 200 above the first opening 200a to compensate for the thickness difference of the epitaxial layer 200, the problem of epitaxial defects aggravated due to the thickness difference of the epitaxial layer 200 and the problem of epitaxial layer defects aggravated due to thermal stress and heat conduction are reduced, thereby improving the reliability of the light-emitting diode. At the same time, since the epitaxial layer 200 includes the first semiconductor layer 230, the light-emitting layer 240 and the second semiconductor layer 250, the thickness of the epitaxial layer 200 of the vertical structure light-emitting diode is significantly reduced compared with the total thickness of the epitaxial layer 200 grown on the heterogeneous substrate, thereby reducing the absorption of the output light and further improving the reliability of the light-emitting diode.

[0099] In this embodiment, the thickness of the boss 260 is 50% to 120% of the depth of the first opening 200a, and the depth of the first opening 200a is the distance from the second surface S2 of the epitaxial layer 200 to the bottom of the first opening 200a; the thickness from the bottom of the first opening 200a to the surface of the boss 260 is the first thickness, the total thickness of the first semiconductor layer 230, the light-emitting layer 240 and the second semiconductor layer 250 is the second thickness, and the first thickness is 50% to 100% of the second thickness; the first thickness is ±10% of the depth of the first opening 200a.

[0100] In this step, the epitaxial layer 200 and the insulating reflective layer 320 are then etched in sequence to form a step 200b exposing the second current spreading layer 340 on the periphery of the epitaxial layer 200, that is, the side walls of the step 200b are the side walls of the epitaxial layer 200 and the insulating reflective layer 320, and the lower step surface exposes the second current spreading layer 340 and the isolation dielectric layer 350.

[0101] Next, please refer to Fig.12 As shown, the exposed surface of the epitaxial layer 200 is roughened. Exemplarily, a 6 mol / L KOH hot solution is used to perform the roughening treatment at 70° C. to form a roughened surface. It is understandable that the step 200 b can be formed first and then roughened, or roughened first and then formed.

[0102] Please refer to Fig.13 As shown, a composite structure passivation layer 500 is formed, and the composite structure passivation layer 500 covers the sidewalls of the epitaxial layer 200 and the sidewalls of the insulating reflective layer 320, and covers the first surface of the epitaxial layer 200 and the sidewalls and top of the boss 260. Specifically, Fig.13In the embodiment, the composite structure passivation layer 500 covers the side walls of the epitaxial layer 200 and the insulating reflective layer 320, and covers the first surface of the epitaxial layer 200, the side walls and the top of the boss 260. The composite structure passivation layer 500 also covers the isolation dielectric layer 350 on the lower step surface, and an opening exposing the second current spreading layer 340 is formed in the composite structure passivation layer 500.

[0103] From the epitaxial layer 200 to the air, the refractive index of the composite structure passivation layer 500 gradually decreases, so that it has higher light transmittance performance. At the same time, the electrical breakdown resistance and environmental resistance of the composite structure passivation layer 500 are significantly improved, and finally a high-reliability and high-performance vertical structure light-emitting diode for ultra-large current density is realized.

[0104] In another embodiment of the present invention, please refer to Fig.14 As shown, the composite structure passivation layer 500 covers the side walls of the epitaxial layer 200 and the side walls of the insulating reflective layer 320, and covers the side walls of the boss 260 and part of the epitaxial layer surface and part of the boss top around the side walls of the boss 260. The coverage width range of the part of the epitaxial layer surface and the part of the boss top is, for example, 5μm to 10μm.

[0105] In another embodiment of the present invention, please refer to Fig.15 As shown, the composite structure passivation layer 500 covers the sidewalls of the epitaxial layer 200 and the sidewalls of the insulating reflective layer 320 , and covers the top and sidewalls of the boss 260 .

[0106] Exemplarily, the composite structure passivation layer 500 includes a stack of a silicon oxynitride layer, an Al2O3 layer and a SiO2 layer, wherein the refractive indices of the silicon oxynitride layer, the Al2O3 layer and the SiO2 layer are arranged in descending order.

[0107] In one embodiment of the present invention, before forming the composite structure passivation layer 500 (the composite structure passivation layer 500 covers a range such as Fig.13 As shown), or after forming the composite structure passivation layer 500 (the composite structure passivation layer 500 covers a range as shown Fig.14 and Fig.15 As shown in FIG. 1 , the surface of the epitaxial layer 200 (the surface away from the second substrate 400) may be treated with F ions to form a high-resistance epitaxial film layer to avoid short circuits in the light-emitting diode. Exemplarily, the thickness of the high-resistance epitaxial film layer may be 20 nm to 50 nm, but is not limited thereto.

[0108] After that, please continue to refer to Fig.13As shown, a second electrode 610 is formed on the second current spreading layer 340 exposed by the opening of the composite structure passivation layer 500. Exemplarily, the second electrode 610 is formed with a thickness of 1 μm by electron beam evaporation technology, and the material of the second electrode 610 is, for example, TiNiAu.

[0109] Then, the back side of the second substrate 400 (ie, the side away from the epitaxial layer 200 ) may be thinned, for example, the thickness of the second substrate 400 may be thinned from 1 mm to 150 μm.

[0110] Please refer to Figure 1 As shown, a first electrode 620 is formed on a side of the second substrate 400 away from the bonding layer 410. Exemplarily, the first electrode 620 is formed by using PVD technology, and the material of the first electrode 620 is, for example, TiPtAu.

[0111] Then, ultraviolet laser metal grooving and diamond knife cutting processing methods can be used to complete the bare chip (die) splitting, and finally a vertical structure light emitting diode is obtained.

[0112] In the method for manufacturing a vertical structure light-emitting diode provided by the utility model, the epitaxial layer 200 at least includes a first semiconductor layer 230, a light-emitting layer 240 and a second semiconductor layer 250 stacked in sequence from top to bottom, the epitaxial layer includes a first surface S1 and a second surface S2 opposite to each other, the second surface S2 of the epitaxial layer 200 is a side surface of the second semiconductor layer 230 away from the light-emitting layer 240, at least one first opening 200a is formed in the epitaxial layer 200, which penetrates the second semiconductor layer 250 and the light-emitting layer 240 and exposes the first semiconductor layer 230, and a boss 260 is formed on the first surface S1 of the epitaxial layer 200, and the projection of the boss 260 on the first semiconductor layer 230 covers the bottom of the first opening 200a, and the bottom of the first opening 200a is a surface close to the side of the first semiconductor layer 230. The utility model provides a boss 260 on the epitaxial layer 200 above the first opening 200a to compensate for the thickness difference of the epitaxial layer 200 in different regions, thereby reducing the problem of epitaxial defects aggravated due to the thickness difference of the epitaxial layer 200 and the problem of epitaxial layer defects aggravated due to thermal stress and heat conduction, thereby improving the reliability of the light-emitting diode. At the same time, since the epitaxial layer 200 includes the first semiconductor layer 230, the light-emitting layer 240 and the second semiconductor layer 250, the thickness of the epitaxial layer 200 of the vertical structure light-emitting diode is significantly reduced compared with the total thickness of the epitaxial layer 200 grown on the heterogeneous substrate, thereby reducing the absorption of the light output and further improving the reliability of the light-emitting diode.

[0113] In addition, the light-emitting diode also includes a composite structure passivation layer 500 covering the epitaxial layer 200. The refractive index of the composite structure passivation layer 500 gradually decreases from the epitaxial layer 200 to the air direction, so that it has higher light transmittance enhancement performance. At the same time, the electrical breakdown resistance and environmental resistance of the composite structure passivation layer 500 are significantly improved, ultimately realizing a high-reliability and high-performance vertical structure light-emitting diode for application in ultra-large current density.

[0114] The above description is only a description of the preferred embodiment of the utility model, and is not any limitation on the scope of rights of the utility model. Any technical personnel in this field can make possible changes and modifications to the technical solution of the utility model by using the methods and technical contents disclosed above without departing from the spirit and scope of the utility model. Therefore, any simple modifications, equivalent changes and modifications made to the above embodiments based on the technical essence of the utility model without departing from the content of the technical solution of the utility model are within the protection scope of the technical solution of the utility model.

Claims

1. A vertical structure light emitting diode, characterized in that: include: An epitaxial layer, the epitaxial layer at least comprising a first semiconductor layer, a light-emitting layer and a second semiconductor layer stacked in sequence from top to bottom, the epitaxial layer comprising a first surface and a second surface opposite to each other, the second surface of the epitaxial layer being a side surface of the second semiconductor layer away from the light-emitting layer; at least one first opening, wherein the first opening penetrates the second semiconductor layer and the light emitting layer and exposes the first semiconductor layer; A boss is located on the first surface of the epitaxial layer, wherein a projection of the boss on the first semiconductor layer covers a bottom of the first opening, and the bottom of the first opening is a surface close to one side of the first semiconductor layer.

2. The vertical structure light emitting diode according to claim 1, characterized in that: The size of the projection of the boss on the first semiconductor layer does not exceed twice the size of the opening of the first opening, and the opening of the first opening is the opening of the first opening on the second surface of the epitaxial layer.

3. The vertical structure light emitting diode according to claim 1 or 2, characterized in that: The thickness d1 of the boss is 50% to 120% of the depth d4 of the first opening, wherein the depth of the first opening is the distance from the second surface of the epitaxial layer to the bottom of the first opening.

4. The vertical structure light emitting diode according to claim 3, characterized in that: The thickness from the bottom of the first opening to the surface of the boss is a first thickness d5, the total thickness of the first semiconductor layer, the light emitting layer and the second semiconductor layer is a second thickness d2, and the first thickness d5 is 50% to 100% of the second thickness d2.

5. The vertical structure light emitting diode according to claim 4, characterized in that: The first thickness d5 is ±10% of the depth d4 of the first opening.

6. The vertical structure light emitting diode according to claim 1, characterized in that: The thickness of the boss is in the range of 0.35 μm to 1.8 μm.

7. The vertical structure light emitting diode according to claim 1, characterized in that: A plurality of the first opening arrays are arranged in the epitaxial layer.

8. The vertical structure light emitting diode according to claim 1 or 7, characterized in that: The first opening includes a through hole and / or a groove.

9. The vertical structure light emitting diode according to claim 1, characterized in that: The first surface is a surface of the first semiconductor layer, and the boss is located on the first semiconductor layer.

10. The vertical structure light emitting diode according to claim 1, characterized in that: The epitaxial layer further includes a first ohmic contact layer located on the first semiconductor layer, the first surface is a surface of the first ohmic contact layer, and the boss is located on the first ohmic contact layer.

11. The vertical structure light emitting diode according to claim 1, characterized in that: The epitaxial layer also includes a first ohmic contact layer and an unintentional doping layer stacked in sequence from bottom to top on the first semiconductor layer, the first surface is the surface of the unintentional doping layer, and the boss is located on the unintentional doping layer.

12. The vertical structure light emitting diode according to any one of claims 9 to 11, characterized in that: The boss is an unintentionally doped layer.

13. The vertical structure light emitting diode according to any one of claims 9 to 10, characterized in that: The boss is a first ohmic contact layer and an unintentionally doped layer stacked in sequence from bottom to top.

14. The vertical structure light emitting diode according to claim 1, characterized in that: The vertical structure light emitting diode further comprises: A second ohmic contact layer, wherein the second ohmic contact layer is located on a surface of a portion of the second semiconductor layer away from the first semiconductor layer; an insulating reflective layer, wherein the insulating reflective layer covers the second ohmic contact layer and the second semiconductor layer, and covers a side wall of the first opening; a plurality of second openings, wherein the second openings penetrate the insulating reflective layer and expose a portion of the second ohmic contact layer; a metal reflective layer, the metal reflective layer being located on a surface of a portion of the insulating reflective layer away from the second semiconductor layer and covering at least a sidewall and a bottom of the second opening; and a second current spreading layer, the second current spreading layer being located on a surface of the metal reflective layer away from the epitaxial layer; an isolation dielectric layer, the isolation dielectric layer covering the metal reflection layer, the second current spreading layer and the insulating reflection layer, and covering the side wall of the first opening; A first current spreading layer is located on a surface of the isolation dielectric layer away from the epitaxial layer and fills the first opening.

15. The vertical structure light emitting diode according to claim 14, characterized in that: The light emitting diode further comprises: A bonding layer, located on a side of the first current spreading layer away from the isolation dielectric layer; a substrate, located on a side of the bonding layer away from the first current spreading layer; A first electrode, located on a side of the substrate away from the bonding layer; a step, located at the periphery of the epitaxial layer, penetrating the epitaxial layer and the insulating reflective layer and exposing the second current spreading layer; and The second electrode is located on the step and is electrically connected to the second current spreading layer.

16. The vertical structure light emitting diode according to claim 15, characterized in that: The vertical structure light emitting diode further comprises a composite structure passivation layer covering at least a portion of the surface of the epitaxial layer, and the refractive index of the composite structure passivation layer gradually decreases from the epitaxial layer to the air.

17. The vertical structure light emitting diode according to claim 16, characterized in that: The composite structure passivation layer covers the side walls of the epitaxial layer, the first surface of the epitaxial layer, and the side walls and top of the boss; or, the composite structure passivation layer covers the side walls of the epitaxial layer, the side walls and top of the boss; or, the composite structure passivation layer covers the side walls of the epitaxial layer, the side walls of the boss, and part of the epitaxial layer surface around the side walls of the boss and part of the boss top, and the coverage width of the part of the epitaxial layer surface and the part of the boss top is in the range of 5μm to 10μm.

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