Power over Ethernet (PoE) switch

Abstract

The utility model discloses an Ethernet power supply PoE switch, comprising an Ethernet switch chip comprising a data port which is connected with an Ethernet port and is used for transmitting Ethernet data with external equipment through the Ethernet port; the power supply equipment PSE chip comprises a power supply port, and the power supply port is connected with the Ethernet port and used for supplying power to external equipment through the Ethernet port; the first switch is connected between each power supply port and the Ethernet port and is connected with the MCU; and the MCU is connected with the PSE chip and the first switches and is used for communicating with the PSE chip to obtain fault information and controlling the first switches to be switched off so as to cut off power supply to external equipment when determining that the PSE chip has a port fault. Therefore, the problem that when a part of ports of the PoE switch break down, other normal ports or lower PD equipment cannot work, so that the utilization rate of the ports is not high is solved.

Description

Technical Field

[0001] The utility model relates to the technical field of Ethernet switches, in particular to a Power over Ethernet (PoE) switch. Background Art

[0002] Power on Ethernet (PoE) switches include two functions: Ethernet switch and PoE power supply. The switch port transmits data through the network cable and provides power to the powered device (PD). It ensures the safety of the existing wiring while ensuring the normal operation of the network, eliminating the need for additional power wiring and minimizing costs.

[0003] There are three main steps to implement the PSE (Power Sourcing Equipment) chip power supply for POE power supply: detection, device classification and power supply. First, detect whether it is a powered device, then classify and determine the power consumption of the powered device, and finally provide the corresponding power consumption to the PD device. When using a PoE switch, when a switch port of the PSE chip fails, all ports under the chip will not be able to supply power to the outside. This will cause other normal ports or PD devices under the PSE chip to also fail to work, resulting in low port utilization of the PoE switch. Utility Model Content

[0004] The utility model aims to provide a Power over Ethernet (PoE) switch, which is used to solve the problem in the related art that when some ports of the PoE switch fail, other normal ports or PD devices connected to the PSE chip will also fail to work, resulting in low port utilization of the PoE switch.

[0005] In a first aspect, an embodiment of the utility model provides a Power over Ethernet (PoE) switch, comprising:

[0006] An Ethernet switch chip, comprising a data port, wherein the data port is connected to the Ethernet port and is used to transmit Ethernet data to an external device through the Ethernet port;

[0007] A power supply equipment PSE chip, comprising a power supply port, wherein the power supply port is connected to the Ethernet port and is used to supply power to an external device through the Ethernet port;

[0008] A first switch is connected between each power supply port pin as a positive electrode and the Ethernet port, and is connected to a micro control unit MCU;

[0009] An external device connector, including the Ethernet port, for connecting to an external device;

[0010] The microcontroller unit MCU is connected to the PSE chip and each first switch, and is used for communicating with the PSE chip to obtain fault information, and when it is determined that a port fault occurs in the PSE chip, controlling the first switch to be disconnected to cut off power supply to the external device.

[0011] In one or more possible embodiments, the PoE switch further includes:

[0012] A second switch is connected between the power port of the PSE chip and an external power supply, and is connected to the micro control unit MCU;

[0013] The micro control unit MCU is also used to cut off the connection between the power port and the external power supply by controlling the second switch when determining that a chip failure occurs in the PSE chip.

[0014] In one or more possible embodiments, the PoE switch further includes:

[0015] A storage chip connected to the microcontroller unit MCU;

[0016] The microcontroller unit MCU is further used to store the acquired fault information in a storage chip, control the first switch or the second switch based on the fault information in the storage chip, and clear the fault information in the storage chip when it is determined that the fault is eliminated.

[0017] In one or more possible embodiments, the PSE chip is connected to the microcontroller unit MCU via an interrupt signal port;

[0018] The PSE chip is used to generate an interrupt signal at the interrupt signal port when determining that a port fault or a chip fault occurs.

[0019] In one or more possible embodiments, the PSE chip is connected to the micro control unit MCU via a first integrated circuit bus interface;

[0020] The micro control unit MCU is also used for querying the fault status of each port from the PSE chip through the first integrated circuit bus interface to obtain fault information when the interrupt signal port detects an interrupt signal.

[0021] In one or more possible embodiments, the PSE chip further includes: a status register, configured to store a fault status of each port.

[0022] In one or more possible embodiments, the storage chip is connected to the micro control unit MCU via a second integrated circuit bus interface.

[0023] In one or more possible embodiments, the first switch is a metal oxide semiconductor field effect transistor (MOSFET), and the second switch is a metal oxide semiconductor field effect transistor (MOSFET).

[0024] In one or more possible embodiments, the external device connector is an RJ45 connector, and the power supply port pin is connected to the RJ45 connector via a transformer.

[0025] In one or more possible embodiments, the memory chip is an electrically erasable programmable read-only memory (EEPROM).

[0026] The utility model provides a PoE switch that adds a switch between the power supply port and the Ethernet port, and the switch is controlled by an MCU, so that when a port failure occurs in a PSE chip, the MCU shields the failed port by controlling the switch, cuts off the power supply to the external device through the Ethernet port, does not affect the utilization rate of other normal ports, and improves the utilization rate of the PoE switch port. This solves the problem in the related art that when some ports of the PoE switch fail, other normal ports or PD devices connected to the PSE chip will not work, resulting in a low port utilization rate of the PoE switch.

[0027] Other features and advantages of the utility model will be described in the subsequent description, and partly become apparent from the description, or understood by practicing the utility model. The purpose and other advantages of the utility model can be realized and obtained by the structures specifically pointed out in the written description, claims, and drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] In order to more clearly illustrate the technical solutions of the embodiments of the utility model, the drawings required for use in the embodiments of the utility model will be briefly introduced below. Obviously, the drawings introduced below are only some embodiments of the utility model. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0029] Figure 1 It is a schematic diagram of the structure of a PSE chip according to the related art;

[0030] Figure 2 A structural diagram of a PoE switch according to an embodiment of the utility model;

[0031] Figure 3 A detailed structural diagram of a PoE switch provided according to an embodiment of the utility model;

[0032] Figure 4The present invention provides a flow chart of implementing port isolation on a PoE switch according to an embodiment of the present invention. DETAILED DESCRIPTION

[0033] To further illustrate the technical solution provided by the embodiment of the utility model, this is described in detail below in conjunction with the accompanying drawings and specific implementation methods. Although the embodiment of the utility model provides the method operation steps shown in the following embodiments or drawings, more or fewer operation steps may be included in the method based on routine or no creative labor. In the steps where there is no necessary causal relationship logically, the execution order of these steps is not limited to the execution order provided by the embodiment of the utility model. In the actual processing process or when the control device is executed, the method can be executed in the order of the method shown in the embodiment or drawings or in parallel.

[0034] PoE switch includes two functions: Ethernet switch and PoE power supply. The switch port transmits data through the network cable and supplies power to the PD device. As the power consumption of PD devices (network cameras, IP phones, etc.) increases, the PoE power supply standards formulated by IEEE (Institute of Electrical and Electronics Engineers) are also changing: IEEE802.3af standard, each port supports an output power of 15.4w; IEEE802.3at standard, each port supports an output power of 30w; IEEE802.3bt standard, each port supports an output power of 90w.

[0035] like Figure 1 As shown, the PSE chip includes a power port VCC and a power port pin for powering external devices. The cathode of the power port includes a POS pin as a positive pole and a NEG pin as a negative pole. The power port VCC is connected to an external power supply, and all NEG pins are connected to the same level. In the related art, the PSE chip controls whether the PSE chip supplies power to the outside through the NEG pin. During the use of the PoE switch, when a port of the PSE chip fails, such as short circuit, overvoltage, overcurrent, etc., it will affect the PSE chip corresponding to the port, resulting in all ports under the PSE chip being unable to supply power to the outside. This will also cause other normal ports or PD devices hanging under the PSE chip to not work, resulting in low port utilization of the PoE switch.

[0036] In order to avoid this situation, a solution needs to be provided to isolate the situation where other normal ports cannot be powered due to a damaged Ethernet port.

[0037] Other features and advantages of the utility model will be described in the subsequent description, and partly become apparent from the description, or understood by practicing the utility model. The purpose and other advantages of the utility model can be realized and obtained by the structures specifically pointed out in the written description, claims, and drawings.

[0038] The present invention provides a Power over Ethernet (PoE) switch. Figure 2 As shown, including:

[0039] The Ethernet switch chip 201 includes a data port pin, wherein the data port pin is connected to the Ethernet port and is used to transmit Ethernet data to an external device through the Ethernet port;

[0040] The data port pins of the Ethernet switch chip 201 are connected to the Ethernet port to achieve data communication with external devices, specifically, the Ethernet data sent to the external device is processed and transmitted to the external device via the Ethernet port, and the Ethernet data transmitted by the external device is received via the Ethernet port.

[0041] The power supply equipment PSE chip 202 includes a power supply port pin, wherein the power supply port pin is connected to the Ethernet port and is used to supply power to an external device through the Ethernet port;

[0042] The Ethernet switch chip 201 and the PSE chip are independent chips, which are connected to the same Ethernet port through data port pins and power port pins respectively, so that the Ethernet port in the PoE switch has both Ethernet data transmission function and power supply function.

[0043] The first switch 203 is connected between each power supply port pin as a positive electrode and the Ethernet port, and is connected to the micro control unit MCU;

[0044] The external device connector 204 includes the Ethernet port and is used to connect to an external device;

[0045] The microcontroller unit MCU205 is connected to the PSE chip and each first switch, and is used to communicate with the PSE chip to obtain fault information, and when it is determined that a port fault occurs in the PSE chip, control the first switch to be disconnected to cut off the power supply to the external device.

[0046] In the embodiment of the present application, the power supply and data transmission control of the Ethernet port is no longer achieved by controlling the NEG pin. Instead, a first switch is connected to the positive power supply port pin and then connected to the Ethernet port, and the first switch is connected to the microcontroller unit MCU, thereby supporting the on and off control of the first switch by the MCU, thereby achieving control of whether a single Ethernet port supplies power to an external device.

[0047] When any power supply port of the PSE chip fails, the PSR chip will generate fault information, and the microcontroller unit MCU communicates with the PSE chip to obtain the fault information. The position of the port where the fault occurs can be determined based on the fault information. If it is determined that a port fault occurs, the first switch connected to the pin of the faulty power supply port is controlled, specifically, the first switch is disconnected, thereby cutting off the power supply of the Ethernet port to the external device, thereby shielding the faulty port, while other Ethernet ports continue to work normally, thereby improving the utilization rate of the Ethernet port of the PoE switch.

[0048] When a PoE switch may include multiple PSE chips, when a PSE chip in the PoE switch fails during use, the entire device is usually powered off and waits for repair or replacement. This will also cause other normal ports or PD devices connected to the PSE chip to fail to work, resulting in low utilization of the PoE switch port. The PoE switch described in the embodiment of the present application also includes:

[0049] A second switch 206 is connected between the power port of the PSE chip 202 and an external power source, and is connected to the micro control unit MCU205;

[0050] The micro control unit MCU205 is also used to cut off the connection between the power port and the external power supply by controlling the second switch 206 when determining that a chip failure occurs in the PSE chip 202 .

[0051] The PSE chip 202 is connected to an external power supply through a power port. When a PSE chip has a chip failure, such as short circuit, overvoltage, overcurrent, etc., it will affect the PSE chip corresponding to the port, causing all ports under the PSE chip to be unable to supply power to the outside. When a chip failure occurs, the PSE chip will detect the failure, and the microcontroller unit MCU communicates with the PSE chip to obtain the failure information. According to the failure information, it can be determined that a chip failure currently occurs, and the second switch connected to the power port is controlled, specifically, the second switch is disconnected, thereby cutting off the external power supply to the power port, and realizing power-off of the PSE chip, while other devices in the entire PoE switch are not affected, thereby improving the utilization rate of the normal Ethernet port of the PoE switch.

[0052] As a possible implementation, the first switch may be, but is not limited to, a metal oxide semiconductor field effect transistor MOSFET, and the second switch may be, but is not limited to, a metal oxide semiconductor field effect transistor MOSFET.

[0053] As a possible implementation, Figure 2 As shown, the PoE switch also includes:

[0054] A storage chip 207 connected to the microcontroller unit MCU204;

[0055] The microcontroller unit MCU205 is further used to store the acquired fault information in the storage chip 207, control the first switch or the second switch based on the fault information in the storage chip 207, and clear the fault information in the storage chip when it is determined that the fault is eliminated.

[0056] In the embodiment of the present application, if a fault occurs in the PSE chip, the microcontroller unit MCU will be notified in real time. The microcontroller unit MCU obtains fault information from the PSE chip and stores it in the storage chip. On the one hand, it can record which locations have faults. On the other hand, after receiving the fault notification of the PSE chip and obtaining the fault information, it can compare the fault information with the stored fault information to determine whether a new fault has occurred. If no new fault has occurred, it means that the fault has been cut off before and no further processing is performed. If a new fault has occurred, the fault information of the new fault is stored in the storage chip, and at the same time, based on the fault information of the new fault, the switch connected to the newly appeared fault port or the faulty chip is controlled, thereby cutting off the corresponding connection so that other normal locations are not affected.

[0057] The above-mentioned storage chip is an electrically erasable programmable read-only memory EEPROM, so that the fault information will not be lost when the power is off. Therefore, at the appropriate maintenance time, the PoE switch can be powered off, and the faulty port or faulty chip that has failed can be repaired by maintenance personnel based on the fault information stored in the EEPROM, and the fault information in the storage chip is cleared after the maintenance is completed. In this way, the microcontroller unit MCU cannot read any fault information from the storage chip when the machine is turned on next time, so it will control all switches to close. If the PoE switch is powered off and the maintenance is not completed before the next startup, the microcontroller unit MCU reads the fault information from the storage chip, controls the switch based on the fault information, and shields the fault location. If the PoE switch is successfully repaired after powering off, but the fault information in the storage chip is not cleared, then after the next startup, since the microcontroller unit MCU will not obtain any fault information from the PSE chip, if the fault information is not obtained within the set time, it is determined that the fault is eliminated, and the microcontroller unit MCU clears the fault information in the storage chip.

[0058] The following is a specific embodiment of the Ethernet Power Supply PoE switch in the present application. Figure 3As shown, the first switch 203 uses MOSFET1, the second switch 206 uses MOSFET2, and the storage chip 207 uses EEPROM. The embodiment of the present application adds modules such as MCU2, MOSFET1, MOSFET2 and EEPROM to the original PoE switch. The power port VCC of the PSE chip can be but not limited to 54V voltage, and the power supply port pins of the PSE chip 202 include POS1+, POS2+, POS3+, and POS4+ as positive electrodes. Each POS+ as a positive electrode is connected to MOSFET1, and the MOSFET is controlled to be opened and closed through the MCU pin. The EEPROM is used to store the fault information on the PSE chip obtained by the MCU from the PSE chip. The PSE chip 202 is connected to the microcontroller unit MCU204 through an interrupt signal port (INT port); the PSE chip is used to generate an interrupt signal at the interrupt signal port when determining that a port fault or a chip fault occurs.

[0059] The fault detection mechanism of the PSE chip in the embodiment of the present application is that if a fault is detected in any power supply port or PSE chip, an interrupt signal will be continuously sent through the INT port before the fault is eliminated, so that the microcontroller chip MCU can determine that a fault has occurred and the fault has not been eliminated through the interrupt signal, thereby keeping the fault location in a power-off state. If the INT port no longer generates an interrupt signal, the microcontroller chip MCU can determine that the fault has been eliminated, and can restore the power supply to the fault location by controlling the switch, so that the port is in a normal working state.

[0060] As a possible implementation, the PSE chip 202 is connected to the microcontroller unit MCU205 via a first integrated circuit bus IIC interface; the microcontroller unit MCU is also used to query the PSE chip for the fault status of each port via the first integrated circuit bus interface when the interrupt signal port detects an interrupt signal. The above-mentioned PSE chip also includes: a status register, which is used to store the fault status of each port.

[0061] The PSE chip will store the fault status of each port locally. The fault status includes fault occurrence and non-fault occurrence. Specifically, different bit values ​​of the fault indication bit can be used to indicate it. Therefore, the fault status can include the port number and the fault indication bit. The fault status can be stored in the status register. The first integrated circuit bus IIC interface is a data interface. If the PSE chip fails, an interrupt signal will be generated at the INT port, thereby triggering the micro control unit MCU to read the fault status in the status register in the PSE chip through the first integrated circuit bus IIC interface, so that the faulty port or faulty chip can be determined and the fault information can be obtained.

[0062] The memory chip in the embodiment of the present application is connected to the micro control unit MCU via the second integrated circuit bus IIC interface, so that the micro control unit MCU reads the fault information from the memory chip and reads the fault information read from the PSE to the memory chip. Figure 3 As shown, in the embodiment of the present application, the first integrated circuit bus interface connected to the PSE chip in the MCU is identified as the IIC1 interface, and the second integrated circuit bus interface connected to the EEPROM in the MCU is identified as the IIC2 interface. The MCU is connected to MOSFET1 through the GPIO pin, and is connected to MOSFET2 through the GPIO pin.

[0063] In the embodiment of the present application, the external device connector 204 is an RJ45 connector, and the power supply port pins are connected to the RJ45 connector via a transformer 208 .

[0064] The power supply voltage of the positive power supply port pin, i.e., the POS pin, in the PSE chip can be, but is not limited to, 54V. The RJ45 connector pin is used to connect external devices. The PSE chip controls whether the device supplies power to the outside through the NEG pole. When supplying power to the outside, the MCU controls MOSFET1 to isolate the faulty port.

[0065] This application increases the utilization rate of the PoE switch port by adding MOSFETs to the power supply port pins and the VCC power supply of the power port of the PSE chip and shielding the fault location using MCU control without affecting the utilization rate of other normal ports; and stores the fault information in the EEPROM for easy viewing during troubleshooting, thereby improving maintenance efficiency.

[0066] like Figure 4 The process of implementing fault isolation for the Power over Ethernet (PoE) switch provided in the embodiment of the present application specifically includes:

[0067] Step 401, after the PoE switch is started, it starts self-test;

[0068] Step 402, the MCU checks whether fault information is stored in the EEPROM. If fault information is detected, step 403 is executed, otherwise step 404 is executed;

[0069] Step 403, when it is determined according to the fault information that there is a faulty port, determine the MOSFET1 connected to the positive pin of the faulty port, and control the MOSFET1 to cut off the connection between the faulty port and the external device;

[0070] Step 404, the MCU determines whether the PSE chip generates an interrupt signal at the INT port periodically. If no interrupt signal is received within a set time, step 405 is executed, otherwise step 406 is executed;

[0071] Step 405, determining that the POE switch can work normally, controlling the MOSFETs connected to the positive pins of all power supply ports to be in a conducting state, and erasing the fault information stored in the EEPROM;

[0072] Step 406, the MCU queries the fault status of each port stored in the status register of the PSE chip through the IIC1 interface to determine the fault type;

[0073] When a power supply port of the PSE chip fails, an interrupt signal will be immediately sent to the MCU. The MCU will query which power supply port is faulty through IIC1, and then immediately turn off the MOSFET connected to the positive pole of the port, cutting off the external power supply. At the same time, the faulty port number is stored in the EEPROM. At this time, the other normal power supply ports on the PSE chip can continue to supply power to the outside.

[0074] Step 407, determine whether it is a disconnection fault, if the fault type is a chip fault, execute step 408, if the fault type is a port fault, execute step 409;

[0075] Step 408, determining that a chip failure occurs, turning off the MOSFET 2 connected to the power port of the PSE chip, disconnecting the power supply, storing the failure information in the EEPROM, and executing step 412;

[0076] When the PSE chip (non-power supply port) is damaged, such as chip short circuit, overvoltage, overcurrent, etc., the PSE chip will also send an interrupt signal. At this time, the MCU first checks whether the port is faulty through IIC1. If the detected port is not faulty, the MCU determines that the chip is damaged, and immediately controls MOSFET2 to turn off the VCC_54V power supply on the PSE chip, so that the entire chip is powered off, and the chip fault information is written to the EEPROM.

[0077] Step 409, shut down the power supply of the faulty port and update the fault information to be stored in the EEPROM;

[0078] Step 410, the MCU cyclically queries other ports of the PSE chip through the IIC1 interface;

[0079] If the port fault is not repaired, the PSE chip will continue to send out interrupt signals. The MCU will query the PSE chip through IIC1 to see if there are other ports damaged. If other ports are found to be damaged, the new fault information will be written to the EEPROM to continuously record the fault information.

[0080] Step 411, determine whether a new fault occurs, if yes, return to step 407, otherwise go to step 412;

[0081] Step 412, in response to the fault information viewing instruction, the fault information in the EEPROM is output to facilitate maintenance personnel to perform maintenance.

[0082] When a fault occurs in the above two situations, the MCU will save the fault information (port or chip fault) in the EEPROM. During maintenance, the information in the EEPROM is checked to locate the specific fault location. After the repair, the information in the EEPROM is erased, and the MCU will not detect the interrupt during the power-on self-test and work normally until a new fault occurs.

[0083] Although the preferred embodiments of the present invention have been described, those skilled in the art may make additional changes and modifications to these embodiments once they have learned the basic creative concept. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications falling within the scope of the present invention.

[0084] Obviously, those skilled in the art can make various changes and modifications to the present invention without departing from the spirit and scope of the present invention. Thus, if these modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalents, the present invention is also intended to include these modifications and variations.

Claims

1. A Power over Ethernet (PoE) switch, characterized in that: include: An Ethernet switch chip, comprising a data port pin, wherein the data port pin is connected to an Ethernet port and is used to transmit Ethernet data to an external device through the Ethernet port; A power supply equipment PSE chip, comprising a power supply port pin, wherein the power supply port pin is connected to the Ethernet port and is used to supply power to an external device through the Ethernet port; A first switch is connected between each power supply port pin as a positive electrode and the Ethernet port, and is connected to a micro control unit MCU; An external device connector, including the Ethernet port, for connecting to an external device; The microcontroller unit MCU is connected to the PSE chip and each first switch, and is used for communicating with the PSE chip to obtain fault information, and when it is determined that a port fault occurs in the PSE chip, controlling the first switch to be disconnected to cut off power supply to the external device.

2. The PoE switch according to claim 1, characterized in that: The PoE switch also includes: A second switch is connected between the power port of the PSE chip and an external power supply, and is connected to the micro control unit MCU; The micro control unit MCU is also used to cut off the connection between the power port and the external power supply by controlling the second switch when determining that a chip failure occurs in the PSE chip.

3. The PoE switch according to claim 1 or 2, characterized in that: PoE switches also include: A storage chip connected to the microcontroller unit MCU; The microcontroller unit MCU is further used to store the acquired fault information in a storage chip, control the first switch or the second switch based on the fault information in the storage chip, and clear the fault information in the storage chip when it is determined that the fault is eliminated.

4. The PoE switch according to claim 1 or 2, characterized in that: The PSE chip is connected to the micro control unit MCU via an interrupt signal port; The PSE chip is used to generate an interrupt signal at the interrupt signal port when determining that a port fault or a chip fault occurs.

5. The PoE switch according to claim 4, characterized in that: The PSE chip is connected to the micro control unit MCU via a first integrated circuit bus interface; The micro control unit MCU is also used for querying the fault status of each port from the PSE chip through the first integrated circuit bus interface to obtain fault information when the interrupt signal port detects an interrupt signal.

6. The PoE switch according to claim 5, characterized in that: The PSE chip further includes: a status register for storing the fault status of each port.

7. The PoE switch according to claim 3, characterized in that: The storage chip is connected to the micro control unit MCU via a second integrated circuit bus interface.

8. The PoE switch according to claim 2, characterized in that: The first switch is a metal oxide semiconductor field effect transistor MOSFET, and the second switch is a metal oxide semiconductor field effect transistor MOSFET.

9. The PoE switch according to claim 1, characterized in that: The external device connector is an RJ45 connector, and the power supply port pins are connected to the RJ45 connector via a transformer.

10. The PoE switch according to claim 3, characterized in that: The storage chip is an electrically erasable programmable read-only memory (EEPROM).

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