Display panel and display terminal

Abstract

The utility model discloses a display panel and a display terminal. The display panel comprises a substrate and a thin film transistor, the thin film transistor comprises an active part, a gate insulating layer and a gate electrode, and the active part comprises a main body part and an edge part; the gate insulating layer is arranged on one side of the active part and comprises a first insulating part aligned with the main body part and a second insulating part aligned with the edge part; the gate is arranged on the surface of the gate insulating layer away from one side of the active part; wherein the orthographic projection of the second insulating part on the substrate at least covers the orthographic projection of the edge part on the substrate, and the capacitance of the gate oxide layer corresponding to the second insulating part is smaller than that of the gate oxide layer corresponding to the first insulating part. The capacitance of the gate oxide layer corresponding to the second insulating part is set to be smaller than the capacitance of the gate oxide layer corresponding to the first insulating part, so that the thin film transistor corresponding to the edge part is more difficult to open, the influence of a hump effect is reduced, the current of the thin film transistor in a working interval is increased, and the charging capability of the thin film transistor is improved.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to a display panel and a display terminal. Background Art

[0002] There is a hump effect in thin film transistors, that is, the main area and edge area of ​​the active layer of the thin film transistor have different threshold voltages. The threshold voltage of the active layer in the edge area is more negative than the threshold voltage of the active layer in the main area, which causes the current of the thin film transistor to decrease within the operating voltage range, affecting the charging capacity of the circuit.

[0003] Therefore, it is urgent to improve the above technical problems. Utility Model Content

[0004] The present application provides a display panel and a display terminal to improve the technical problem that the current of a thin film transistor decreases within an operating voltage range, thereby affecting the charging capacity of the thin film transistor.

[0005] To solve the above technical problems, the technical solutions provided by this application are as follows:

[0006] The present application provides a display panel, the display panel comprising a substrate and a thin film transistor disposed on one side of the substrate, the thin film transistor comprising:

[0007] The active part includes a main body and edge parts arranged at two ends of the main body;

[0008] a gate insulating layer, disposed on one side of the active portion, the gate insulating layer comprising a first insulating portion disposed in alignment with the main portion and a second insulating portion disposed in alignment with the edge portion;

[0009] A gate is disposed on a surface of the gate insulating layer that is away from the active portion;

[0010] The orthographic projection of the second insulating portion on the substrate at least covers the orthographic projection of the edge portion on the substrate, and the gate oxide layer capacitance corresponding to the second insulating portion is smaller than the gate oxide layer capacitance corresponding to the first insulating portion.

[0011] In the display panel of the present application, the thickness of the second insulating portion is greater than the thickness of the first insulating portion.

[0012] In the display panel of the present application, the material of the second insulating portion is the same as the material of the first insulating portion, and the material of the first insulating portion and the second insulating portion are both one of silicon nitride, silicon oxide, and silicon oxynitride.

[0013] In the display panel of the present application, the second insulating part includes a stacked first sublayer and a second sublayer, the first insulating part includes a first sublayer, and the number of insulating layers included in the second insulating part is greater than the number of insulating layers included in the first insulating part.

[0014] In the display panel of the present application, the second sub-layer is arranged on a side of the first sub-layer close to the gate, and the dielectric constant of the second sub-layer is smaller than the dielectric constant of the first sub-layer.

[0015] In the display panel of the present application, the first sublayer and the second sublayer are made of the same material.

[0016] In the display panel of the present application, the materials of the first sub-layer and the second sub-layer are respectively different ones of silicon nitride, silicon oxide, and silicon oxynitride.

[0017] In the display panel of the present application, a surface of one side of the second insulating portion close to the gate includes a curved surface, and an orthographic projection of the curved surface on the substrate overlaps with an orthographic projection of the edge portion on the substrate.

[0018] In the display panel of the present application, the radius of curvature of the curved surface is 0.5 micrometers to 10 micrometers.

[0019] The present application also provides a display terminal, which includes the above-mentioned display panel.

[0020] Beneficial effects: The present application discloses a display panel and a display terminal. The display panel includes a substrate and a thin film transistor arranged on one side of the substrate, the thin film transistor includes an active part, a gate insulating layer and a gate, the active part includes a main body and edge parts arranged at both ends of the main body; the gate insulating layer is arranged on the surface of one side of the active part, the gate insulating layer includes a first insulating part arranged in alignment with the main body and a second insulating part arranged in alignment with the edge; the gate is arranged on the side of the gate insulating layer away from the active part; wherein the orthographic projection of the second insulating part on the substrate at least covers the orthographic projection of the edge part on the substrate, and the gate oxide layer capacitance corresponding to the second insulating part is smaller than the gate oxide layer capacitance corresponding to the first insulating part. The present application sets the gate oxide layer capacitance corresponding to the second insulating part to be smaller than the gate oxide layer capacitance corresponding to the first insulating part, so that the thin film transistor corresponding to the edge part is more difficult to turn on, thereby reducing the influence of the hump effect, increasing the current of the thin film transistor in the working range, and improving the charging capacity of the thin film transistor. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] The technical solution and other beneficial effects of the present application will be made apparent by describing in detail the specific implementation methods of the present application in conjunction with the accompanying drawings.

[0022] Figure 1 A schematic diagram of a top view structure of a display panel provided in an embodiment of the present application;

[0023] Figure 2 for Figure 1 A schematic diagram of an amplified structure of a thin film transistor;

[0024] Figure 3 for Figure 2 Schematic diagram of the cross-sectional structure at AA in the middle;

[0025] Figure 4 for Figure 2 A schematic diagram of a cross-sectional structure at BB;

[0026] Figure 5 for Figure 2 A schematic diagram of a cross-sectional structure at another location BB;

[0027] Figure 6 for Figure 2 A schematic diagram of a cross-sectional structure at another location BB;

[0028] Figure 7 A comparison diagram of the transfer characteristic curve of the embodiment of the present application and the transfer characteristic curve of the comparative example;

[0029] Figure 8 A schematic diagram of the structure of a display terminal provided in an embodiment of the present application.

[0030] Description of reference numerals:

[0031] Display panel 1, display area AA, non-display area NA, substrate 10, thin film transistor 20, active portion 21, source contact portion 211, drain contact portion 212, doped portion 213, channel portion 214, main portion 21a, edge portion 21b, gate insulating layer 22, first insulating portion 221, second insulating portion 222, first sublayer 2210, second sublayer 2220, gate 23, source 24, drain 25, shading portion 30, pixel electrode 40, first direction D1, second direction D2, display terminal 2, terminal body 3. DETAILED DESCRIPTION

[0032] The technical solutions in the embodiments of the present application will be described clearly and completely below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present application. In addition, it should be understood that the specific implementation methods described herein are only used to illustrate and explain the present application, and are not used to limit the present application. In the present application, unless otherwise stated, the directional words used, such as "upper" and "lower", generally refer to the upper and lower parts of the device in actual use or working state, specifically the drawing direction in the drawings; and "inside" and "outside" refer to the outline of the device.

[0033] The present application provides a display panel 1, such as Figures 1 to 4 As shown, the display panel 1 includes a substrate 10 and a thin film transistor 20 arranged on one side of the substrate 10, the thin film transistor 20 includes an active part 21, a gate insulating layer 22 and a gate 23, the active part 21 includes a main body 21a and edge parts 21b arranged at both ends of the main body 21a; the gate insulating layer 22 is arranged on one side of the active part 21, the gate insulating layer 22 includes a first insulating part 221 arranged in alignment with the main body 21a and a second insulating part 222 arranged in alignment with the edge part 21b; the gate 23 is arranged on the surface of the gate insulating layer 22 away from the active part 21; wherein the orthographic projection of the second insulating part 222 on the substrate 10 at least covers the orthographic projection of the edge part 21b on the substrate 10, and the gate oxide layer capacitance corresponding to the second insulating part 222 is smaller than the gate oxide layer capacitance corresponding to the first insulating part 221.

[0034] In this embodiment, the display panel 1 may be an LCD panel, an OLED panel, a Mini-LED panel, a Micro-LED panel, etc.

[0035] In this embodiment, the substrate 10 may be a rigid substrate or a flexible substrate. The material of the rigid substrate includes a glass substrate, a quartz substrate or a silicon wafer, etc., and the material of the flexible substrate includes one of colorless polyimide (PI), polycarbonate (PC), polynorbornene (PNB) and polyethylene terephthalate (PET), etc.

[0036] In this embodiment, the display panel 1 includes a display area AA and a non-display area NA disposed on at least one side of the display area AA. The display area AA is provided with a plurality of sub-pixels, and the display area AA is used to display images. The non-display area NA is provided with a gate drive circuit, etc., and the gate drive circuit is used to drive the sub-pixels of the display area AA. The thin film transistor 20 can be located in the display area AA or the non-display area NA, and this application does not limit this.

[0037] In this embodiment, the thin film transistor 20 includes an active portion 21. The material of the active portion 21 can be single crystal silicon, low temperature polysilicon, oxide semiconductor, etc.

[0038] In this embodiment, the active portion 21 may include a channel portion 214 and a source contact portion 211 and a drain contact portion 212 arranged at both ends of the channel portion 214, a doped portion 213 may be arranged between the source contact portion 211 and the channel portion 214, and a doped portion 213 may be arranged between the drain contact portion 212 and the channel portion 214.

[0039] The thin film transistor 20 includes a source electrode 24 and a drain electrode 25 . The source contact portion 211 is electrically connected to the source electrode 24 , and the drain contact portion 212 is electrically connected to the drain electrode 25 .

[0040] In this embodiment, if Figure 2 and Figure 3 As shown, the main body 21a of the active part 21 extends in the direction from the source 24 to the drain 25, and the main body 21a is arranged in the middle area of ​​the active part 21. For the convenience of description, the direction from the source 24 to the drain 25 is referred to as the first direction D1, and the direction arranged at an angle with the first direction D1 is referred to as the second direction D2. The first direction D1 can be perpendicular to the second direction D2 or at an acute angle. The main body 21a extends along the first direction D1, and one end of the main body 21a is electrically connected to the source 24, and the other end is electrically connected to the drain 25. The first direction D1 is the channel length direction.

[0041] like Figure 2 As shown, the edge portion 21b is disposed at both ends of the main body 21a, and the edge portion 21b also extends along the first direction D1, and the edge portion 21b is disposed in the edge area of ​​the active portion 21, and the edge area is disposed adjacent to the middle area. That is to say, the main body 21a and the edge portion 21b can be disposed in contact.

[0042] In this embodiment, the gate insulating layer 22 is disposed between the gate 23 and the active portion 21. The material of the gate insulating layer 22 can be a stack of one or more layers of silicon nitride, silicon oxide, silicon oxynitride, etc. The gate insulating layer 22 can be disposed as a whole layer or in a patterned manner. When the gate insulating layer 22 is disposed in a patterned manner, the gate insulating layer 22 at least covers the active portion 21.

[0043] The gate insulating layer 22 includes a first insulating portion 221 arranged in alignment with the main body 21a and a second insulating portion 222 arranged in alignment with the edge portion 21b. The alignment means that the first insulating portion 221 is substantially located directly above the main body 21a, and the second insulating portion 222 is substantially located directly above the edge portion 21b. The orthographic projection of the second insulating portion 222 on the substrate 10 at least covers the orthographic projection of the edge portion 21b on the substrate 10. That is to say, the second insulating portion 222 can completely cover the inclined surface of the edge portion 21b, or the second insulating portion 222 completely covers the inclined surface of the edge portion 21b and covers part of the area of ​​the main body 21a close to the edge portion 21b.

[0044] In this embodiment, the gate 23 is disposed on the surface of the gate insulating layer 22 on the side away from the substrate 10. The gate 23 may extend along the second direction D2. The orthographic projection of the gate 23 on the substrate 10 overlaps with the orthographic projection of the channel portion 214 on the substrate 10. The width of the gate 23 in the first direction D1 may be smaller than the width of the active portion 21 in the first direction D1. The orthographic projection of the gate 23 on the substrate 10 is disposed between the orthographic projections of the source contact portion 211 and the drain contact portion 212 on the substrate 10. That is to say, the orthographic projection of the gate 23 on the substrate 10 overlaps with the orthographic projection of the main portion 21a on the substrate 10, and the orthographic projection of the gate 23 on the substrate 10 overlaps with the orthographic projection of the edge portion 21b on the substrate 10.

[0045] It should be noted that the thin film transistor 20 may be a top-gate transistor or a bottom-gate transistor. The top-gate transistor is used as an example for introduction in the present application, which should not be construed as a limitation to the present application.

[0046] In this embodiment, the material of the gate 23 can be any one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd) and copper (Cu) or an alloy thereof.

[0047] The patterning process includes coating photoresist, exposure and development, etching, etc. Due to the influence of the patterning process, the side wall of the active portion 21 will form a cone angle with the bearing surface of the substrate 10. This causes the edge portion 21b to include an inclined surface, and the inclined surface is at an acute angle with the bearing surface of the substrate 10. The thickness of the edge portion 21b is less than the thickness of the main portion 21a, and the threshold voltage of the transistor corresponding to the edge portion 21b is less than the threshold voltage of the transistor corresponding to the main portion 21a, that is, the edge portion 21b is easier to turn on. Among them, the bearing surface of the substrate 10 refers to the side surface of the substrate 10 close to the thin film transistor 20. Thickness refers to the dimension in the direction perpendicular to the bearing surface of the substrate 10.

[0048] The characteristics of the transistor corresponding to the edge portion 21b are different from those of the transistor corresponding to the main portion 21a. The thin film transistor 20 can be regarded as a transistor corresponding to the edge portion 21b and a transistor corresponding to the main portion 21a connected in parallel, which produces a hump effect. The hump effect reduces the current of the thin film transistor 20 in the working range and reduces the charging capacity of the thin film transistor 20.

[0049] In this embodiment, the gate oxide capacitance corresponding to the second insulating portion 222 is the gate oxide capacitance of the transistor corresponding to the edge portion 21b, and the gate oxide capacitance corresponding to the first insulating portion 221 is the gate oxide capacitance of the transistor corresponding to the main portion 21a. In this embodiment, by setting the gate oxide capacitance corresponding to the second insulating portion 222 to be smaller than the gate oxide capacitance corresponding to the first insulating portion 221, it is more difficult to turn on the transistor corresponding to the edge portion 21b, thereby reducing the impact of the hump effect, increasing the current of the thin film transistor 20 in the working range, and improving the charging capacity of the circuit.

[0050] In this embodiment, if Figure 3 As shown, the display panel 1 includes a pixel electrode 40, and the pixel electrode 40 is electrically connected to the drain electrode 25. The thin film transistor 20 provides a driving voltage for the pixel electrode 40.

[0051] In this embodiment, if Figure 2 and Figure 3 As shown, the display panel 1 includes a light shielding portion 30, which is disposed on a side of the active portion 21 close to the substrate 10, and the orthographic projection of the channel portion 214 on the substrate 10 is located within the orthographic projection of the light shielding portion 30 on the substrate 10. The light shielding portion 30 is used to shield light incident from one side of the substrate 10 to prevent the light from affecting the electrical properties of the thin film transistor 20.

[0052] In the display panel 1 of the present application, Figures 4 to 6 As shown, the thickness of the second insulating portion 222 is greater than the thickness of the first insulating portion 221 .

[0053] In this embodiment, since the thickness of the second insulating portion 222 is greater than the thickness of the first insulating portion 221, the thickness of the medium in the gate oxide layer capacitor corresponding to the second insulating portion 222 is increased, thereby reducing the gate oxide layer capacitor corresponding to the second insulating portion 222, making it more difficult to turn on the transistor corresponding to the edge portion 21b, thereby reducing the impact of the hump effect, increasing the current of the thin film transistor 20 in the working range, and improving the charging capacity of the circuit.

[0054] In the display panel 1 of the present application, the material of the second insulating portion 222 is the same as that of the first insulating portion 221. For example, the materials of the first insulating portion 221 and the second insulating portion 222 may both be silicon oxide or the like. The gate insulating layer 22 may be formed by a film forming process, and the thickness of the gate insulating layer 22 formed by the film forming process is uniform. A groove is provided in the region of the gate insulating layer 22 corresponding to the main body 21a, thereby reducing the thickness of the gate insulating layer 22 corresponding to the main body 21a, and forming the first insulating portion 221. No groove is provided in the region corresponding to the second insulating portion 222, that is, the thickness of the second insulating portion 222 is equal to the thickness of the original gate insulating layer 22.

[0055] It should be understood that the groove is arranged corresponding to the main body 21a, that is, the orthographic projection of the side wall of the groove on the substrate 10 coincides with the orthographic projection of the main body 21a on the substrate 10, and the orthographic projection of the side wall of the groove on the substrate 10 does not overlap with the orthographic projection of the edge portion 21b on the substrate 10.

[0056] In the display panel 1 of the present application, Figure 5 As shown, the second insulating part 222 includes a stacked first sublayer 2210 and a second sublayer 2220 , the first insulating part 221 includes the first sublayer 2210 , and the number of insulating layers included in the second insulating part 222 is greater than the number of insulating layers included in the first insulating part 221 .

[0057] In this embodiment, the second insulating portion 222 may include two insulating layers, and the first insulating portion 221 may include one insulating layer, so that the thickness of the second insulating portion 222 is greater than the thickness of the first insulating portion 221. Through the above configuration, the gate oxide layer capacitance corresponding to the second insulating portion 222 is smaller than the gate oxide layer capacitance corresponding to the first insulating portion 221.

[0058] When the materials of the first sublayer 2210 and the second sublayer 2220 are the same, since the thickness of the second insulating portion 222 is greater than that of the first insulating portion 221 , the gate oxide capacitance corresponding to the second insulating portion 222 can be smaller than the gate oxide capacitance corresponding to the first insulating portion 221 .

[0059] When the materials of the first sublayer 2210 and the second sublayer 2220 are different, since the gate oxide layer capacitance corresponding to the second insulating part 222 is the capacitance of two layers of materials connected in series, the capacitance of the series capacitance is smaller than the capacitance of any one of the capacitances, thereby making the gate oxide layer capacitance corresponding to the second insulating part 222 smaller than the gate oxide layer capacitance corresponding to the first insulating part 221.

[0060] In the display panel 1 of the present application, the second sublayer 2220 is arranged on a side of the first sublayer 2210 close to the gate 23, and the dielectric constant of the second sublayer 2220 is smaller than the dielectric constant of the first sublayer 2210. The capacitance value of the capacitor is proportional to the dielectric constant, and through the above arrangement, the gate oxide layer capacitance corresponding to the second insulating portion 222 can be further reduced than the gate oxide layer capacitance corresponding to the first insulating portion 221.

[0061] In the display panel 1 of the present application, the first sublayer 2210 and the second sublayer 2220 are made of the same material. In this embodiment, the density of the second sublayer 2220 is less than that of the first sublayer 2210. For example, the materials of the first sublayer 2210 and the second sublayer 2220 may both be silicon oxide, the first sublayer 2210 may be dense silicon oxide, and the second sublayer 2220 may be loose silicon oxide. Dense silicon oxide has a high dielectric constant, and loose silicon oxide has a low dielectric constant, so that the gate oxide layer capacitance corresponding to the second insulating portion 222 is smaller than the gate oxide layer capacitance corresponding to the first insulating portion 221.

[0062] In the display panel 1 of the present application, the first sublayer 2210 and the second sublayer 2220 are made of different materials. For example, the material of the first sublayer 2210 may be silicon nitride, and the material of the second sublayer 2220 may be silicon oxide. Alternatively, the material of the first sublayer 2210 may be silicon oxide, and the material of the second sublayer 2220 may be silicon nitride.

[0063] When the materials of the first sublayer 2210 and the second sublayer 2220 are different, the gate oxide layer capacitance corresponding to the second insulating portion 222 is equivalent to two capacitors connected in series, the first sublayer 2210 and the second sublayer 2220 correspond to one of the capacitors respectively, and the capacitance of the capacitor connected in series is smaller than the capacitance of any one of the capacitors. The gate oxide layer capacitance corresponding to the first insulating portion 221 is the capacitance corresponding to the first sublayer 2210, therefore, the gate oxide layer capacitance corresponding to the second insulating portion 222 is smaller than the gate oxide layer capacitance corresponding to the first insulating portion 221.

[0064] Optionally, in this embodiment, the dielectric constant of the first sublayer 2210 is greater than the dielectric constant of the second sublayer 2220, thereby further reducing the gate oxide layer capacitance corresponding to the second insulating portion 222, making it more difficult to turn on the transistor corresponding to the edge portion 21b, and further improving the hump effect.

[0065] It should be noted that by setting the materials of the first sublayer 2210 and the second sublayer 2220 to be different, the etching characteristics of different materials are different, and it is easier to control the etching selectivity in the patterning process. That is to say, when etching one layer of material, the etching rate of the other layer of material is very small and is not easily etched, thereby improving the accuracy of patterning.

[0066] In the display panel 1 of the present application, Figure 6 As shown, a surface of one side of the second insulating portion 222 close to the gate 23 includes a curved surface, and the orthographic projection of the curved surface on the substrate 10 overlaps with the orthographic projection of the edge portion 21 b on the substrate 10 .

[0067] In this embodiment, the arc surface has a smoother transition than the plane surface, which avoids the concentration of electric field lines at the interface between the second insulating portion 222 and the gate 23, and has a better effect on improving the hump effect. At the same time, the arc surface can also reduce stress concentration, avoid disconnection of the gate 23 and cracks in the second insulating portion 222, and improve the yield.

[0068] In this embodiment, the curvature radius of the arc surface may be 0.5 micrometers to 10 micrometers. If the curvature radius is too small, a smooth transition will not be achieved, while if the curvature radius is too large, the space occupied by the second insulating portion 222 will be increased.

[0069] Exemplarily, the radius of curvature of the curved surface can be 0.5 microns, 1 micron, 1.5 microns, 2 microns, 2.5 microns, 3 microns, 3.5 microns, 4 microns, 4.5 microns, 5 microns, 5.5 microns, 6 microns, 6.5 microns, 7 microns, 7.5 microns, 8 microns, 8.5 microns, 9 microns, 9.5 microns, 10 microns, etc.

[0070] In order to illustrate the effect of the embodiment of the present application, the inventor proposes a comparative example. The difference between the comparative example and the embodiment of the present application is that the gate 23 insulating layer of the comparative example has a uniform thickness, that is, the thickness of the gate 23 insulating corresponding body portion 21a and edge portion 21b is the same. Figure 7 The figure is a comparison of the transfer characteristic curve of the thin film transistor of the embodiment of the present application and the transfer characteristic curve of the thin film transistor of the comparative example. The horizontal axis is the gate voltage Vgs of the thin film transistor 20, in volts; the vertical axis is the logarithmic form of the source-drain current Ids of the thin film transistor 20, in amperes. Among them, curve S1, curve S2, and curve S3 are the transfer curves of the thin film transistor when Vd is 0.1 volts, and curve S4, curve S5, and curve S6 are the transfer curves of the thin film transistor when Vd is 10 volts. Curves S1 and curve S4 are the transfer curves of the comparative example, and curves S2 and curve S5 are Figure 4 The transfer curves of the embodiment, curve S3 and curve S6 are Figure 6 Transfer curves of the embodiments in FIG.

[0071] The operating range of the thin film transistor 20 is the range between the two dotted lines in the figure, that is, the operating voltage of the thin film transistor 20 is between 2V and 5V. Figure 7It can be seen that within the working range, the curves S1 and S4 of the comparative example are concave downward, that is, the current decreases, resulting in a decrease in charging capacity. However, within the working range, the concave degree of the curves S2, S3, S5 and S6 of the embodiment is improved, that is, the current increases, improving the charging capacity.

[0072] That is to say, compared with the curve S1 and curve S4 of the comparative example, the thin film transistor 20 of the embodiment of the present application has a larger current in the working interval, which improves the charging capacity of the circuit. In the embodiment, the current increase in the working interval of curve S3 and curve S6 is greater than that of another embodiment, which can further improve the charging capacity of the circuit. Curve S3 and curve S6 correspond to Figure 6 The embodiment shows that setting an arc surface has a better effect on improving the hump effect.

[0073] like Figure 8 As shown, the present application also provides a display terminal 2, and the display terminal 2 includes the above-mentioned display panel 1.

[0074] In this embodiment, if Figure 8 As shown, the display terminal 2 includes a display panel 1 and a terminal body 3, and the display panel 1 and the terminal body 3 are combined into one body.

[0075] In this embodiment, the display terminal 2 can be any product or component with a display function, such as a mobile phone, a tablet computer, a television, a monitor, a laptop computer, a digital photo frame, a navigator, etc.

[0076] In the above embodiments, the description of each embodiment has its own emphasis. For parts that are not described in detail in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0077] The display panel and display terminal provided in the embodiments of the present application are introduced in detail above. Specific examples are used in this article to illustrate the principles and implementation methods of the present application. The description of the above embodiments is only used to help understand the technical solutions and core ideas of the present application. Ordinary technicians in this field should understand that they can still modify the technical solutions recorded in the aforementioned embodiments, or replace some of the technical features therein with equivalents; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A display panel, characterized in that: The invention comprises a substrate and a thin film transistor arranged on one side of the substrate, wherein the thin film transistor comprises: The active part includes a main body and edge parts arranged at two ends of the main body; a gate insulating layer, disposed on one side of the active portion, the gate insulating layer comprising a first insulating portion disposed in alignment with the main portion and a second insulating portion disposed in alignment with the edge portion; A gate, disposed on a surface of the gate insulating layer facing away from the active portion; The orthographic projection of the second insulating portion on the substrate at least covers the orthographic projection of the edge portion on the substrate, and the gate oxide layer capacitance corresponding to the second insulating portion is smaller than the gate oxide layer capacitance corresponding to the first insulating portion.

2. The display panel according to claim 1, characterized in that: The second insulating portion has a thickness greater than that of the first insulating portion.

3. The display panel according to claim 2, characterized in that: The material of the second insulating portion is the same as that of the first insulating portion, and the material of the first insulating portion and the second insulating portion are both one of silicon nitride, silicon oxide, and silicon oxynitride.

4. The display panel according to claim 2, characterized in that: The second insulating portion includes a first sublayer and a second sublayer that are stacked, the first insulating portion includes a first sublayer, and the number of insulating layers included in the second insulating portion is greater than the number of insulating layers included in the first insulating portion.

5. The display panel according to claim 4, characterized in that: The second sub-layer is disposed on a side of the first sub-layer close to the gate, and the dielectric constant of the second sub-layer is smaller than the dielectric constant of the first sub-layer.

6. The display panel according to claim 5, characterized in that: The first sub-layer and the second sub-layer are made of the same material.

7. The display panel according to claim 4, characterized in that: The materials of the first sub-layer and the second sub-layer are respectively different ones of silicon nitride, silicon oxide, and silicon oxynitride.

8. The display panel according to any one of claims 1 to 7, characterized in that: A surface of one side of the second insulating portion close to the gate comprises a curved surface, and an orthographic projection of the curved surface on the substrate overlaps with an orthographic projection of the edge portion on the substrate.

9. The display panel according to claim 8, characterized in that: The curvature radius of the arc surface is 0.5 micrometers to 10 micrometers.

10. A display terminal, characterized in that: The display terminal comprises the display panel according to any one of claims 1 to 9.

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