Silicon carbide device

Abstract

The utility model provides a silicon carbide device which comprises a substrate, a contact region, an interlayer dielectric layer and a metal silicide layer, an epitaxial layer is formed on the substrate, and a source region and a drain region which are arranged at an interval are formed in the epitaxial layer; the contact region is located in the epitaxial layer between the source region and the drain region and is in contact with the source region and the drain region, and the top surface of the contact region is lower than the top surfaces of the source region and the drain region; the interlayer dielectric layer is located on the epitaxial layer, a contact hole is formed in the interlayer dielectric layer and is aligned with the contact region, and the bottom of the contact hole is lower than the top surfaces of the source region and the drain region, so that the top surface and the side wall of the source region in the contact hole and the top surface and the side wall of the drain region form steps; therefore, the contact area between the metal silicide layer and the source region and the drain region can be increased, namely, the metal silicide layer can be in contact with the side walls and the top surfaces of the source region and the drain region, so that the contact voltage between the metal silicide layer and the contact hole can be reduced, and the performance of the device is improved.

Description

Technical Field

[0001] The utility model relates to the technical field of semiconductors, in particular to a silicon carbide device. Background Art

[0002] Silicon carbide power devices are also called power electronic devices. Since SiC (silicon carbide) has a high critical electric field, high thermal conductivity and high saturation drift rate, silicon carbide power devices are mainly used in high-power electronic devices for power equipment power conversion and control circuits, including power diodes, power triodes, thyristors, field effect transistors, insulated gate bipolar transistors, etc. Silicon carbide power components have a far-reaching impact in the medium and high voltage fields above 1000V. The main application areas include electric vehicles, charging piles, photovoltaic new energy, rail transportation, smart grids, etc. As the design size of silicon carbide devices gradually decreases, the size of the contact holes in silicon carbide devices also continues to decrease, which eventually leads to an increase in the contact resistance between the contact holes and the metal silicide layer. The increase in contact resistance has a very adverse effect on the performance of the device, such as an increase in threshold voltage, an increase in on-resistance, and easy heating. Utility Model Content

[0003] The utility model aims to provide a silicon carbide device to reduce the contact resistance between a contact hole and a metal silicide layer.

[0004] To achieve the above object, the utility model provides a silicon carbide device, comprising:

[0005] A substrate, on which an epitaxial layer is formed, wherein a source region and a drain region are formed in the epitaxial layer.

[0006] A contact region, the contact region is located in the epitaxial layer between the source region and the drain region and is in contact with the source region and the drain region, and a top surface of the contact region is lower than top surfaces of the source region and the drain region;

[0007] an interlayer dielectric layer, located on the epitaxial layer, wherein the interlayer dielectric layer has a contact hole, wherein the contact hole is aligned with the contact region, wherein the bottom of the contact hole is lower than the top surface of the source region and the drain region, and wherein the top surface and side wall of the source region and the top surface and side wall of the drain region in the contact hole form steps;

[0008] A metal silicide layer covers the sidewall and the bottom of the contact hole.

[0009] Optionally, in the silicon carbide device, at least two well regions spaced apart are formed in the epitaxial layer, and the source region and the drain region are respectively located in two adjacent well regions.

[0010] Optionally, in the silicon carbide device, the conductivity type of the source region is the same as the conductivity type of the drain region.

[0011] Optionally, in the silicon carbide device, the conductivity type of the source region and the conductivity type of the drain region are both N-type.

[0012] Optionally, in the silicon carbide device, the conductivity type of the well region is the same as the conductivity type of the contact region.

[0013] Optionally, in the silicon carbide device, the conductivity type of the well region and the conductivity type of the contact region are both P-type.

[0014] Optionally, in the silicon carbide device, the silicon carbide device further includes:

[0015] A gate oxide layer is located on the epitaxial layer and covers the epitaxial layer, a portion of the well region, a portion of the source region and a portion of the drain region.

[0016] Optionally, in the silicon carbide device, the silicon carbide device further includes:

[0017] The gate layer is located on the gate oxide layer, and the interlayer dielectric layer also extends to cover the gate layer.

[0018] Optionally, in the silicon carbide device, the silicon carbide device further includes:

[0019] A conductive layer is located on the metal silicide layer and fills the contact hole.

[0020] Optionally, in the silicon carbide device, the material of the epitaxial layer and the material of the substrate are both silicon carbide.

[0021] In the silicon carbide device provided by the utility model, the silicon carbide device includes a substrate, a contact region, an interlayer dielectric layer and a metal silicide layer, an epitaxial layer is formed on the substrate, and a source region and a drain region are formed in the epitaxial layer; the contact region is located in the epitaxial layer between the source region and the drain region and is in contact with the source region and the drain region, and the top surface of the contact region is lower than the top surface of the source region and the drain region; the interlayer dielectric layer is located on the epitaxial layer, and a contact hole is provided in the interlayer dielectric layer, the contact hole is aligned with the contact region, and the bottom of the contact hole is lower than the top surface of the source region and the drain region , so that the top surface and side wall of the source region and the top surface and side wall of the drain region in the contact hole all form steps; the metal silicide layer covers the side wall and bottom of the contact hole; because the top surface and side wall of the source region and the top surface and side wall of the drain region in the contact hole all form steps, the contact area between the metal silicide layer and the source region and the drain region can be increased, that is, the metal silicide layer can be in contact with the side wall and top surface of the source region and the drain region, thereby reducing the contact voltage between the metal silicide layer and the contact hole, and improving the performance of the device. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] Figure 1 It is a schematic diagram of the cross-sectional structure of a silicon carbide device according to an embodiment of the utility model;

[0023] Figure 2 It is a schematic flow chart of a method for manufacturing a silicon carbide device according to an embodiment of the utility model;

[0024] Figure 3 to Figure 19 It is a schematic diagram of the structure formed in the method for manufacturing a silicon carbide device according to an embodiment of the utility model;

[0025] The following are the descriptions of the reference numerals:

[0026] 100 - substrate; 101 - epitaxial layer; 102 - well region; 103 - source region; 104 - drain region; 105 - groove; 106 - contact region; 110 - insulating layer; 111 - first hard mask layer;

[0027] 120 - first patterned photoresist layer; 121 - first opening; 122 - sidewall;

[0028] 130 - a second hard mask layer;

[0029] 140 - a second patterned photoresist layer; 141 - a second opening;

[0030] 142-self-aligned barrier layer;

[0031] 150-protective layer;

[0032] 160-gate oxide layer; 170-gate layer;

[0033] 180- a third patterned photoresist layer;

[0034] 181-the third opening;

[0035] 190 - interlayer dielectric layer; 191 - contact hole; 191a - upper contact hole; 191b - lower contact hole; 191c - step;

[0036] 200 - patterned mask layer; 210 - metal silicide layer; 220 - conductive layer. DETAILED DESCRIPTION

[0037] The silicon carbide device proposed by the utility model is further described in detail below in combination with the accompanying drawings and specific embodiments. According to the following description, the advantages and features of the utility model will be more clear. It should be noted that the accompanying drawings are all in a very simplified form and are not in precise proportions, which are only used to conveniently and clearly assist in explaining the purpose of the embodiments of the utility model.

[0038] As used in the present invention, the singular forms "one", "an", and "the" include plural objects, the term "or" is usually used to include the meaning of "and / or", the term "several" is usually used to include the meaning of "at least one", and the term "at least two" is usually used to include the meaning of "two or more". In addition, the terms "first", "second", and "third" are used only for descriptive purposes and cannot be understood as indicating or implying relative importance or implicitly indicating the number of indicated technical features. Therefore, the features defined as "first", "second", and "third" may explicitly or implicitly include one or at least two of the features.

[0039] Figure 1 Schematic diagram of the cross-sectional structure of the silicon carbide device provided by the embodiment of the utility model. Figure 1 As shown, this embodiment provides a silicon carbide device, including a substrate 100, a contact region 106, an interlayer dielectric layer 190 and a metal silicide layer 210. An epitaxial layer 101 is formed on the substrate 100, and the material of the substrate 100 and the epitaxial layer 101 are both silicon carbide (SiC).

[0040] like Figure 1 As shown, a source region 103 and a drain region 104 are formed in the epitaxial layer 101. Further, at least two well regions 102 are formed in the epitaxial layer 101, and the source region 103 and the drain region 104 are respectively located in two adjacent well regions 102. The conductivity type of the source region 103 is the same as the conductivity type of the drain region 104. The conductivity types of the source region 103 and the drain region 104 are both N-type. The conductivity type of the well region 102 is the same as the conductivity type of the contact region 106. The conductivity types of the well region 102 and the contact region 106 are both P-type.

[0041] The top surfaces of the source region 103 , the drain region 104 and the well region 102 are flush, and the source region 103 , the drain region 104 and the well region 102 all extend from the top surface of the epitaxial layer 101 into the epitaxial layer 101 .

[0042] The source region 103 is located in the well region 102 , wherein the bottom of the source region 103 is higher than the bottom of the well region 102 , and a side wall (or edge) of the source region 103 may overlap with a side wall of the well region 102 .

[0043] The drain region 104 is located in the well region 102 , wherein the bottom of the drain region 104 is higher than the bottom of the well region 102 , and a side wall of the drain region 104 may overlap with a side wall of the well region 102 .

[0044] The contact region 106 is located in the epitaxial layer 101 between the source region 103 and the drain region 104 and contacts the source region 103 and the drain region 104. The top surface of the contact region 106 is lower than the top surfaces of the source region 103 and the drain region 104. In this way, the contact area between the contact hole 191 and the metal silicide is increased. Furthermore, the bottom of the contact region 106 can be lower than the bottom of the well region 102.

[0045] In this embodiment, the metal silicide layer 210 covers the sidewalls and bottom of the contact hole 191. Since the top surface and sidewalls of the source region 103 and the top surface and sidewalls of the drain region 104 in the contact hole 191 form a step 191c, the contact area between the metal silicide layer 210 and the source region 103 and the drain region 104 can be increased, that is, the metal silicide layer 210 can be in contact with the sidewalls and top surfaces of the source region 103 and the drain region 104, thereby reducing the contact voltage between the metal silicide layer 210 and the contact hole 191 and improving the performance of the device. The material of the metal silicide layer 210 can be, for example, nickel silicon.

[0046] In addition, the silicon carbide device further includes a gate oxide layer 160, which is located on the epitaxial layer 101 and covers the epitaxial layer 101, part of the well region 102, part of the source region 103, and part of the drain region 104. The material of the gate oxide layer 160 may be, for example, silicon oxide, and the gate oxide layer 160 is used to isolate the epitaxial layer 101 from the gate layer 170.

[0047] like Figure 1As shown, the silicon carbide device further includes a gate layer 170, the gate layer 170 is located on the gate oxide layer 160, and the interlayer dielectric layer 190 also extends to cover the gate layer 170. The gate layer 170 may be made of doped polysilicon.

[0048] Figure 2 Schematic diagram of the process of manufacturing a silicon carbide device according to an embodiment of the present utility model. Figure 2 As shown, this embodiment also provides a method for manufacturing a silicon carbide device, comprising:

[0049] Step S1: providing a substrate, on which an epitaxial layer is formed, and in which a source region and a drain region are formed at intervals;

[0050] Step S2: etching a portion of the epitaxial layer to form a groove, wherein the groove is located between the source region and the drain region, and the bottom of the groove is lower than the top surface of the source region and the drain region;

[0051] Step S3: performing ion implantation on the epitaxial layer at the bottom of the groove to form a contact region, wherein the contact region is in contact with the source region and the drain region, and a top surface of the contact region is lower than a top surface of the source region and the drain region;

[0052] Step S4: forming an interlayer dielectric layer and a patterned mask layer in sequence, wherein the interlayer dielectric layer fills the groove and extends to cover the epitaxial layer, and the patterned mask layer exposes a portion of the interlayer dielectric layer on the contact area;

[0053] Step S5: etching the interlayer dielectric layer using the patterned mask layer as a mask to form a contact hole, wherein the contact hole is aligned with the contact region, and the top surface and sidewall of the source region and the top surface and sidewall of the drain region in the contact hole both form steps; and,

[0054] Step S6: forming a metal silicide layer, wherein the metal silicide layer covers the sidewall and the bottom of the contact hole.

[0055] Figure 3 to Figure 19 The structure diagram formed in the method for manufacturing the silicon carbide device according to the embodiment of the utility model is shown in FIG. The method for manufacturing the silicon carbide device according to the embodiment of the utility model will be described in more detail below in conjunction with the accompanying drawings.

[0056] First, if Figure 3 Combined with Figure 7 As shown, step S1 is performed to provide a substrate 100, on which an epitaxial layer 101 is formed, and in which a source region 103 and a drain region 104 are formed at intervals. Specifically, as Figure 3As shown, a substrate 100 may be provided first, and the material of the substrate 100 may be silicon carbide; then, as shown in FIG. Figure 3 As shown, an epitaxial process is performed on the substrate 100 to form the epitaxial layer 101 . The material of the epitaxial layer 101 may be silicon carbide, that is, the material of the epitaxial layer 101 is the same as that of the substrate 100 .

[0057] Then, if Figure 6 As shown, an ion implantation process is performed on the epitaxial layer 101 to form a well region 102. In this embodiment, P-type ion implantation is performed on the epitaxial layer 101 to obtain a well region 102 with a P-type conductive line.

[0058] Specifically, the method for forming the well region 102 includes: first, Figure 4 As shown, an insulating layer 110, a first hard mask layer 111 and a first patterned photoresist layer 120 are sequentially formed on the epitaxial layer 101, and the patterned photoresist layer 120 exposes a portion of the first hard mask layer 111. The material of the first hard mask layer 111 can be silicon nitride, which can be formed by a chemical vapor deposition process. The material of the insulating layer 110 can be silicon oxide, which can be formed by a thermal oxidation process.

[0059] Then, if Figure 5 As shown, the first hard mask layer 111 is etched with the first patterned photoresist layer 120 to form a first opening 121, and the first opening 121 exposes a portion of the insulating layer 110. In this embodiment, the first hard mask layer 111 at the bottom of the first opening 121 can be etched by a dry etching process to form the first opening 121. The insulating layer at the bottom of the first opening 121 can protect the epitaxial layer 101 and prevent the subsequent ion implantation from damaging the epitaxial layer 101; then, as shown in FIG. Figure 6 As shown, the first patterned photoresist layer 120 is continued to be used as a mask to perform ion implantation on the exposed epitaxial layer 101 below the insulating layer 110 to form at least two well regions 102 spaced apart from each other; then, as shown Figure 7 As shown, the first patterned photoresist layer 120 is removed, wherein the first patterned photoresist layer 120 can be removed by an ashing process.

[0060] Continue to refer Figure 7 , forming a sidewall 122, the sidewall 122 covers the sidewall and top surface of the first opening 121. The sidewall 122 may be made of silicon oxide, silicon nitride, or a stacked structure of silicon oxide and silicon nitride, and the sidewall 122 may be used as a mask for ion implantation when subsequently forming the source region 103 and the drain region 104.

[0061] Afterwards, if Figure 7 As shown, the well region 102 at the bottom of the first opening 121 is ion-implanted using the sidewall 122 and the first hard mask layer 111 as masks to form the source region 103 and the drain region 104, wherein the source region 103 and the drain region 104 are respectively located in two adjacent well regions 102. Specifically, the source region 103 may be located in one well region 102, wherein the bottom of the source region 103 is higher than the bottom of the well region 102, and a side wall (or edge) of the source region 103 may overlap with a side wall of the well region 102. The drain region 104 may be located in another well region 102, wherein the bottom of the drain region 104 is higher than the bottom of the well region 102, and a side wall (or edge) of the drain region 104 may overlap with a side wall of the well region 102.

[0062] In this embodiment, the conductivity type of the well region 102 and the contact region 106 is P type, and the conductivity type of the source region 103 and the drain region 104 is N type.

[0063] After forming the source region 103 and the drain region 104, the spacer 122 and the first hard mask layer 111 are removed to expose the insulating layer 110. The spacer 122 and the first hard mask layer 111 may be removed by an ashing process or a wet cleaning method.

[0064] Next, refer to Fig. 9 , performing step S2, etching a portion of the epitaxial layer 101 to form a groove 105, wherein the groove 105 is located between the source region 103 and the drain region 104, and the bottom of the groove 105 is lower than the top surface of the source region 103 and the drain region 104. The depth of the groove may be 0.1 μm to 0.3 μm, for example, 0.1 μm, 0.2 μm or 0.3 μm.

[0065] Specifically, the method for etching the partial thickness of the epitaxial layer 101 includes: first, as Figure 8 As shown, a second hard mask layer 130 and a second patterned photoresist layer 140 are sequentially formed on the epitaxial layer 101, and a second opening 141 is provided in the second patterned photoresist layer 140. The second opening 141 is aligned with the epitaxial layer 101 between the source region 103 and the drain region 104, and the second opening exposes a portion of the second hard mask layer 130. The material of the second hard mask layer 130 may be silicon nitride, and may be formed by a chemical vapor deposition process. The width of the second opening 141 may be equal to the spacing between the source region 103 and the drain region 104, so that the sidewalls of the groove formed subsequently can be adjacent to the sidewalls of the source region and the drain region.

[0066] Then, if Fig. 9 As shown, the second patterned photoresist layer 140 is used as a mask to sequentially etch the exposed second hard mask layer 130 and the epitaxial layer 101 to form the groove 105, wherein the groove 105 exposes the sidewalls of the source region 103 and the drain region 104. Furthermore, the groove 105 penetrates a portion of the epitaxial layer, that is, the bottom of the groove 105 is lower than the top surface of the source region 103 and the top surface of the drain region 104, and the bottom of the groove 105 is higher than the bottom of the source region 103 and the bottom of the drain region 104. When etching the epitaxial layer 101, since the width of the second opening 141 in the second patterned photoresist layer 140 is equal to the spacing between the source region 103 and the drain region 104, the width of the groove 105 can be made equal to the spacing between the source region 103 and the drain region 104, thereby exposing the sidewalls of the source region 103 and the drain region 104. The exposed second hard mask layer 130 and the epitaxial layer 101 may be sequentially etched using an anisotropic etching process, and the anisotropic etching process may be, for example, a plasma etching process.

[0067] Next, refer to Fig.11 , step S3 is performed to perform ion implantation on the epitaxial layer 101 at the bottom of the groove 105 to form a contact region 106, wherein the contact region 106 is in contact with the source region 103 and the drain region 104, that is, one side wall (or surface) of the contact region 106 overlaps with one side wall of the source region 103, and the other side wall of the contact region 106 overlaps with one side wall of the drain region 104. And the top surface of the contact region 106 is lower than the top surfaces of the source region 103 and the drain region 104.

[0068] In this embodiment, the method for forming the contact area 106 includes: first, referring to Fig.10 , forming a self-aligned barrier layer 142, the self-aligned barrier layer 142 covers the sidewall and bottom of the groove 105, and the material of the self-aligned barrier layer 142 can be silicon oxide. The self-aligned barrier layer 142 can protect the surface of the epitaxial layer 101 from damage during the subsequent ion implantation process, reduce the direct impact of ions on the surface of the epitaxial layer 101, thereby reducing the risk of surface damage, and can further improve the distribution and depth of ions in the subsequent contact area 106 in the epitaxial layer 101, which is conducive to achieving a more accurate doping effect. Among them, the self-aligned barrier layer 142 is formed by a self-aligned process without using an additional photolithography process.

[0069] Then, if Fig.11As shown, the epitaxial layer 101 at the bottom of the self-aligned barrier layer 142 is continuously ion-implanted using the second patterned photoresist layer 140 as a mask to form the contact region 106, the conductivity type of the contact region 106 being P type, wherein the ions doped in the contact region 106 may include, for example, aluminum ions. In addition, when ion implantation is performed on the epitaxial layer 101 at the bottom of the self-aligned barrier layer 142, the second patterned photoresist layer 140 is used as a mask, i.e., the ion implantation process performed when forming the contact region 106 may use the mask used when forming the groove 105 in the previous process, that is, the ion implantation process performed when forming the contact region 106 and the etching process used when forming the groove 105 in the previous process use the same mask (i.e., the second patterned photoresist layer 140), so no additional photolithography process is used, and no additional photomask is required.

[0070] Then, if Fig.12 As shown, the second patterned photoresist layer 140 and the second hard mask layer 130 are removed in sequence to expose the epitaxial layer 101, the source region 103 and the drain region 104. Here, the second patterned photoresist layer 140 and the second hard mask layer 130 may be removed by a wet cleaning process or an ashing process.

[0071] Then, if Fig.13 As shown, a protective layer 150 is formed, and the protective layer 150 fills the groove 105 and extends to cover the epitaxial layer 101, the source region 103 and the drain region 104. The material of the protective layer 150 can be carbon, and the protective layer 105 is used to protect the source region 103, the drain region 104 and the contact region 106 in the subsequent annealing process. The annealing process is performed to diffuse the ions in the source region, the drain region and the contact region, and in addition, the lattice defects of the epitaxial layer can be repaired. In addition, due to the existence of the protective layer 150, the source region 103, the drain region 104 and the contact region 106 can be protected to prevent the ions in the source region 103, the drain region 104 and the contact region 106 from diffusing out of the epitaxial layer 101; and the protective layer is removed by a dry etching process or a wet etching process.

[0072] Afterwards, if Fig.14 As shown, a gate oxide layer 160 and a gate layer 170 are formed in sequence, the gate oxide layer 160 covers the epitaxial layer 101, the source region 103, the drain region 104, the well region 102 and the self-aligned barrier layer 142, and the gate layer 170 covers the contact region 106 and extends to cover the gate oxide layer 160. Specifically, the material of the gate oxide layer 160 can be silicon oxide, and the gate oxide layer 160 can be formed by a thermal oxidation process or a chemical vapor deposition process. The material of the gate layer 170 can be doped polysilicon.

[0073] Then, if Fig.15 As shown, a third patterned photoresist layer 180 is formed on the gate layer 170, and the third patterned photoresist layer 180 exposes a portion of the gate layer 170, that is, the gate layer 170 on the contact area 106 and a portion of the gate layer 170 on the source area 103; and,

[0074] Continue to refer Fig.15 , the exposed gate layer 170 is etched using the third patterned photoresist layer 180 as a mask to form a third opening 181, wherein the third opening 181 is aligned with the contact area 106, and the width of the third opening 181 is greater than the width of the contact area 106, so as to expose the gate oxide layer 160 on the contact area 106, and expose part of the gate oxide layer 160 on the source area 103 and the drain area 104. Here, the gate layer 170 can be exposed by an anisotropic dry etching process.

[0075] Next, refer to Fig.16 Combined with Fig.17 , executing step S4, sequentially forming an interlayer dielectric layer 190 and a patterned mask layer 200, wherein the interlayer dielectric layer 190 fills the groove 105 and extends to cover the epitaxial layer 101, and the patterned mask layer 200 exposes a portion of the interlayer dielectric layer 190 on the contact area 106. In this embodiment, the interlayer dielectric layer 190 can be formed by a chemical vapor deposition process, such as an enhanced plasma high-density chemical vapor deposition process.

[0076] In this embodiment, the interlayer dielectric layer 190 extends to cover the exposed top surface of the gate oxide layer 160 and the gate.

[0077] In this embodiment, the patterned mask layer 200 can be a patterned photoresist layer, and the patterned photoresist layer has a groove, which exposes a portion of the interlayer dielectric layer 190 on the contact area 106. Furthermore, the width of the groove can be greater than the width of the contact area 106. In this way, the contact hole 191 formed subsequently can expose part of the side walls of the source area 103 and the drain area 104.

[0078] Next, refer to Fig.18, step S5 is performed, the interlayer dielectric layer 190 is etched using the patterned mask layer 200 as a mask to form a contact hole 191, the contact hole 191 is aligned with the contact region 106, and the top surface and side wall of the source region 103 and the top surface and side wall of the drain region 104 in the contact hole 191 form a step 191c. Specifically, the contact hole includes an upper contact hole 191a and a lower contact hole 191b that are connected, the width of the upper contact hole 191a is greater than the width of the lower contact hole 191b, so that 191a is formed between the upper contact hole 191a and the lower contact hole 191b, wherein the lower contact hole 191b is located between the source region and the drain region.

[0079] Specifically, the interlayer dielectric layer 190 may be etched by an anisotropic dry etching process. Furthermore, after etching the interlayer dielectric layer 190 using the patterned hard mask layer 200 as a mask, the gate oxide layer 160 and the self-aligned barrier layer 142 are sequentially etched to expose the contact region 106, part of the sidewall and part of the top surface of the source region 103, and part of the sidewall and part of the top surface of the drain region 104. During the etching process, the interlayer dielectric layer 190, the gate oxide layer 160, and the self-aligned barrier layer 142 are etched by an etching gas, and the etching gas molecules or ions react chemically with the interlayer dielectric layer 190, the gate oxide layer 160, and the self-aligned barrier layer 142, thereby achieving etching. During the etching process, the anisotropic dry etching process may use an etching gas with a relatively high etching selectivity for the interlayer dielectric layer and the epitaxial layer. In this way, during the etching process, the upper contact hole 191a is formed first. After the upper contact hole 191a is formed, the interlayer dielectric layer 190, the gate oxide layer 160 and the self-aligned barrier layer 142 can be further etched downward to form a lower contact hole 191b. During the etching of the interlayer dielectric layer 190, the gate oxide layer 160 and the self-aligned barrier layer 142, the etching amount of the source region or the drain region is small or almost no etching occurs, thereby forming a step between the upper contact hole 191a and the lower contact hole 191b.

[0080] In this embodiment, the anisotropic dry etching process can use fluorine-containing gases, such as carbon tetrafluoride (CF4) and sulfur hexafluoride (SF6). These gases can react with silicon oxide in a plasma environment to generate volatile fluorides, thereby achieving efficient etching of the interlayer dielectric layer and making the etching rate of the source region or the drain region relatively low, thereby achieving a higher etching selectivity ratio.

[0081] In this embodiment, since the top surface and side wall of the source region 103 and the top surface and side wall of the drain region 104 in the contact hole 191 form a step 191c, that is, not only the top surface of the source region 103 and the drain region 104 are exposed in the contact hole 191, but also part of the side surface of the source region 103 and the drain region 104 are exposed, the effective area of ​​the contact hole can be increased, thereby increasing the contact area between the subsequently formed metal silicide layer 210 and the contact hole 191. In addition, there is no need to add an additional mask or mask layer to increase the effective area of ​​the contact hole, and the effective area of ​​the contact hole can be easily increased only by improving the front-end process. That is to say, in this embodiment, while increasing the effective area of ​​the contact hole, there is no need to add an additional mask or mask layer.

[0082] Next, refer to Fig.19 , forming a metal silicide layer 210, the metal silicide layer 210 covers the sidewalls and bottom of the contact hole 191. Since the top surface and sidewalls of the source region 103 and the top surface and sidewalls of the drain region 104 in the contact hole 191 form steps 191c, the contact area between the metal silicide layer 210 and the source region 103 and the drain region 104 can be increased, that is, the contact area between the metal silicide layer 210 and the sidewalls and bottom of the contact hole 191 is increased, so that the metal silicide layer 210 can contact the sidewalls and top surfaces of the source region 103 and the drain region 104, thereby reducing the contact voltage between the metal silicide layer 210 and the contact hole 191, and improving the performance of the device. Furthermore, since the top surface and side walls of the source region 103 and the top surface and side walls of the drain region 104 in the contact hole 191 form a step 191 c , it is beneficial to the subsequent filling of the conductive layer 220 and can improve the filling performance of the conductive layer 220 .

[0083] Afterwards, refer to Figure 1 , forming a conductive layer 220, the conductive layer 220 is located on the metal silicide layer 210 and fills the contact hole. In this embodiment, the conductive layer 220 can be made of aluminum and can be formed by physical vapor deposition (PVD).

[0084] In summary, in the silicon carbide device provided by the utility model, the silicon carbide device includes a substrate, a contact region, an interlayer dielectric layer and a metal silicide layer, an epitaxial layer is formed on the substrate, and a source region and a drain region are formed in the epitaxial layer; the contact region is located in the epitaxial layer between the source region and the drain region and is in contact with the source region and the drain region, and the top surface of the contact region is lower than the top surface of the source region and the drain region; the interlayer dielectric layer is located on the epitaxial layer, and a contact hole is provided in the interlayer dielectric layer, the contact hole is aligned with the contact region, and the bottom of the contact hole is lower than the top surface of the source region and the drain region. The top surface of the source region in the contact hole and the top surface and side walls of the drain region form steps; the metal silicide layer covers the side walls and the bottom of the contact hole; because the top surface and side walls of the source region in the contact hole and the top surface and side walls of the drain region form steps, the contact area between the metal silicide layer and the source region and the drain region can be increased, that is, the metal silicide layer can be in contact with the side walls and top surfaces of the source region and the drain region, thereby reducing the contact voltage between the metal silicide layer and the contact hole and improving the performance of the device.

[0085] The above description is only a description of the preferred embodiment of the utility model, and is not any limitation on the scope of the utility model. Any changes and modifications made by ordinary technicians in the field of the utility model based on the above disclosure are within the scope of protection of the claims. In addition, it should be recognized that although the utility model has been disclosed as above with preferred embodiments, the above embodiments are not used to limit the utility model. For any technician familiar with the field, without departing from the scope of the technical solution of the utility model, the technical content disclosed above can be used to make many possible changes and modifications to the technical solution of the utility model, or modified into equivalent embodiments of equivalent changes. Therefore, any simple modification, equivalent changes and modifications made to the above embodiments based on the technical essence of the utility model without departing from the content of the technical solution of the utility model still fall within the scope of protection of the technical solution of the utility model.

Claims

1. A silicon carbide device, characterized in that: include: A substrate, on which an epitaxial layer is formed, wherein a source region and a drain region are formed in the epitaxial layer. A contact region, the contact region is located in the epitaxial layer between the source region and the drain region and is in contact with the source region and the drain region, and a top surface of the contact region is lower than top surfaces of the source region and the drain region; an interlayer dielectric layer, located on the epitaxial layer, wherein the interlayer dielectric layer has a contact hole, wherein the contact hole is aligned with the contact region, wherein the bottom of the contact hole is lower than the top surface of the source region and the drain region, and wherein the top surface and side wall of the source region and the top surface and side wall of the drain region in the contact hole form steps; A metal silicide layer covers the sidewall and the bottom of the contact hole.

2. The silicon carbide device according to claim 1, characterized in that: At least two well regions are spaced apart from each other and are formed in the epitaxial layer. The source region and the drain region are respectively located in two adjacent well regions.

3. The silicon carbide device according to claim 2, characterized in that: The conductivity type of the source region is the same as the conductivity type of the drain region.

4. The silicon carbide device according to claim 3, characterized in that: The conductivity type of the source region and the conductivity type of the drain region are both N type.

5. The silicon carbide device according to claim 2, characterized in that: The conductivity type of the well region is the same as the conductivity type of the contact region.

6. The silicon carbide device according to claim 5, characterized in that: The conductivity type of the well region and the conductivity type of the contact region are both P type.

7. The silicon carbide device according to claim 2, characterized in that: The silicon carbide device also includes: A gate oxide layer is located on the epitaxial layer and covers the epitaxial layer, a portion of the well region, a portion of the source region and a portion of the drain region.

8. The silicon carbide device according to claim 7, characterized in that: The silicon carbide device further includes: a gate layer, wherein the gate layer is located on the gate oxide layer, and the interlayer dielectric layer also extends to cover the gate layer.

9. The silicon carbide device according to claim 8, characterized in that: The silicon carbide device also includes: A conductive layer is located on the metal silicide layer and fills the contact hole.

10. The silicon carbide device according to claim 1, characterized in that: The material of the epitaxial layer and the material of the substrate are both silicon carbide.

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