Semiconductor device

Abstract

The utility model relates to the technical field of semiconductors, and provides a semiconductor device, which comprises a base layer, a buffer layer and a first gate metal layer, the buffer layer and the base layer are stacked; the first gate metal layer is arranged on one side of the buffer layer, and the first gate metal layer is a TiAlN first gate metal layer, a TaAlN first gate metal layer or a WalN first gate metal layer. According to the semiconductor device, the first gate metal layer is set to be the TiAlN first gate metal layer, the TaAlN first gate metal layer or the WalN first gate metal layer, the characteristic that the aluminum element is poor in work function is utilized, when the content of the aluminum element in the composition is reduced, the work function of the aluminum element can be adjusted, then the threshold voltage of the gate metal layer is increased, and the performance of the semiconductor device is improved. The regulation and control amplitude of the threshold voltage of the semiconductor device is increased, and the application requirement of driving the gate voltage in a wide range is met.

Description

Technical Field

[0001] The utility model relates to the technical field of semiconductors, in particular to a semiconductor device. Background Art

[0002] During semiconductor manufacturing, after the epitaxial wafer is cleaned, a single-component gate metal layer is deposited on its surface by magnetron sputtering, atomic layer deposition or electron beam evaporation. Due to the single component of the gate metal layer, the threshold voltage regulation range of the semiconductor device is small and cannot meet the application requirements of a wide range of driving gate voltage. Utility Model Content

[0003] The utility model provides a semiconductor device, which is used to solve the defect of small regulating amplitude of threshold voltage of semiconductor devices in the prior art.

[0004] The utility model provides a semiconductor device, comprising: a base layer; a buffer layer stacked with the base layer; a first gate metal layer arranged on one side of the buffer layer, wherein the first gate metal layer is a TiAlN first gate metal layer, a TaAlN first gate metal layer or a WalN first gate metal layer.

[0005] According to a semiconductor device provided by the utility model, the content of titanium, tantalum or tungsten in the first gate metal layer is greater than 10%, and the content of aluminum in the first gate metal layer is less than 30%.

[0006] A semiconductor device provided by the utility model further includes a second gate metal layer, wherein the second gate metal layer is located on either side of the first gate metal layer, and the first gate metal layer and the second gate metal layer form a gate metal layer group.

[0007] According to a semiconductor device provided by the utility model, the second gate metal layer is a TiAlN second gate metal layer, a TaAlN second gate metal layer or a WAlN second gate metal layer.

[0008] According to a semiconductor device provided by the utility model, the content of titanium, tantalum or tungsten in the second gate metal layer is greater than 30%, and the content of aluminum in the second gate metal layer is less than 10%.

[0009] According to a semiconductor device provided by the utility model, the second gate metal layer is a TiN second gate metal layer, a TaN second gate metal layer or a WN second gate metal layer.

[0010] According to a semiconductor device provided by the utility model, there are multiple gate metal layer groups, and multiple gate metal layer groups are stacked.

[0011] According to a semiconductor device provided by the utility model, it also includes a protection layer, and the protection layer is stacked with the gate metal layer group.

[0012] According to a semiconductor device provided by the utility model, the protective layer is a TiAlN protective layer, a TaAlN protective layer or a WAlN protective layer.

[0013] According to a semiconductor device provided by the utility model, the protective layer is a TiN protective layer, a TaN protective layer or a WN protective layer.

[0014] The semiconductor device provided by the utility model sets the first gate metal layer as a TiAlN first gate metal layer, a TaAlN first gate metal layer or a WalN first gate metal layer, utilizes the characteristic of the poor work function of the aluminum element, and when the content of the aluminum element in the composition is reduced, the work function of the aluminum element can be adjusted, thereby increasing the threshold voltage of the gate metal layer, increasing the regulation range of the threshold voltage of the semiconductor device, and meeting the application requirements of a wide range of driving gate voltages. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] In order to more clearly illustrate the technical solutions in the present invention or the prior art, a brief introduction will be given below to the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0016] Figure 1 This is one of the structural schematic diagrams of the semiconductor device provided by the utility model;

[0017] Figure 2 This is the second structural schematic diagram of the semiconductor device provided by the utility model;

[0018] Figure 3 This is the third structural schematic diagram of the semiconductor device provided by the utility model;

[0019] Figure 4 This is the fourth structural schematic diagram of the semiconductor device provided by the utility model;

[0020] Figure 5 This is the fifth structural schematic diagram of the semiconductor device provided by the utility model;

[0021] Reference numerals:

[0022] 10: base layer; 20: buffer layer; 31: first gate metal layer; 32: second gate metal layer; 40: protection layer. DETAILED DESCRIPTION

[0023] In order to make the purpose, technical solution and advantages of the utility model clearer, the technical solution of the utility model will be described clearly and completely in conjunction with the drawings in the utility model. Obviously, the described embodiments are part of the embodiments of the utility model, not all of the embodiments. Based on the embodiments in the utility model, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the utility model.

[0024] The features of the terms "first" and "second" in the specification and claims of the utility model may explicitly or implicitly include one or more of the features. In the description of the utility model, unless otherwise specified, the meaning of "plurality" is two or more.

[0025] Combine the following Figure 1-Figure 5 The semiconductor device of the present invention is described.

[0026] like Figure 1 As shown, in an embodiment of the present utility model, the semiconductor device includes: a base layer 10, a buffer layer 20 and a first gate metal layer 31. The base layer 10 and the buffer layer 20 are stacked, and the first gate metal layer 31 is arranged on one side of the buffer layer 20, wherein the first gate metal layer 31 is a TiAlN first gate metal layer, a TaAlN first gate metal layer or a WAlN first gate metal layer.

[0027] Specifically, in the prior art, the gate metal layer is usually a TiN gate metal layer, a TaN gate metal layer or a WN gate metal layer. Due to the single component of the gate metal layer, the threshold voltage of the semiconductor device is small in regulation range and cannot meet the application requirements of a wide range of driving gate voltage.

[0028] Generally, adjusting the threshold voltage requires controlling the epitaxial layer composition and thermal annealing process. This method has a great influence on other electrical parameters of the semiconductor device, especially when adjusting the epitaxial layer composition, it will directly affect the dynamic performance and reliability of the semiconductor device. In this embodiment, the gate metal layer is set to a TiAlN first gate metal layer, a TaAlN first gate metal layer or a WAlN first gate metal layer, and aluminum is added to the first gate metal layer 31. When the content of the aluminum element is adjusted, the work function can be adjusted, and then the threshold voltage of the first gate metal layer 31 can be adjusted. Specifically, reducing the content of the aluminum element in the first gate metal layer 31 can increase the threshold voltage of the first gate metal layer 31, thereby increasing the threshold voltage regulation amplitude of the semiconductor device, meeting the application requirements of a wide range of driving gate voltages, and changing the compound structure of the first gate metal layer 31 has little effect on the process and the reliability of the semiconductor device.

[0029] In this embodiment, the base layer 10 is a Si base layer, a SiC base layer or a sapphire base layer. The buffer layer 20 is a GaN buffer layer, an intrinsic GaN buffer layer, a GaAlN buffer layer or a PGaN buffer layer.

[0030] The semiconductor device provided by the embodiment of the utility model, by setting the first gate metal layer to a TiAlN first gate metal layer, a TaAlN first gate metal layer or a WalN first gate metal layer, utilizes the poor work function of the aluminum element, and reduces the content of the aluminum element in the composition. The work function of the aluminum element can be adjusted, thereby increasing the threshold voltage of the gate metal layer, increasing the regulation range of the threshold voltage of the semiconductor device, and meeting the application requirements of a wide range of driving gate voltages.

[0031] Furthermore, in the embodiment of the present invention, the content of titanium, tantalum or tungsten in the first gate metal layer 31 is greater than 10%, and the content of aluminum in the first gate metal layer 31 is less than 30%.

[0032] Specifically, within a certain range, reducing the content of aluminum in the first gate metal layer 31 can increase the threshold voltage, reduce Schottky reverse leakage, and thus reduce the power loss and reliability of the semiconductor device; while increasing the content of aluminum in the first gate metal layer 31 can reduce the threshold voltage, increase the saturation current of the semiconductor device, and increase leakage. Based on this, in the embodiment of the present utility model, the content of aluminum in the first gate metal layer 31 is controlled within a range of less than 30%, and the content of aluminum in the first gate metal layer 31 can be adjusted within an allowable range according to the specific use conditions of the semiconductor device.

[0033] In the embodiment of the present invention, the leakage current is relatively large when the metal semiconductor contacts the Schottky gate structure. Therefore, the content of the aluminum element in the first gate metal layer 31 can be reduced within an allowable range to reduce the leakage current.

[0034] The semiconductor device provided by the embodiment of the utility model can reduce Schottky reverse leakage by reducing the aluminum content, thereby improving the performance of the semiconductor device.

[0035] like Figure 2 and Figure 3 As shown, the semiconductor device further includes a second gate metal layer 32 , the first gate metal layer 31 and the second gate metal layer 32 are stacked, the second gate metal layer 32 is located on either side of the first gate metal layer 31 , and the first gate metal layer 31 and the second gate metal layer 32 form a gate metal layer group.

[0036] Specifically, in the present embodiment, the gate metal layer group is a layer structure in which two layers of gate conductive materials are stacked. When arranged, the first gate metal layer 31 can be arranged adjacent to the buffer layer 20, and the second gate metal layer 32 can also be arranged adjacent to the buffer layer 20. Since the first gate metal layer 31 is a TiAlN first gate metal layer, a TaAlN first gate metal layer or a WAlN first gate metal layer, the threshold voltage of the gate metal layer 30 can be adjusted by adjusting the content of the aluminum element in the composition. Specifically, for example, the content of the aluminum element in the first gate metal layer 31 can be reduced to increase the threshold voltage control range of the semiconductor device.

[0037] Optionally, in an embodiment of the present invention, the second gate metal layer 32 is a TiAlN second gate metal layer, a TaAlN second gate metal layer or a WAlN second gate metal layer.

[0038] Specifically, the material of the second gate metal layer 32 can be the same as that of the first gate metal layer 31, such as the first gate metal layer 31 and the second gate metal layer 32 are both TiAlN gate metal layers; the material of the second gate metal layer 32 can also be different from that of the first gate metal layer 31, such as the first gate metal layer 31 is a TiAlN first gate metal layer, and the second gate metal layer 32 is a TaAlN second gate metal layer.

[0039] Furthermore, when the second gate metal layer 32 is a TiAlN second gate metal layer, a TaAlN second gate metal layer or a WAlN second gate metal layer, no matter the first gate metal layer 31 is disposed adjacent to the buffer layer 20 or the second gate metal layer 32 is disposed adjacent to the buffer layer 20, since both gate metal layers still contain aluminum elements, the gate metal layer away from the buffer layer 20 can protect the semiconductor device. In the Gate first process, the Gate will be exposed to chemical reagents, which will inevitably bring metal contamination. Compared with a single protective layer compound, the aluminum element in the first gate metal layer 31 or the second gate metal layer 32 can increase the gate metal layer's resistance to chemical reagent corrosion, making the binding energy stronger, and thus not easily corroded by chemical reagents.

[0040] Further, in the embodiment of the present invention, the content of titanium, tantalum or tungsten in the second gate metal layer 32 is greater than 30%, and the content of aluminum in the second gate metal layer 32 is less than 10%. Setting the content of aluminum in the second gate metal layer 32 to a higher value within the allowable range can enhance the chemical corrosion resistance of the semiconductor device.

[0041] The semiconductor device provided by the embodiment of the utility model can reduce Schottky reverse leakage by setting the gate metal layer to a structure in which a first gate metal layer and a second gate metal layer are stacked, and by increasing the content of aluminum elements in the two gate metal layers. At the same time, the semiconductor device can enhance its resistance to chemical corrosion, thereby improving the performance and service life of the semiconductor device.

[0042] Optionally, in another embodiment of the present invention, the second gate metal layer 32 is a TiN second gate metal layer, a TaN second gate metal layer or a WN second gate metal layer. When the second gate metal layer 32 is a TiN second gate metal layer, a TaN second gate metal layer or a WN second gate metal layer, when the second gate metal layer 32 is disposed adjacent to the buffer layer 20, the first gate metal layer 31 contains aluminum elements, which can not only increase the threshold voltage adjustment range and reduce leakage, but also enhance the chemical reagent corrosion resistance of the semiconductor device.

[0043] In an embodiment of the present invention, there are multiple gate metal layer groups, and the multiple gate metal layer groups are stacked.

[0044] Specifically, when the thickness of the gate metal layer group is relatively thin, a plurality of gate metal layer groups may be provided, and the plurality of gate metal layer groups may be stacked. Further, the semiconductor device further includes a protective layer 40, and the protective layer 40 is stacked with the gate metal layer group. Specifically, in an embodiment of the utility model, the protective layer 40 may be a TiAlN protective layer, a TaAlN protective layer or a WAlN protective layer; the protective layer 40 may also be a TiN protective layer, a TaN protective layer or a WN protective layer. When the protective layer 40 is a TiAlN protective layer, a TaAlN protective layer or a WAlN protective layer, the aluminum element in the protective layer 40 may increase the gate metal layer's resistance to chemical reagent corrosion, making the binding energy stronger, thereby making it less susceptible to chemical reagent corrosion. Increasing the content of the aluminum element in the protective layer 40 may improve the semiconductor device's resistance to chemical reagent corrosion, thereby improving the performance and service life of the semiconductor device.

[0045] Furthermore, the gate metal layer group includes a first gate metal layer 31 and a second gate metal layer 32. When multiple gate metal layer groups are stacked, there are two situations. One is as follows: Figure 4 The situation shown in Figure 4In the illustrated embodiment, the first gate metal layer 31 of the first gate metal layer group is disposed adjacent to the buffer layer 20. After the plurality of gate metal layer groups are stacked, the gate conductive material located at the outermost layer is the second gate metal layer 32. When the second gate metal layer 32 is a TiAlN second gate metal layer, a TaAlN second gate metal layer or a WAlN second gate metal layer, increasing the content of the aluminum element in the second gate metal layer 32 can improve the chemical reagent corrosion resistance of the semiconductor device, thereby improving the performance and service life of the semiconductor device. At this time, the outermost second gate metal layer 32 can be used as a protective layer 40, and the protective layer 40 may not be provided to reduce the thickness of the semiconductor device.

[0046] When the second gate metal layer 32 is a TiN second gate metal layer, a TaN second gate metal layer or a WN second gate metal layer, a protective layer 40 is stacked on the outermost second gate metal layer 32, and the protective layer 40 can be set to a TiAlN protective layer, a TaAlN protective layer or a WAlN protective layer, so as to increase the content of aluminum in the protective layer 40 and thus increase the chemical reagent corrosion resistance of the semiconductor device.

[0047] exist Figure 5 In the illustrated embodiment, the second gate metal layer 32 of the first gate metal layer group is disposed adjacent to the buffer layer 20. After a plurality of gate metal layer groups are stacked, the gate conductive material located at the outermost layer is the first gate metal layer 31. Since the first gate metal layer 31 contains aluminum, it can be used as a protective layer 40. By increasing the content of the aluminum element in the first gate metal layer 31, the ability of the semiconductor device to resist corrosion by chemical reagents can be improved, thereby improving the performance and service life of the semiconductor device. In this case, the protective layer 40 may not be provided to reduce the thickness of the semiconductor device.

[0048] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the utility model, rather than to limit it. Although the utility model has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the various embodiments of the utility model.

Claims

1. A semiconductor device, characterized in that: include: Grassroots; A buffer layer, stacked with the base layer; The first gate metal layer is disposed on one side of the buffer layer, and the first gate metal layer is a TiAlN first gate metal layer, a TaAlN first gate metal layer or a WAlN first gate metal layer.

2. The semiconductor device according to claim 1, wherein: It also includes a second gate metal layer, which is located on either side of the first gate metal layer, and the first gate metal layer and the second gate metal layer form a gate metal layer group.

3. The semiconductor device according to claim 2, characterized in that The second gate metal layer is a TiAlN second gate metal layer, a TaAlN second gate metal layer or a WAlN second gate metal layer.

4. The semiconductor device according to claim 2, characterized in that The second gate metal layer is a TiN second gate metal layer, a TaN second gate metal layer or a WN second gate metal layer.

5. The semiconductor device according to claim 2, wherein: There are multiple gate metal layer groups, and multiple gate metal layer groups are stacked.

6. The semiconductor device according to claim 2 or 5, characterized in that: It also includes a protection layer, which is stacked with the gate metal layer group.

7. The semiconductor device according to claim 6, characterized in that The protective layer is a TiAlN protective layer, a TaAlN protective layer or a WAlN protective layer.

8. The semiconductor device according to claim 6, characterized in that The protective layer is a TiN protective layer, a TaN protective layer or a WN protective layer.

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