Superconducting quantum chip and quantum computer
By forming multiple through-through holes on the superconducting layer to limit the activity of quasi-particles, the energy loss problem caused by the quasi-particles approaching the Josephson junction in the superconducting quantum chip is solved, and the performance of the chip is improved.
Patent Information
- Application Number
- CN202420391598.0
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-02-29
- Publication Date
- 2025-03-18
- Estimated Expiration
- 2034-02-28
AI Technical Summary
In extremely low temperature environments, quasi-particles in superconducting quantum chips are close to the Josephson junction, resulting in energy loss and reduced performance.
A plurality of through holes are formed on the superconducting layer to limit the activity of the quasi-particles and prevent them from approaching the junction region of the Josephson junction.
Effectively prevent quasi-particles from participating in the tunneling process of Josephson junction, reduce energy decoherence, and improve the performance of superconducting quantum chips.
Smart Images
Figure CN222639032U_ABST
Abstract
Description
Technical Field
[0001] The present application belongs to the field of quantum computing technology, and in particular, relates to a superconducting quantum chip and a quantum computer. Background Art
[0002] Quantum computers are physical devices that follow the laws of quantum mechanics to perform high-speed mathematical and logical operations, store and process quantum information. The main characteristics of quantum computers are fast operation speed, strong information processing capabilities, and a wide range of applications. Compared with ordinary computers, the more information is processed, the more advantageous it is for quantum computers to perform operations, and the more accurate the operations can be.
[0003] At present, the core of superconducting quantum computers - superconducting quantum chips are generally placed in the extremely low temperature space of a dilution refrigerator for operation; the problem that follows is: after entering the dilution refrigerator, the concentration of quasiparticles will be greatly increased due to its extremely low temperature environment; and the behavior of these quasiparticles near the Josephson junction of the superconducting quantum chip is very complicated. For example, quasiparticles may absorb or release photons or phonons, resulting in energy loss, and release it into the low temperature environment in the form of heat; and this process will cause the tunneling process of the Josephson junction to introduce losses, making the bits appear as energy decoherence, thereby reducing the performance of the superconducting quantum chip; in short, preventing quasiparticles in superconducting quantum chips from approaching the Josephson junction has become an urgent problem to be solved in superconducting quantum chips. Utility Model Content
[0004] The purpose of the present application is to provide a superconducting quantum chip and a quantum computer to solve the problem of quasiparticles being close to the Josephson junction in the superconducting quantum chip in the prior art, and to confine the quasiparticles generated by the superconducting material in the chip within the through hole to prevent the quasiparticles from introducing losses in the tunneling process of the Josephson junction and causing energy decoherence, thereby avoiding the performance degradation of the superconducting quantum chip.
[0005] In order to solve the above technical problems, the utility model provides a superconducting quantum chip, comprising:
[0006] substrate;
[0007] A superconducting layer is formed on the surface of the substrate, and a Josephson junction is arranged on the surface of the superconducting layer away from the substrate;
[0008] In a direction perpendicular to the superconducting layer, a plurality of through holes are provided in a region of the superconducting layer away from the Josephson junction;
[0009] Wherein, all the through holes are used to confine the quasiparticles to prevent the quasiparticles from approaching the Josephson junction.
[0010] Preferably, all of the through holes are quadrangular prisms with quadrilateral cross-sections.
[0011] Preferably, the distance between any two adjacent through holes is consistent.
[0012] Preferably, the substrate is a silicon substrate or a sapphire substrate.
[0013] Preferably, the material of the superconducting layer is aluminum.
[0014] Preferably, the superconducting quantum chip further comprises a resonant cavity and a signal line;
[0015] The resonant cavity and the signal line are arranged on the surface of the superconducting layer having a Josephson junction;
[0016] The through hole does not intersect the resonant cavity and the signal line.
[0017] Preferably, it also includes a metal film layer;
[0018] The metal film layer is formed at one end of the superconducting metal layer of the Josephson junction away from the junction region.
[0019] Preferably, there are multiple metal film layers;
[0020] The metal film layer is electrically connected to the superconducting metal layer of the Josephson junction.
[0021] Preferably, the material of the metal film layer is a superconducting metal or a common metal;
[0022] Wherein, the superconducting energy gap of the superconducting metal is smaller than the superconducting energy gap of the superconducting layer.
[0023] In order to solve the above technical problems, the utility model also provides a quantum computer, comprising any one of the above-mentioned superconducting quantum chips.
[0024] Compared with the prior art, the superconducting quantum chip provided by the present application includes a substrate and a superconducting layer formed on the surface of the substrate; and, the key point is that a plurality of dense through holes penetrating the superconducting layer are formed on the superconducting layer. According to its physical mechanism, these through holes are all used to confine quasiparticles to avoid high concentrations of quasiparticles participating in the tunneling process of the Josephson junction and causing energy decoherence; the superconducting quantum chip provided by the present invention can "capture" or "confine" quasiparticles, thereby improving the performance of the superconducting quantum chip. BRIEF DESCRIPTION OF THE DRAWINGS
[0025] Figure 1 A schematic diagram of the planar structure of a superconducting quantum chip provided in an embodiment of the present application;
[0026] Figure 2 A schematic diagram of a structure in which a superconducting layer has through holes provided in an embodiment of the present application;
[0027] Figure 3 Schematic diagram of the Josephson junction and metal film layer structure provided in an embodiment of the present application.
[0028] Explanation of reference numerals: 1 - substrate, 2 - superconducting layer, 21 - through hole, 22 - Josephson junction, 3 - metal film layer. DETAILED DESCRIPTION
[0029] The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present application, and should not be construed as limiting the present application.
[0030] In the description of the present application, it should be understood that the terms "center", "up", "down", "left", "right", etc., indicating directions or positional relationships are based on the directions or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific direction, be constructed and operated in a specific direction, and therefore should not be understood as a limitation on the present application.
[0031] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first" and "second" may explicitly or implicitly include one or more of the features. In the description of this application, the meaning of "plurality" is at least two, such as two, three, etc., unless otherwise clearly and specifically defined.
[0032] In condensed matter physics, Cooper pairs or BCS pairs are pairs of electrons (or other fermions) that are bound together at low temperatures, and the state of Cooper pairs is responsible for superconductivity. As mentioned in the background, when a superconducting quantum chip enters the extremely low temperature test area of a dilution refrigerator, the Cooper pairs in its superconducting material decompose due to environmental radiation to form quasiparticles. The behavior of this high concentration of quasiparticles near the Josephson junction area is relatively complex, such as accompanied by the absorption or emission of photons or phonons, resulting in energy loss, and the energy is released into the low temperature environment in the form of heat; in superconducting quantum chips, the above quasiparticle activity causes the tunneling process of the Josephson junction to introduce losses, which is specifically manifested as energy decoherence in bits.
[0033] Therefore, confining or capturing quasiparticles in the superconducting layer of a superconducting quantum chip can effectively prevent the decoherence of the superconducting quantum chip and thereby improve the performance of the superconducting quantum chip.
[0034] Please refer to Figure 1The utility model provides a superconducting quantum chip for limiting quasiparticles in the superconducting quantum chip. The superconducting quantum chip includes a substrate 1 and a superconducting layer 2 formed on one surface of the substrate 1; and the superconducting layer 2 is provided with a Josephson junction 22 on its surface by photolithography or the like; in a direction perpendicular to the superconducting layer 2, a region of the superconducting layer 2 away from the Josephson junction 22 is provided with a plurality of through holes 21 penetrating through the two surfaces of the superconducting layer 2, and all the through holes 21 are used to limit the position of the quasiparticles so that the quasiparticles are away from the junction region of the Josephson junction 22.
[0035] As is known to all, when the ambient temperature is far below the superconducting critical temperature, most of the electrons in the superconducting material in the superconducting quantum chip are combined into Cooper pairs through phonons; in this state, the content of quasiparticles in the superconducting material is extremely low to negligible under thermal equilibrium; but when the superconducting quantum chip is placed in the extremely low temperature space of a dilution refrigerator, a large number of Cooper pairs decompose into quasiparticles, which greatly increases the concentration of quasiparticles; and the activities of these quasiparticles in the junction area close to the Josephson junction 22 are complex, specifically absorbing or emitting photons or phonons to cause energy loss, thereby causing the bit to appear as energy decoherence.
[0036] In some embodiments of the present application, a superconducting quantum chip as described above is provided, specifically in the form of providing a through hole 21 structure, which is used to "capture" or "limit" the position of the quasiparticle so that it does not participate in the tunneling process of the Josephson junction 22, thereby improving the performance of the superconducting quantum chip.
[0037] Specifically, a substrate 1 is provided, which may be a silicon substrate or a sapphire substrate, etc. The substrate 1 is processed by processes such as coating, exposure and development, and etching to form a superconducting layer 2 and a Josephson junction 22 formed by etching the superconducting layer 2 on its surface, so as to realize the basic components required for superconducting operations of a superconducting quantum chip.
[0038] Furthermore, since the superconducting layer 2 is attached to the substrate 1, the plane where the superconducting layer 2 is located is parallel to the plane where the surface of the substrate 1 is located; and the Josephson junction 22 and other quantum components are made in the superconducting layer 2, it can be understood that the Josephson junction 22 and other quantum components are coplanar and parallel to the superconducting layer 2.
[0039] According to the above, a plurality of through holes 21 are provided in the area away from the Josephson junction 22 on the surface of the superconducting layer 2 facing away from the substrate 1 in the direction perpendicular to the superconducting layer 2; it is worth mentioning that the through holes 21 completely penetrate and spatially connect the two opposite surfaces of the superconducting layer 2, and when the through holes 21 are photolithographically manufactured, the process is to ensure that the superconducting layer 2 is completely penetrated, and even etching can be performed until part of the substrate 1 is etched to ensure that the through holes 21 completely penetrate the two surfaces of the superconducting layer 2; from the perspective of physical arrangement, the arrangement density and size of the through holes 21 can be determined according to the quantum devices on the superconducting layer 2, but the arrangement mode and layout of the through holes 21 at least meet the following requirements: the distance between all the first through holes 21 and the Josephson junction 22 or the quantum device is at least 10 μm; in addition, the density of all the through holes 21 is as large as possible and the size is as small as possible within the controllable process.
[0040] According to the background, when the superconducting quantum chip enters the extremely low temperature space of the dilution refrigerator, the concentration of quasiparticles is greatly increased due to factors such as space radiation. The through hole 21 can effectively "capture" or "limit" the position of these quasiparticles, so that the quasiparticles are confined in the through hole 21 to prevent them from participating in the tunneling process of the Josephson junction 22 junction area, thereby improving the performance of the superconducting quantum chip.
[0041] In addition, for the current superconducting quantum chip industry, most of them are capable of manufacturing superconducting quantum chips with flip-chip structures. For superconducting quantum chips with flip-chip structures, the superconducting quantum chip structure provided by the utility model is also applicable. Specifically, the superconducting metal layers in the Flip layer and the Bsae layer of the flip-chip structure are used to set the penetrating through hole 21, and the setting method is based on the above.
[0042] Please refer to Figure 2 All through holes 21 are etched and made into a quadrangular prism shape with a quadrilateral cross section; the quadrangular prism shape is reproduced according to the inventor's specific experiments, and according to his discovery, the through hole 21 in the shape of a quadrangular prism can better limit the position of high-concentration quasiparticles. However, the shape of the through hole 21 should not be limited to the above shape, and the through hole 21 can also be set to a cylindrical, rectangular, cube, etc. shape, and it can be made according to the process method and specific environment.
[0043] Moreover, for the arrangement of the through holes 21 on the superconducting layer 2, the present application provides that the distance between any two adjacent through holes 21 is consistent, so as to better and more efficiently capture or confine the quasiparticles in the superconducting quantum chip. In general, the arrangement of all through holes 21 on the superconducting layer 2 is based on a uniform, close, and regular manner to achieve the maximum efficiency in confining the quasiparticles.
[0044] In one embodiment of the present application, the substrate 1 is set as a silicon substrate or a sapphire substrate, and the surface of the substrate 1 can be processed subsequently by coating, exposure and development, etching, and washing to form a superconducting layer 2 and its quantum elements.
[0045] The usual manufacturing materials of the chip, and the application in the superconducting quantum chip, the substrate 1 can be made of various appropriate materials, such as silicon or sapphire, which can be selected according to actual needs and is not limited to the above materials.
[0046] Furthermore, for the superconducting layer 2 manufactured on the substrate 1 , in the embodiment of the present application, the material of the superconducting layer 2 is set to be aluminum.
[0047] Under the current technical background, any conductor has a certain value of resistance at room temperature. However, there are some metals, such as lead, tin, niobium, aluminum and other metals, whose resistance at both ends is zero at a specific extremely low temperature. This is the superconducting effect. According to the principle of fact, the superconducting layer 2 can be manufactured by selecting any one of the superconducting metals.
[0048] Please refer again Figure 1 The superconducting quantum chip also includes a resonant cavity and a signal line, and the resonant cavity and the signal line are arranged on the same surface of the superconducting layer 2 where the Josephson junction 22 is located; according to the above description of the through hole 21, it can be understood that before the through hole 21 is made, the superconducting layer 2 will be planned according to the arrangement of the quantum devices in the superconducting quantum chip, so that the through hole 21 does not intersect with the resonant cavity, signal line and other devices to avoid affecting the normal computing performance of the superconducting quantum chip; strictly speaking, the superconducting quantum chip should be provided with quantum devices such as quantum bits, reading cavities, microwave lines, signal ports, etc., and these components are integrated on the surface of a substrate, and there should be good communication methods between the various devices: such as coupling, electrical connection, etc.
[0049] Please refer to Figure 3 In order to more deeply and comprehensively restrict the quasi-particles produced, a metal film layer 3 may be added; the metal film layer 3 is formed at one end of the superconducting metal of the Josephson junction 22 away from the junction region.
[0050] As is known to all, in actual process engineering, superconducting quantum bits are mostly composed of Josephson junctions 22 and parallel capacitors; the Josephson junction 22 can be equivalent to a nonlinear inductor; and the Josephson junction 22 is a structure composed of superconductor-insulator-superconductor, among which the most common is the Al-AlOx-Al junction.
[0051] As mentioned above, the Josephson junction 22 is often made on the substrate 1, and two layers of superconducting layers 2 are sputter-coated on the substrate 1 by magnetron sputtering or the like, and the overlapping area of the two layers of superconducting layers 2 has an oxide layer as an insulating layer, so as to realize the basic superconducting structure of the Josephson junction 22. In addition, the overlapping area of the upper and lower superconducting layers 2 can be understood as the junction area, and the quasiparticles in the superconducting quantum chip will participate in the tunneling process of the junction area, causing energy decoherence, resulting in a decrease in the performance of the superconducting quantum chip; therefore, a metal film layer 3 is also provided on the two superconducting layers 2 of the Josephson junction 22 and at one end away from the junction area, which is used to limit the quasiparticles around the Josephson junction 22 and prevent these quasiparticles from approaching the junction area of the Josephson junction 22.
[0052] It is worth noting that there can be multiple metal film layers 3 ; and these metal film layers 3 are electrically connected to the superconducting metal layers of the Josephson junction 22 respectively.
[0053] As described above, in a complete superconducting quantum chip, there are often multiple Josephson junctions 22 and readout lines, control lines, resonators and capacitors arranged corresponding to the multiple Josephson junctions 22; therefore, in order to make each Josephson junction 22 as unaffected by quasiparticles as possible, multiple metal film layers 3 are arranged, and each metal film layer 3 is arranged at the end of a superconducting layer 2 of a Josephson junction 22, so as to achieve the effect of limiting the position of quasiparticles to the greatest extent.
[0054] In one embodiment of the present application, the material of the metal film layer 3 is a superconducting metal or an ordinary metal. It is worth noting that when the metal film layer 3 is selected as a superconducting metal material, the superconducting energy gap of the superconducting metal must be smaller than the superconducting energy gap of the superconducting layer 2, so as to limit the position of the quasi-particles and reduce energy decoherence, so as to improve the performance of the superconducting quantum chip.
[0055] Specifically, when the metal is in a superconducting state, the formula of the superconducting gap Δ is: Δ = 1.75kTc, where k is the Boltzmann constant and Tc is the superconducting critical temperature. When aluminum is used as the material of the superconducting layer 2, the Tc of aluminum is 1.2K. At this time, titanium (Ti) and zirconium (Zr) can be used as the material of the metal film layer 3; wherein the Tc of Ti is 0.39K and the Tc of Zr is 0.55K, indicating that the superconducting energy gaps of titanium and zirconium are smaller than the superconducting energy gap of aluminum. In addition, when the material of the superconducting film layer is selected as an ordinary metal, copper metal can be selected as an example.
[0056] In one embodiment of the present application, a quantum computer is provided, comprising the superconducting quantum chip of the aforementioned embodiment.
[0057] In the description of this specification, the description with reference to the terms "one embodiment", "some embodiments", "example" or "specific example" etc. means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present application. In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described may be combined in any one or more embodiments in a suitable manner. In addition, those skilled in the art may combine and combine different embodiments or examples described in this specification.
[0058] The above describes in detail the structure, features and effects of the present application based on the embodiments shown in the drawings. The above is only a preferred embodiment of the present application, but the present application does not limit the scope of implementation to what is shown in the drawings. Any changes made in accordance with the concept of the present application, or modifications to equivalent embodiments with equivalent changes, which still do not exceed the spirit covered by the description and drawings, should be within the protection scope of the present application.
Claims
1. A superconducting quantum chip, characterized in that: include: Base (1); A superconducting layer (2) is formed on the surface of the substrate (1), and a Josephson junction (22) is provided on the surface of the superconducting layer (2) facing away from the substrate (1); In a direction perpendicular to the superconducting layer (2), a plurality of through holes (21) are provided in a region of the superconducting layer (2) away from the Josephson junction (22); Wherein, all the through holes (21) are used to confine quasiparticles to prevent the quasiparticles from approaching the Josephson junction (22).
2. The superconducting quantum chip according to claim 1, characterized in that: All of the through holes (21) are quadrangular prisms with quadrilateral cross sections.
3. The superconducting quantum chip according to claim 2, characterized in that: The distance between any two adjacent through holes (21) is consistent.
4. The superconducting quantum chip according to claim 1, characterized in that: The substrate (1) is a silicon substrate or a sapphire substrate.
5. The superconducting quantum chip according to claim 1, characterized in that: The material of the superconducting layer (2) is aluminum.
6. The superconducting quantum chip according to any one of claims 1 to 5, characterized in that: The superconducting quantum chip also includes a resonant cavity and a signal line; The resonant cavity and the signal line are arranged on the surface of the superconducting layer (2) having a Josephson junction (22); The through hole (21) does not intersect the resonant cavity and the signal line.
7. The superconducting quantum chip according to claim 1, characterized in that: Also includes a metal film layer (3); The metal film layer (3) is formed at an end of the superconducting metal layer of the Josephson junction (22) away from the junction region.
8. The superconducting quantum chip according to claim 7, characterized in that: The metal film layer (3) is multiple; The metal film layer (3) is electrically connected to the superconducting metal layer of the Josephson junction (22).
9. The superconducting quantum chip according to claim 8, characterized in that: The material of the metal film layer (3) is a superconducting metal or a common metal; The superconducting energy gap of the superconducting metal is smaller than the superconducting energy gap of the superconducting layer (2).
10. A quantum computer, characterized in that: include: The superconducting quantum chip according to any one of claims 1 to 9.