Novel display circuit

By using transistor T23 to turn off the relevant transistors in the precharge stage of the new display circuit, the problem of Q point leakage acceleration at high temperature is solved, and a more stable Gout output is achieved.

CN222653641UActive Publication Date: 2025-03-21CPT TECH GRP
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Patent Information

Application Number
CN202421341253.0
Authority / Receiving Office
CN · China
Patent Type
Utility models(China)
Current Assignee / Owner
Filing Date
2024-06-13
Publication Date
2025-03-21
Estimated Expiration
2034-06-13

AI Technical Summary

Technical Problem

In high temperature environment, when the traditional 24T1C circuit is at a high potential at the Q point, the P point potential pull-down capability is insufficient, resulting in the Q point leakage acceleration, affecting the Gout output in the voltage stabilization stage.

Method used

A new display circuit is designed to prevent the charging of the P1 and P2 nodes by using the transistors T23 to turn off the transistors T21 and T22 during the precharge stage, thereby keeping the P point at a low potential, and reducing leakage at the Q point.

Benefits of technology

It effectively avoids the Q point leakage acceleration caused by the rise of P point potential at high temperature, ensuring the level of the Q point twice the voltage and the stability of the Gout output in the voltage stabilization stage.

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Abstract

The utility model provides a novel display circuit, which comprises a closing and voltage stabilizing circuit module, and the closing and voltage stabilizing circuit module comprises transistors T2, T3, T12, T13, T15, T8, T21, T22, T9 and T23. The grid electrodes of the T2 and the T12, the drain electrodes of the T13 and the T15 and the pre-charging circuit module are connected to a point Q, a node P1 is arranged on a connecting line of the grid electrodes of the T3, the T5-2 and the T5, and a node P2 is arranged on a connecting line of the grid electrodes of the T13, the T6-2 and the T6; the grid electrode of the T23 is connected with the Q point, the drain electrode of the T23 is connected with the grid electrode of the T21 and the drain electrode of the T8, and the source electrode of the T23 is connected with a voltage signal VGL1; the source electrode of the T21 and the grid electrode and the source electrode of the T8 are connected with a signal V1, and the drain electrode of the T21 is connected with a node P1; the source electrode of the T22 and the grid electrode and the source electrode of the T9 are connected with a signal V2, the grid electrode of the T22 and the drain electrode of the T9 are jointly connected with the drain electrode of the T23, and the drain electrode of the T22 is connected with a node P2. The T21 and the T22 are closed through the T23, so that the T8 and the T9 cannot charge the P1 and the P2, the P point is maintained at a low potential, and the effect on electric leakage of the Q point cannot be generated.
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Description

Technical Field

[0001] The utility model relates to the technical field of display panels, and in particular to a novel display circuit. Background Art

[0002] At present, people's demand for in-vehicle display panels is increasing with the popularity of new energy vehicles. Different from other usage scenarios, in-vehicle panels pay special attention to the display capabilities of the panels in high temperature environments. Therefore, whether the panel driving circuit can output signals normally under high temperature is particularly important. It is known that the leakage capacity of TFT devices in circuits will increase significantly at high temperatures, and if TFT works in a high temperature environment for a long time, its threshold voltage may shift, affecting the switching characteristics of TFT. The traditional 24T1C circuit architecture consists of a pre-charge circuit, a shutdown and voltage stabilization circuit, and an output circuit, such as Figure 1 However, under high temperature and threshold voltage negative bias 1.5V conditions, as shown in Figure 2 As shown, before the pre-charging of point Q ends and the voltage regulation stage begins, the voltage at point Q drops due to high temperature and threshold voltage offset, which also weakens the effect of T2 pulling down point P, increases the voltage at point P, and accelerates the drop in the voltage at point Q, affecting the level of the double voltage at point Q and the Gout output during the voltage regulation stage. Utility Model Content

[0003] The technical problem to be solved by the utility model is to provide a new display circuit, which can enhance the ability to pull down the potential of point P when point Q is at a high potential, avoid the situation where the leakage of point Q is accelerated due to the increase of point P potential in a high temperature environment, and improve the Gout output capacity.

[0004] The utility model is achieved in this way:

[0005] The utility model provides a novel display circuit, comprising a pre-charging circuit module and an output circuit module, and also comprising a closing and voltage stabilizing circuit module, wherein the pre-charging circuit module and the output circuit module are respectively connected to the closing and voltage stabilizing circuit module;

[0006] The shutdown and voltage stabilization circuit module includes transistors T2, T3, T12, T13, T15, T8, T21, T22, T9, T23, T5, T5-2, T6 and T6-2;

[0007] The gate of the transistor T2, the gate of T12, the drain of T13, the drain of T15 and the pre-charging circuit module are connected to point Q, and the output circuit module is connected to point Q;

[0008] The drain of the transistor T2, the gate of T3, the gate of T5-2 and the gate of T5 are connected, and a node P1 is provided on the connection line of the drain of T2, the gate of T3, the gate of T5-2 and the gate of T5;

[0009] The drain of the transistor T12, the gate of T13, the gate of T6-2 and the gate of T6 are connected, and a node P2 is provided on the connection line of the drain of T12, the gate of T13, the gate of T6-2 and the gate of T6;

[0010] The source of the transistor T2, the source of T3, the source of T12, and the source of T13 are all connected to the voltage signal VGL1;

[0011] The gate of the transistor T23 is connected to the Q point, the drain of the transistor T23 is connected to the gate of T21 and the drain of T8, and the source of the transistor T23 is connected to the voltage signal VGL1;

[0012] The source of the transistor T21 and the gate and source of T8 are commonly connected to the signal V1, and the drain of the transistor T21 is connected to the node P1;

[0013] The source of the transistor T22 and the gate and source of T9 are commonly connected to the signal V2 , the gate of the transistor T22 and the drain of T9 are commonly connected to the drain of the transistor T23 , and the drain of the transistor T22 is connected to the node P2 .

[0014] Further, the shutdown and voltage stabilization circuit module also includes transistors T18, T19, T10, T11, T14, T14-2, T16, T17 and T20;

[0015] The gate of the transistor T10 is connected to the signal V2, the drain of the transistor T10 is connected to the node P1, and the source of the transistor T10 is connected to the voltage signal VGL1;

[0016] The gate of the transistor T11 is connected to the signal V1, the source of the transistor T11 is connected to the voltage signal VGL1, and the drain of the transistor T11 is connected to the node P2;

[0017] The gates of the transistors T18 and T19 are commonly connected to the signal Xn-4, the drain of the transistor T18 is connected to the node P1, the drain of the transistor T19 is connected to the node P2, the sources of the transistors T18 and T19 and the source of T15 are commonly connected to the voltage signal VGL1, and the gate of the transistor T15 is connected to the signal CLR;

[0018] The drain of the transistor T5-2 is connected to the output circuit module, and the source of the transistor T5-2 is connected to the voltage signal VGL1;

[0019] The gate of the transistor T14-2 is connected to the signal CLR, the drain of the transistor T14-2 is connected to the output circuit module, and the source of the transistor T14-2 is connected to the voltage signal VGL1;

[0020] The gates of the transistors T16 and T17 are connected to the signal CLR-P, the sources of the transistors T16 and T17 are connected to the voltage signal VGL1, the drain of the transistor T16 is connected to the node P1, and the drain of the transistor T17 is connected to the node P2;

[0021] The source of the transistor T5 is connected to the voltage signal VGL2, and the drain of the transistor T5 is connected to the output circuit module;

[0022] The source of the transistor T6-2 is connected to the voltage signal VGL1, and the drain of the transistor T6-2 is connected to the output circuit module;

[0023] The source of the transistor T6 is connected to the voltage signal VGL2, and the drain of the transistor T6 is connected to the output circuit module;

[0024] The gate of the transistor T20 is connected to the signal Xn+4, the source of the transistor T20 is connected to the voltage signal VGL2, and the drain of the transistor T20 is connected to the output circuit module;

[0025] The gate of the transistor T14 is connected to the signal CLR, the source of the transistor T14 is connected to the voltage signal VGL2, and the drain of the transistor T14 is connected to the output circuit module.

[0026] Further, the pre-charging circuit module includes transistors T1 and T7, the drains of the transistors T1 and T7 are connected to the gates of transistors T2 and T12 and the drains of transistors T3 and T15 and then connected to the Q point, the gate and source of the transistor T1 are connected to the signal Xn-4, the gate of the transistor T7 is connected to the signal Xn+4, and the source of the transistor T7 is connected to transistors T18, T19 and T15 and then connected to the voltage signal VGL1.

[0027] Furthermore, the output circuit module includes a capacitor C1, transistors T4 and T4-2, the gates of the transistors T4 and T4-2 are connected to the Q point, the sources of the transistors T4 and T4-2 are connected to the signal CK, the drain of the transistor T4-2 is connected to the drains of T5-2, T14-2 and T6-2 and then connected to the signal output terminal Xn, one end of the capacitor C1 is connected to the gates of the transistors T4 and T4-2, and the other end of the capacitor C1 is connected to the drains of the transistors T4, T5, T6, T20 and T14 and then connected to the signal output terminal Gn.

[0028] The advantages of the utility model are: in the pre-charging stage, transistors T21 and T22 are turned off by transistor T23, so that T8 and T9 cannot charge P1 and P2, point P is always maintained at a low potential, point Q is only affected by the leakage of the device, and can still form a double voltage of point Q in the voltage stabilization stage to ensure the output of Gout, thereby improving the ability of the panel drive circuit to output signals normally at high temperatures and enhancing the reliability of the panel. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] The present invention will be further described below in conjunction with the embodiments with reference to the accompanying drawings.

[0030] Figure 1 This is a schematic diagram of the traditional 24T1C circuit architecture.

[0031] Figure 2 It is a waveform diagram of the traditional 24T1C circuit under high temperature and threshold voltage negative bias 1.5V conditions.

[0032] Figure 3 This is a waveform diagram of a traditional 24T1C circuit under high temperature and 2V negative threshold voltage conditions.

[0033] Figure 4 It is a schematic diagram of the 27T1C display circuit architecture structure of the utility model.

[0034] Figure 5 It is a waveform diagram of the 27T1C circuit of the utility model under the conditions of high temperature and negative threshold voltage of 1.5V.

[0035] Figure 6 It is a waveform diagram of the 27T1C circuit of the utility model under the conditions of high temperature and negative threshold voltage of 2V. DETAILED DESCRIPTION

[0036] See also Figure 4 The utility model provides a novel display circuit, including a pre-charging circuit module and an output circuit module, and also including a closing and voltage stabilizing circuit module, wherein the pre-charging circuit module and the output circuit module are respectively connected to the closing and voltage stabilizing circuit module;

[0037] The shutdown and voltage stabilization circuit module includes transistors T2, T3, T12, T13, T15, T8, T21, T22, T9, T23, T5, T5-2, T6 and T6-2;

[0038] The gate of the transistor T2, the gate of T12, the drain of T13, the drain of T15 and the pre-charging circuit module are connected to point Q, and the output circuit module is connected to point Q;

[0039] The drain of the transistor T2, the gate of T3, the gate of T5-2 and the gate of T5 are connected, and a node P1 is provided on the connection line of the drain of T2, the gate of T3, the gate of T5-2 and the gate of T5;

[0040] The drain of the transistor T12, the gate of T13, the gate of T6-2 and the gate of T6 are connected, and a node P2 is provided on the connection line of the drain of T12, the gate of T13, the gate of T6-2 and the gate of T6;

[0041] The source of the transistor T2, the source of T3, the source of T12, and the source of T13 are all connected to the voltage signal VGL1;

[0042] The gate of the transistor T23 is connected to the Q point, the drain of the transistor T23 is connected to the gate of T21 and the drain of T8, and the source of the transistor T23 is connected to the voltage signal VGL1;

[0043] The source of the transistor T21 and the gate and source of T8 are commonly connected to the signal V1, and the drain of the transistor T21 is connected to the node P1;

[0044] The source of the transistor T22 and the gate and source of T9 are commonly connected to the signal V2 , the gate of the transistor T22 and the drain of T9 are commonly connected to the drain of the transistor T23 , and the drain of the transistor T22 is connected to the node P2 .

[0045] Specifically, the shutdown and voltage stabilization circuit module also includes transistors T18, T19, T10, T11, T14, T14-2, T16, T17 and T20;

[0046] The gate of the transistor T10 is connected to the signal V2, the drain of the transistor T10 is connected to the node P1, and the source of the transistor T10 is connected to the voltage signal VGL1;

[0047] The gate of the transistor T11 is connected to the signal V1, the source of the transistor T11 is connected to the voltage signal VGL1, and the drain of the transistor T11 is connected to the node P2;

[0048] The gates of the transistors T18 and T19 are commonly connected to the signal Xn-4, the drain of the transistor T18 is connected to the node P1, the drain of the transistor T19 is connected to the node P2, the sources of the transistors T18 and T19 and the source of T15 are commonly connected to the voltage signal VGL1, and the gate of the transistor T15 is connected to the signal CLR;

[0049] The drain of the transistor T5-2 is connected to the output circuit module, and the source of the transistor T5-2 is connected to the voltage signal VGL1;

[0050] The gate of the transistor T14-2 is connected to the signal CLR, the drain of the transistor T14-2 is connected to the output circuit module, and the source of the transistor T14-2 is connected to the voltage signal VGL1;

[0051] The gates of the transistors T16 and T17 are connected to the signal CLR-P, the sources of the transistors T16 and T17 are connected to the voltage signal VGL1, the drain of the transistor T16 is connected to the node P1, and the drain of the transistor T17 is connected to the node P2;

[0052] The source of the transistor T5 is connected to the voltage signal VGL2, and the drain of the transistor T5 is connected to the output circuit module;

[0053] The source of the transistor T6-2 is connected to the voltage signal VGL1, and the drain of the transistor T6-2 is connected to the output circuit module;

[0054] The source of the transistor T6 is connected to the voltage signal VGL2, and the drain of the transistor T6 is connected to the output circuit module;

[0055] The gate of the transistor T20 is connected to the signal Xn+4, the source of the transistor T20 is connected to the voltage signal VGL2, and the drain of the transistor T20 is connected to the output circuit module;

[0056] The gate of the transistor T14 is connected to the signal CLR, the source of the transistor T14 is connected to the voltage signal VGL2, and the drain of the transistor T14 is connected to the output circuit module.

[0057] Specifically, the pre-charging circuit module includes transistors T1 and T7, the drains of the transistors T1 and T7 are connected to the gates of transistors T2 and T12 and the drains of transistors T3 and T15 and then connected to the Q point, the gate and source of the transistor T1 are connected to the signal Xn-4, the gate of the transistor T7 is connected to the signal Xn+4, and the source of the transistor T7 is connected to transistors T18, T19 and T15 and then connected to the voltage signal VGL1.

[0058] Specifically, the output circuit module includes a capacitor C1, transistors T4 and T4-2, the gates of the transistors T4 and T4-2 are connected to the Q point, the sources of the transistors T4 and T4-2 are connected to the signal CK, the drain of the transistor T4-2 is connected to the drains of T5-2, T14-2 and T6-2 and then connected to the signal output terminal Xn, one end of the capacitor C1 is connected to the gates of the transistors T4 and T4-2, and the other end of the capacitor C1 is connected to the drains of the transistors T4, T5, T6, T20 and T14 and then connected to the signal output terminal Gn.

[0059] In the pre-charge stage, the voltage at point Q increases, transistor T23 is turned on, and the gates of transistors T21 and T22 are written with voltage signal VGL1, so that transistors T21 and T22 are turned off, thereby making it impossible for transistors T8 and T9 to charge nodes P1 and P2. Point P is always maintained at a low potential, and point Q is only affected by the leakage of the device. It can still form a voltage twice that of point Q in the voltage regulation stage to ensure the output of Gout.

[0060] Please compare Figure 2 and Figure 5 As shown in the waveform diagram, in the pre-charge stage, the 27T1C circuit of the present invention turns off the transistors T21 and T22 through the transistor T23, and the P point is always maintained at a low potential. After the pre-charge stage, the P point is always maintained at a low potential, and the leakage level of the Q point is significantly lower than that of the 24T1C circuit. Therefore, the level of the double voltage of the Q point in the voltage stabilization stage is better than that of the 24T1C circuit, and the Gout output capacity is more stable.

[0061] Please compare Figure 3 and Figure 6 As shown in the waveform diagram, under the influence of the increased negative bias of the threshold voltage, the device is more prone to leakage. In the pre-charge stage of the traditional 24T1C circuit, due to the increased leakage of the Q point, the P point cannot continue to maintain a low potential, and the Q point voltage is further lowered, resulting in the inability to form a double voltage at the Q point in the voltage stabilization stage, and Gout has no output. In comparison, in the pre-charge stage, the 27T1C circuit of the utility model turns off transistors T21 and T22 through transistor T23, and the P point is always maintained at a low potential. The Q point is only affected by the leakage of the device, and can still form a double voltage at the Q point in the voltage stabilization stage to ensure the output of Gout.

[0062] Although the specific implementation methods of the present invention are described above, those skilled in the art should understand that the specific embodiments described are only illustrative and are not intended to limit the scope of the present invention. Equivalent modifications and changes made by those skilled in the art in accordance with the spirit of the present invention should be included in the scope of protection of the claims of the present invention.

Claims

1. A novel display circuit, comprising a pre-charging circuit module and an output circuit module, characterized in that: It also includes a closing and voltage stabilizing circuit module, and the pre-charging circuit module and the output circuit module are respectively connected to the closing and voltage stabilizing circuit module; The shutdown and voltage stabilization circuit module includes transistors T2, T3, T12, T13, T15, T8, T21, T22, T9, T23, T5, T5-2, T6 and T6-2; The gate of the transistor T2, the gate of T12, the drain of T13, the drain of T15 and the pre-charging circuit module are connected to point Q, and the output circuit module is connected to point Q; The drain of the transistor T2, the gate of T3, the gate of T5-2 and the gate of T5 are connected, and a node P1 is provided on the connection line of the drain of T2, the gate of T3, the gate of T5-2 and the gate of T5; The drain of the transistor T12, the gate of T13, the gate of T6-2 and the gate of T6 are connected, and a node P2 is provided on the connection line of the drain of T12, the gate of T13, the gate of T6-2 and the gate of T6; The source of the transistor T2, the source of T3, the source of T12, and the source of T13 are all connected to the voltage signal VGL1; The gate of the transistor T23 is connected to the Q point, the drain of the transistor T23 is connected to the gate of T21 and the drain of T8, and the source of the transistor T23 is connected to the voltage signal VGL1; The source of the transistor T21 and the gate and source of T8 are commonly connected to the signal V1, and the drain of the transistor T21 is connected to the node P1; The source of the transistor T22 and the gate and source of T9 are commonly connected to the signal V2 , the gate of the transistor T22 and the drain of T9 are commonly connected to the drain of the transistor T23 , and the drain of the transistor T22 is connected to the node P2 .

2. A novel display circuit as claimed in claim 1, characterized in that: The shutdown and voltage stabilization circuit module also includes transistors T18, T19, T10, T11, T14, T14-2, T16, T17 and T20; The gate of the transistor T10 is connected to the signal V2, the drain of the transistor T10 is connected to the node P1, and the source of the transistor T10 is connected to the voltage signal VGL1; The gate of the transistor T11 is connected to the signal V1, the source of the transistor T11 is connected to the voltage signal VGL1, and the drain of the transistor T11 is connected to the node P2; The gates of the transistors T18 and T19 are commonly connected to the signal Xn-4, the drain of the transistor T18 is connected to the node P1, the drain of the transistor T19 is connected to the node P2, the sources of the transistors T18 and T19 and the source of T15 are commonly connected to the voltage signal VGL1, and the gate of the transistor T15 is connected to the signal CLR; The drain of the transistor T5-2 is connected to the output circuit module, and the source of the transistor T5-2 is connected to the voltage signal VGL1; The gate of the transistor T14-2 is connected to the signal CLR, the drain of the transistor T14-2 is connected to the output circuit module, and the source of the transistor T14-2 is connected to the voltage signal VGL1; The gates of the transistors T16 and T17 are connected to the signal CLR-P, the sources of the transistors T16 and T17 are connected to the voltage signal VGL1, the drain of the transistor T16 is connected to the node P1, and the drain of the transistor T17 is connected to the node P2; The source of the transistor T5 is connected to the voltage signal VGL2, and the drain of the transistor T5 is connected to the output circuit module; The source of the transistor T6-2 is connected to the voltage signal VGL1, and the drain of the transistor T6-2 is connected to the output circuit module; The source of the transistor T6 is connected to the voltage signal VGL2, and the drain of the transistor T6 is connected to the output circuit module; The gate of the transistor T20 is connected to the signal Xn+4, the source of the transistor T20 is connected to the voltage signal VGL2, and the drain of the transistor T20 is connected to the output circuit module; The gate of the transistor T14 is connected to the signal CLR, the source of the transistor T14 is connected to the voltage signal VGL2, and the drain of the transistor T14 is connected to the output circuit module.

3. A novel display circuit as claimed in claim 2, characterized in that: The pre-charging circuit module includes transistors T1 and T7, the drains of the transistors T1 and T7 are connected to the gates of the transistors T2 and T12 and the drains of the transistors T3 and T15 and then connected to the Q point, the gate and source of the transistor T1 are connected to the signal Xn-4, the gate of the transistor T7 is connected to the signal Xn+4, and the source of the transistor T7 is connected to the transistors T18, T19 and T15 and then connected to the voltage signal VGL1.

4. A novel display circuit as claimed in claim 2, characterized in that: The output circuit module includes a capacitor C1, transistors T4 and T4-2, the gates of the transistors T4 and T4-2 are connected to the Q point, the sources of the transistors T4 and T4-2 are connected to the signal CK, the drain of the transistor T4-2 is connected to the drains of T5-2, T14-2 and T6-2 and then connected to the signal output terminal Xn, one end of the capacitor C1 is connected to the gates of the transistors T4 and T4-2, and the other end of the capacitor C1 is connected to the drains of the transistors T4, T5, T6, T20 and T14 and then connected to the signal output terminal Gn.