Image sensor and electronic device

Abstract

The utility model provides an image sensor and an electronic device, and the image sensor comprises a semiconductor substrate which comprises a plurality of pixel units arranged in an array; the interconnection layer is located on the semiconductor substrate; the storage element layer is located on the semiconductor substrate and comprises a plurality of storage units arranged in an array mode, and the storage units correspond to the pixel units; wherein the storage unit comprises a first polar plate structure and a second polar plate structure, the first polar plate structure comprises an accommodating area, and the second polar plate structure is electrically led out through the accommodating area based on an interconnection layer. According to the utility model, the storage element layer is arranged in the interconnection layer, and the storage unit corresponds to the pixel unit, so that the arrangement of the storage element can be effectively realized, the compactness of the device layout can be improved, the lead-out mode of another polar plate structure is realized through the interconnection layer based on the design of the accommodating area, and the process design and the implementation mode can be further optimized.

Description

Technical Field

[0001] The utility model belongs to the technical field of image sensor structure and preparation, in particular to an image sensor and electronic equipment. Background Art

[0002] Image sensors are an important component of digital cameras. Depending on the components, they can be divided into two categories: CCD (Charge Coupled Device) and CMOS (Complementary Metal-Oxide Semiconductor). With the continuous development of CMOS integrated circuit manufacturing technology, especially the design and manufacturing technology of CMOS image sensors, CMOS image sensors have gradually replaced CCD image sensors and become the mainstream. CMOS image sensors have the advantages of low voltage, low power consumption, low cost and high integration, and have important application value in the fields of machine vision, consumer electronics, high-definition monitoring and medical imaging.

[0003] With the development of image sensors, some storage elements are often required in pixel circuits. For example, they can be used to receive the charge overflowed from the photoelectric conversion element under high light, can be used to perform quantization of the signal of photoelectric conversion under different gains, can also be used to store parts to achieve global exposure, etc. However, due to factors such as the limited space for device preparation and the complexity of the preparation process caused by performance requirements, it is difficult to obtain effectively configured storage elements and to form an effective layout of storage elements in image sensors.

[0004] Therefore, how to provide an image sensor and a method for manufacturing the same, and an electronic device to solve the problems in the prior art that it is difficult to effectively arrange storage elements in the image sensor and it is difficult to effectively simplify the process.

[0005] It should be noted that the above introduction to the technical background is only for the convenience of providing a clear and complete description of the technical solutions of this application and for the convenience of understanding by those skilled in the art. It cannot be considered that the above technical solutions are well known to those skilled in the art simply because they are described in the background technology section. Utility Model Content

[0006] In view of the above-mentioned shortcomings of the prior art, the purpose of the present invention is to provide an image sensor and a method for preparing the same, and an electronic device, so as to solve the problems in the prior art that storage elements are difficult to be effectively configured in image sensors and that it is difficult to form an effective layout of storage elements.

[0007] In order to achieve the above-mentioned object and other related objects, the utility model provides an image sensor, comprising:

[0008] A semiconductor substrate, wherein the semiconductor substrate comprises a plurality of pixel units arranged in an array;

[0009] an interconnect layer, the interconnect layer being located on the semiconductor substrate;

[0010] A storage element layer is located on the semiconductor substrate, and the storage element layer includes a plurality of storage units arranged in an array, and the storage units are arranged corresponding to the pixel units; wherein:

[0011] The storage unit includes a first plate structure and a second plate structure, the first plate structure includes a receiving area, and the second plate structure is electrically led out through the receiving area and based on the interconnection layer.

[0012] Optionally, the first electrode plate structure includes a receiving opening and a electrode plate main body surrounding the receiving opening, wherein the receiving opening defines the receiving area, and the first electrode plate structure realizes electrical lead-out based on the electrode plate main body.

[0013] Optionally, the electrode body includes a capacitor configuration portion and an electrical lead-out portion, the capacitor configuration portion is arranged opposite to the second electrode structure, the electrical lead-out portion extends from a side of the second electrode structure and realizes electrical lead-out of the first electrode structure based on the electrical lead-out portion.

[0014] Optionally, the storage unit includes a first electrode lead-out structure, a first contact region is provided between the first electrode lead-out structure and the first electrode plate structure, and electrical lead-out of the first electrode plate structure is achieved based on the first contact region and through the electrode plate main body.

[0015] Optionally, when the electrode plate main body includes the capacitor configuration portion and the electrical lead-out portion, the electrical lead-out portion extends from a side portion of the second electrode plate structure toward the semiconductor substrate to form a position control region.

[0016] Optionally, the storage unit includes a second electrode lead-out structure, a second contact area is provided between the second electrode lead-out structure and the second electrode plate structure, and the orthographic projection of the second contact area on the surface of the semiconductor substrate is located within the orthographic projection of the accommodating area on the surface of the semiconductor substrate, so as to realize the electrical lead-out of the second electrode plate structure based on the second contact area.

[0017] Optionally, the second electrode plate structure includes at least two second electrode plate layers, and each of the second electrode plate layers includes a lead-out area corresponding to the accommodating area, and the lead-out area of ​​each second electrode plate layer is electrically connected through the second electrode lead-out structure.

[0018] Optionally, in each of the lead-out areas corresponding to the accommodating area, there are two adjacent lead-out areas that are in direct contact with each other or have an interlayer dielectric layer.

[0019] Optionally, the first electrode plate structure includes at least two first electrode plate layers corresponding to the second electrode plate layers.

[0020] Optionally, the interconnection layer includes a transition layer located on the semiconductor substrate, the second electrode structure includes a bottom second electrode layer located on the surface of the transition layer, the first electrode structure includes a bottom first electrode layer located on the bottom second electrode layer, the bottom first electrode layer extends from the surface of the bottom second electrode layer to the transition layer to form a bottom contact portion, and a capacitor dielectric layer is formed at least between the bottom contact portion and the surface of the transition layer.

[0021] Optionally, the first electrode plate structure has an inclined portion arranged on a peripheral side of the accommodating area.

[0022] Optionally, the storage unit and the pixel unit are arranged in correspondence with each other, wherein the center of the storage unit and the center of the pixel unit using the storage unit are arranged in correspondence with each other up and down.

[0023] Optionally, the pixel unit has a capacitor connection point, the storage unit has a pixel connection point, the pixel connection point includes an electrical lead-out point of the first plate structure and the second plate structure, and the capacitor connection point is electrically connected to the corresponding pixel connection point through the interconnect layer.

[0024] Optionally, the storage unit includes at least two storage sub-elements, and the arrangement of the at least two storage sub-elements includes:

[0025] Each of the storage sub-elements is independently arranged, or there are at least two storage sub-elements that share the first plate structure, or the first plate structure of each storage sub-element is shared and correspondingly includes at least two second plate structures, and the shared first plate structure includes a accommodating area corresponding to the number of second plate structures.

[0026] Optionally, the first electrode structure further includes a wiring area spaced apart from the accommodating area, and the interconnection layer includes a plurality of interconnection contact pillars, which are arranged corresponding to the wiring area to achieve electrical connection of the devices to be connected.

[0027] Optionally, the interconnection layer includes a first wiring structure layer, and the first electrode lead-out structure, the second electrode lead-out structure and the interconnection contact pillar all extend to the first wiring structure layer and are electrically connected through the first wiring structure layer.

[0028] Optionally, the interconnection contact pillar, the first electrode lead-out structure, and the second electrode lead-out structure are all of the same depth.

[0029] Optionally, the storage unit has a symmetry axis along a first direction, and the wiring area and the lead-out area of ​​the first plate structure are arranged along the first direction, wherein when the storage unit includes at least two storage sub-elements, each of the storage sub-elements is arranged along a second direction different from the first direction and is disposed on both sides of the symmetry axis.

[0030] The utility model also provides an electronic device, comprising the image sensor as described in any one of the above solutions.

[0031] The utility model also provides a method for preparing an image sensor as described in any one of the above solutions. In addition, the above image sensor structure of the utility model can also be prepared by other methods, wherein:

[0032] The preparation method comprises the following steps:

[0033] Providing the semiconductor substrate comprising a plurality of pixel units arranged in an array;

[0034] The interconnection layer and the storage element layer are prepared on the semiconductor substrate to obtain the image sensor, wherein the storage element layer is formed during the preparation of the interconnection layer.

[0035] Optionally, preparing the interconnect layer and the storage element layer comprises the following steps:

[0036] preparing a first interconnect layer on the semiconductor substrate;

[0037] Preparing a first electrode plate structure and a second electrode plate structure having an accommodation area on the first interconnect layer;

[0038] A second interconnect layer is prepared on the first interconnect layer having the first electrode plate structure and the second electrode plate structure formed thereon; wherein:

[0039] During the process of preparing the second interconnection layer, the first electrode lead-out structure, the second electrode lead-out structure and the interconnection contact pillar penetrating the second interconnection layer are formed.

[0040] Optionally, in the process of preparing the first electrode plate structure and the second electrode plate structure having the accommodation area, the method includes:

[0041] forming an interlayer dielectric material layer between the first plate structure and the second plate structure;

[0042] Etching the interlayer dielectric material layer to obtain a second electrode plate structure consisting of at least two second electrode plate layers, wherein two adjacent second electrode plate layers are in direct contact with each other;

[0043] Alternatively, based on the interlayer dielectric material layer, a second electrode plate structure consisting of at least two second electrode plate layers is obtained, and two adjacent second electrode plate layers are isolated by the interlayer dielectric material layer.

[0044] As described above, the image sensor and electronic device of the present invention can improve the compactness of the device layout by arranging the storage element layer in the interconnection layer and corresponding the storage unit to the pixel unit, and effectively realize the arrangement of the storage element in the image sensor. Based on the design method of the accommodating area and the lead-out method of realizing another electrode structure through the interconnection layer in the existing image sensor, the layout design of the storage element and the lead-out structure can be further optimized, the storage capacity of the storage element can be improved, and the image quality can be optimized. BRIEF DESCRIPTION OF THE DRAWINGS

[0045] Figure 1 Shown is a basic structural block diagram of an image sensor system.

[0046] Figure 2 Shown is a schematic diagram of a pixel circuit corresponding to a pixel unit in an image sensor.

[0047] Figure 3 Shown is a flow chart for preparing an image sensor according to an embodiment of the present application.

[0048] Figure 4 Shown is a schematic diagram of the structure of forming a first interconnect layer in the preparation of an image sensor according to an embodiment of the present application.

[0049] Figure 5-10 It is a schematic diagram showing a structure obtained by forming a first electrode plate structure and a second electrode plate structure in the preparation of an image sensor according to an embodiment of the present application.

[0050] Figure 11-14 Shown is a schematic diagram of forming a second interconnect layer during the preparation of an image sensor according to an embodiment of the present application.

[0051] Fig.15 Shown is a top view of a structure obtained during the preparation of an image sensor according to an embodiment of the present application.

[0052] Fig.16 Shown is a top view of the corresponding structure of the semiconductor substrate and the storage element layer in an embodiment of the present application.

[0053] Fig.17 Shown is a three-dimensional diagram of the corresponding structure of the semiconductor substrate and the storage element layer in the embodiment of the present application.

[0054] Fig.18 Shown is a top view of another structure obtained during the preparation of the image sensor according to an embodiment of the present application.

[0055] Fig.19 Shown is a performance comparison chart of two image sensor structures in the embodiment of the present application.

[0056] Fig. 20 Shown is a cross-sectional view of the structure of another image sensor obtained in an embodiment of the present application.

[0057] Figure 21-26 It is a schematic diagram showing another structure obtained by forming a first electrode plate structure and a second electrode plate structure in the preparation of an image sensor according to an embodiment of the present application.

[0058] Fig. 27 Shown is a cross-sectional view of the structure of yet another image sensor obtained in an embodiment of the present application.

[0059] Component number description

[0060] 100 Semiconductor Substrate

[0061] 100a pixel unit

[0062] 200a First interconnect layer

[0063] 200b Second interconnect layer

[0064] 201 First dielectric layer

[0065] 202 First interconnect wiring layer

[0066] 203 Etch stop layer

[0067] 204 Transition Layer

[0068] 205 Second dielectric layer

[0069] 206a, 206b, 206c interconnection contact holes

[0070] 207 conductive material layer

[0071] 208a Second electrode lead structure

[0072] 208b First electrode lead structure

[0073] 208c Interconnect Contact Pillar

[0074] 209 Second interconnect wiring layer

[0075] 300 Storage Component Layer

[0076] 300a Storage Unit

[0077] 302 bottom second plate layer

[0078] 305 First Plate Structure

[0079] 305a Accommodating opening

[0080] 305b Plate body

[0081] 308 upper second plate layer

[0082] 309 Second Plate Structure DETAILED DESCRIPTION

[0083] The following is an explanation of the implementation of the present invention through specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through other different specific implementations, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention.

[0084] It should be emphasized that the term “include / comprises” when used herein refers to the presence of features, integers, steps or components, but does not exclude the presence or addition of one or more other features, integers, steps or components.

[0085] Features described and / or illustrated with respect to one embodiment may be used in the same or similar manner in one or more other embodiments, combined with features in other embodiments, or substituted for features in other embodiments.

[0086] For example, when describing the embodiments of the present invention in detail, for the sake of convenience, the cross-sectional diagrams showing the device structure will not be partially enlarged according to the general scale, and the schematic diagrams are only examples, which should not limit the scope of protection of the present invention. In addition, in actual production, the three-dimensional dimensions of length, width and depth should be included.

[0087] For ease of description, spatially relative terms such as "under", "below", "below", "below", "above", "on", etc. may be used herein to describe the relationship of one element or feature shown in the drawings to other elements or features. It will be understood that these spatially relative terms are intended to encompass other orientations of the device in use or operation in addition to the orientation depicted in the drawings. In addition, when a layer is referred to as being "between" two layers, it can be the only layer between the two layers, or one or more intervening layers may also be present.

[0088] In the context of the present application, a structure in which a first feature is described as being "above" a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features are formed between the first and second features, such that the first and second features may not be in direct contact.

[0089] It should be noted that the illustrations provided in this embodiment are only used to illustrate the basic concept of the present invention in a schematic manner, and therefore the illustrations only show components related to the present invention rather than being drawn according to the number, shape and size of components in actual implementation. In actual implementation, the type, quantity and proportion of each component may be changed at will, and the component layout may also be more complicated.

[0090] The contents proposed in the present invention are described in detail below in conjunction with the accompanying drawings provided in the present invention.

[0091] Figure 1 The basic structure block diagram of an image sensor system is shown. The image sensor includes a readout circuit and a control circuit connected to a pixel array. In addition, a functional logic unit is connected to the readout circuit, and the readout circuit and the control circuit are connected to a status register to realize the control of the pixel array. The pixel array includes a plurality of pixels (P1, P2, P3) arranged in rows (R1, R2, R3...Ry) and columns (C1, C2, C3...Cx). The pixel signal output by the pixel array is output to the readout circuit via the column line. In some applications, after the pixel acquires the image data, it is read out using the readout mode specified by the status register and then transmitted to the functional logic unit. In a specific implementation, the readout circuit may include an analog-to-digital conversion (ADC) circuit and other circuits.

[0092] In some applications, the status register may include a programmable selection system to determine whether the readout system is exposed and readout through a rolling shutter mode or a global shutter mode. The functional logic unit may store raw image data or image data after image processing. In some implementations, the readout circuit may read out a row of image data at a time along the readout column line. Of course, other methods may also be used to read out the image data. The operation of the control circuit can be determined by the current setting of the status register. For example, the control circuit generates a shutter signal for controlling image acquisition. In some applications, this shutter signal can be a global exposure signal so that all pixels of the pixel array simultaneously acquire their image data through a single acquisition window. In other applications, this shutter signal can also be a rolling exposure signal so that the pixels of each pixel row of the pixel array continuously implement exposure reading operations through the acquisition window.

[0093] Figure 2 A schematic diagram of a pixel unit in an image sensor is shown. Figure 2 As shown in the figure, each pixel unit includes a photoelectric conversion element (e.g., a photodiode) and a pixel circuit (as shown in the dotted box in the figure). The photodiode can be a buried photodiode (PPD) used in current image sensors. In one application example, the pixel circuit includes a reset transistor (RST), a source follower transistor (SF), and a pixel selection transistor (RS), which are connected to the transistors shown in the figure. Figure 2 The transfer transistor (TX) and photodiode shown in . In a stacked structure application example, the pixel circuit includes a reset transistor, a source follower transistor, a pixel selection transistor disposed on a first circuit chip, and also includes a transfer transistor disposed on a second circuit chip, and the photodiode in the second circuit chip is connected to other transistors in the first circuit chip based on the transfer transistor. In a further application example, the pixel circuit may also include a gain control transistor (DCG) connected between a floating diffusion region (FD) and a reset transistor. During operation, the photoelectric conversion element generates photocharges in response to incident light during exposure, the transfer transistor is connected to a transfer signal, which controls the transfer transistor to transfer the accumulated charge in the photoelectric conversion element to the floating diffusion region, the reset transistor is connected between the power supply voltage and the floating diffusion region, responds to the reset signal to reset the sensor pixel circuit (for example, discharges or charges the floating diffusion region and the photodiode to the current voltage), the floating diffusion region is connected to the gate of the source follower transistor, the source follower transistor is connected between the power supply voltage and the pixel selection transistor, responds to the potential of the floating diffusion region and outputs it, the pixel selection transistor connects the source follower transistor and the bit line, responds to the pixel selection control signal to implement pixel selection readout and outputs it to the readout column.

[0094] However, in existing image sensors, due to factors such as limited space for device preparation and complicated preparation processes caused by performance requirements, it is difficult to obtain effectively configured storage elements, difficult to form an effective layout of storage elements in image sensors, and difficult to achieve storage element preparation through effective processes, etc., which limits the improvement of image quality formed by image sensors. The image sensor and preparation method of the present application can effectively solve the above problems, and will be described in detail below in conjunction with specific embodiments.

[0095] Embodiment 1:

[0096] See also Figure 3 As shown, this embodiment provides a method for preparing an image sensor and a corresponding structure. Figure 3 The flowchart of the preparation method is shown, wherein the preparation method comprises the following steps:

[0097] S1: providing a semiconductor substrate including a plurality of pixel units arranged in an array;

[0098] S2: preparing an interconnection layer and a storage element layer on a semiconductor substrate to obtain an image sensor, wherein the storage element layer is formed during the preparation of the interconnection layer.

[0099] In this embodiment, the storage element layer is prepared during the preparation process of the interconnection layer of the image sensor. The storage element can be arranged and prepared by means of existing processes and structures, which can simplify the process and save costs.

[0100] See also Figure 4-14 As shown, in this embodiment, preparing the interconnection layer and the storage element layer includes the following steps:

[0101] First, if Figure 4 As shown, a first interconnection layer 200a is prepared on a semiconductor substrate.

[0102] Specifically, the semiconductor substrate ( Figure 4 (not shown) can be any structure in the field of image sensors for preparing various functional areas of image sensors. Based on the semiconductor substrate, photosensitive elements, various pixel transistors of CMOS image sensors can be prepared, and interconnection wiring can be performed. Among them, the semiconductor substrate can be a structure composed of a single layer of material, including but not limited to a silicon substrate. The elements in each area are prepared in the silicon substrate, and its material can be single crystal silicon, single crystal germanium, polycrystalline silicon, amorphous silicon, and can also be silicon germanium compounds, etc.

[0103] In addition, the semiconductor substrate can also be a stacked structure composed of two or more material layers, and each region is prepared in any required layer. For example, the semiconductor substrate includes a silicon substrate and an epitaxial layer (EPI) formed on the silicon substrate, and photoelectric conversion elements and transistor components (such as charge transfer elements) are prepared in the epitaxial layer. Further, a back-illuminated image sensor can be prepared based on the above structure. Of course, the semiconductor substrate can also be silicon on insulator SOI, etc. In addition, the semiconductor substrate can also have N-type doped or P-type doped regions so that the devices prepared therein meet the functional requirements.

[0104] Specifically, the first interconnection layer 200a may be a part of a structural layer prepared on a semiconductor substrate for realizing electrical connection and lead-out of each transistor in an image sensor, and may be a part of an interconnection structure of an existing image sensor. Each structural layer may be prepared using existing materials and processes.

[0105] In one example, the first interconnect layer 200a includes a first dielectric layer 201, which is formed on a semiconductor substrate, and a first interconnect wiring layer 202 is formed in the first dielectric layer 201. Further, the first interconnect layer 200a may also include an etch stop layer 203 formed on the first interconnect wiring layer 202. The material of the first dielectric layer 201 includes but is not limited to silicon oxide, the material of the etch stop layer 203 includes but is not limited to silicon nitride, and the material of the first interconnect wiring layer 202 includes but is not limited to copper.

[0106] In an optional example, the first interconnect layer 200a includes a transition layer 204, which is formed on the first interconnect wiring layer 202. When the etch stop layer 203 is formed, the transition layer 204 is formed on the surface of the etch stop layer 203. The transition layer 204 can be formed by a thermal oxidation process, and the material can be silicon oxide. The subsequent preparation of the storage element layer 300 is facilitated on the basis of the transition layer 204.

[0107] Then, if Figure 5-10 As shown, a first plate structure 305 having an accommodation region and a second plate structure 309 are prepared on the first interconnect layer 200 a to form a storage element layer 300 .

[0108] In this embodiment, the method for preparing the first electrode plate structure 305 and the second electrode plate structure 309 includes:

[0109] like Figure 5 As shown, a bottom second electrode material layer 301 is prepared on the first interconnect layer 200a. The material of the bottom second electrode material layer 301 includes but is not limited to Cu and TIN, and can be formed based on a PVD process. When a transition layer 204 is formed, the bottom second electrode material layer 301 is prepared on the surface of the transition layer 204.

[0110] like Figure 6 As shown, the bottom second electrode plate material layer 301 is etched to obtain the bottom second electrode plate layer 302;

[0111] like Figure 7 As shown, a first interlayer dielectric material layer 303 and a bottom first electrode material layer 304 are deposited on the first interconnect layer 200a to obtain the bottom second electrode layer 302;

[0112] Among them, when the transition layer 204 is formed, the first interlayer dielectric material layer 303 is formed on the surface of the bottom second electrode layer 302 and further extends to form on the surface of the transition layer 204, and can be used as an intermediate layer and a capacitor dielectric layer for subsequently realizing the first electrode structure 305. The setting of the transition layer 204 can be beneficial to the preparation of the storage element layer and its arrangement in the device.

[0113] like Figure 8 As shown, the bottom first electrode material layer 304 is etched to obtain the first electrode layer 305; in this embodiment, in the step of preparing the first electrode layer 305, an accommodation area for leading out the second electrode structure 309 is formed, which is beneficial to the design of the overall structure of the capacitor and the flexible design of the lead-out components.

[0114] like Fig. 9 As shown, a second interlayer dielectric material layer 306 and an upper second electrode material layer 307 are deposited on the structure of the first electrode layer 305; the upper second electrode material layer 307 is at least located in the accommodation area;

[0115] like Fig.10 As shown, the upper second electrode material layer 307 is etched to obtain an upper second electrode layer 308 .

[0116] At this point, the first plate structure 305 and the second plate structure 309 are prepared, wherein, in this embodiment, the first plate layer directly constitutes the first plate structure, and it can be understood that, in order to simplify the description, the same reference numerals are used here to replace. In addition, the bottom second plate layer 302 and the upper second plate layer 308 constitute the second plate structure 309 in this embodiment, which can function together as a plate after forming a storage element.

[0117] In this embodiment, an interlayer dielectric material layer is formed between the first plate structure 305 and the second plate structure 309, that is, the first interlayer dielectric material layer 303 and the second interlayer dielectric material layer 306, as the dielectric layer between the plates of the storage element (capacitor), and its material can be selected as an hk dielectric layer. In one example, its material can be selected as HfOx, AlO or a stack thereof. In addition, the material of the plate layer of each plate structure in the storage element includes but is not limited to Cu and TIN. Among them, in the second plate structure 309 composed of at least two layers of second plate layers, there are two adjacent layers of second plate layers isolated by an interlayer dielectric material layer, that is, in this embodiment, the second plate structure 309 composed of two layers of second plate layers, the bottom second plate layer 302 and the upper second plate layer 308, and the two layers of second plate layers are isolated by the first interlayer dielectric material layer 303 and the second interlayer dielectric material layer 306 to form a storage element.

[0118] Finally, if Figure 11-14 As shown, a second interconnection layer 200b is prepared on the first plate structure 305 and the second plate structure 309; during the preparation of the second interconnection layer 200b, a first electrode lead-out structure 208a, a second electrode lead-out structure 208b and an interconnection contact column 208c that penetrate the second interconnection layer 200b are prepared to realize the electrical lead-out of the first plate structure 305 and the second plate structure 309 and the electrical connection of the devices to be connected.

[0119] In this embodiment, the method for preparing the second interconnection layer 200b includes:

[0120] First, if Fig.11 As shown, a second dielectric layer 205 is formed on the first interconnect layer 200a having the first plate structure 305 and the second plate structure 309, wherein the material of the second dielectric layer 205 includes but is not limited to silicon oxide, and can be deposited by PVD or CVD;

[0121] Then, if Fig.12 As shown, interconnection contact holes are prepared in the second dielectric layer 205. Fig.12 There are three interconnection contact holes 206a, 206b, and 206c, which can be prepared by photolithography-etching process;

[0122] In one example, the interconnection contact holes 206a, 206b, and 206c penetrate the second dielectric layer 205. Further, in this example, there is an interconnection contact hole 206b that penetrates the first plate structure 305 to subsequently realize the electrical lead-out of the first plate structure 305, and there is an interconnection contact hole 206a that penetrates the second plate structure 309 to subsequently realize the electrical lead-out of the second plate structure 309. In addition, in other examples, the depths of the interconnection contact holes 206b and the interconnection contact holes 206a can also be other ways, as long as the electrical connection of the corresponding plate structures can be realized based on the filled conductive material. In addition, due to the existence of the accommodation area, the depth configuration of the interconnection contact holes 206b and the interconnection contact holes 206a can be more flexible, and the etching conditions can be flexibly selected.

[0123] In a further example, there is also an interconnection contact hole 206c, the interconnection layer includes a first wiring structure layer 202, the interconnection contact hole 206c penetrates the second dielectric layer 205 and extends to the first wiring structure layer 202 and is electrically connected, thereby realizing electrical connection or lead-out of devices in the image sensor based on the first wiring structure layer 202.

[0124] In an optional example, the interconnection contact holes 206a, 206b, and 206c all extend to the first wiring structure layer 202, wherein the interconnection contact holes 206a, 206b, and 206c can respectively correspond to the first wiring structure blocks 202a, 202b, and 202c in different first wiring structure layers 202, and the formed interconnection contact holes expose the corresponding wiring structure blocks to prevent short circuits between each other. The above method can effectively realize the electrical lead-out of the first electrode structure 305 and the second electrode structure 309, and has less restriction on the depth of the lead-out structure, and short circuits are not easy to occur between each other. In addition, it can be prepared by the same process as the contact column structure in the interconnection layer, thereby simplifying the process.

[0125] Continue, as Fig.13As shown, a conductive material layer 207 is filled in each interconnection contact hole, so as to prepare a first electrode lead-out structure 208b, a second electrode lead-out structure 208a and an interconnection contact column 208c based on the conductive material layer 207. In this embodiment, the conductive material layer 207 is filled into each interconnection contact hole and extends to cover the second dielectric layer 205. The conductive material layer can be prepared based on a PVD process, and the material includes but is not limited to copper.

[0126] Finally, if Fig.14 As shown, after forming the conductive material layer 207, it can be ground by a CMP process to obtain an electrical connection structure that fills each interconnection contact hole, such as a first electrode lead-out structure 208b, a second electrode lead-out structure 208a, and an interconnection contact column 208c. Further, a second interconnection wiring layer 209 can be prepared on the basis of each electrical connection structure. The material of the first interconnection wiring layer 209 includes but is not limited to copper. The second interconnection wiring layer 209 can include a plurality of second wiring structure blocks 209a, 209b, and 209c. Each second wiring structure block is electrically connected to the electrical connection structure to further complete the electrical connection of the structure to be connected. Of course, in other examples, other methods can also be used to prepare the second wiring structure blocks 209a, 209b, and 209c and the corresponding first electrode lead-out structure 208b, the second electrode lead-out structure 208a, and the interconnection contact column 208c, such as forming the two into an integrated structure.

[0127] At this point, a storage element layer and a corresponding electrical lead-out structure are preliminarily formed in the interconnect layer. It should be noted that the first wiring structure layer 202 and the second interconnect wiring layer 209 can be metal wiring layers of different layers in the interconnect layer. For example, the image sensor includes five metal wiring layers, and the first wiring structure layer 202 and the second interconnect wiring layer 209 can be the fourth and fifth layers therein, in which the storage element layer is arranged.

[0128] See also Figure 14-17 As shown, corresponding to the above-mentioned preparation method, this embodiment provides an image sensor, wherein the structural arrangement and material selection in the image sensor can refer to the description in the method, and similar features are not repeated here. Of course, the image sensor in this embodiment can also be prepared by other methods. The image sensor includes: a semiconductor substrate 100, an interconnection layer and a storage element layer 300.

[0129] The semiconductor substrate 100 includes a plurality of pixel units 100a arranged in an array. The pixel unit 100a may be any pixel unit in an existing image sensor, including a photoelectric conversion element and a corresponding pixel circuit. The pixel units 100a arranged in rows and columns may form an M×N pixel array, where M and N are both integers greater than 1. Of course, the pixel array may also be a pixel array in which odd rows and even rows are arranged alternately. Fig.16In the illustrated example, a pixel unit 100 a is shown in which four photoelectric conversion elements share a structure.

[0130] The interconnection layer is located on the semiconductor substrate 100 and is used to realize the electrical connection and electrical lead-out of the image sensor devices. It can be composed of several layers of dielectric layers and metal layers and several conductive pillars CT. The material of the dielectric layer includes but is not limited to silicon oxide, and the material of the metal layer and the conductive pillar includes but is not limited to copper, corresponding to the first interconnection layer 200a and the second interconnection layer 200b described in the preparation method.

[0131] The storage element layer 300 includes a plurality of storage units 300a arranged in an array, and the storage unit 300a corresponds to the pixel unit 100a. The correspondence between the two means that the storage unit 300a is used to implement the functions required in the pixel unit 100a. It can be that one storage unit 300a corresponds to one pixel unit 100a, or one storage unit 300a corresponds to at least two pixel units 100a. Of course, in other embodiments, one pixel unit 100a can correspond to at least two storage units 300a.

[0132] In one example, the storage unit 300a and the pixel unit 100a are arranged in a manner corresponding to each other, that is, the storage unit 300a and the pixel unit 100a are arranged in a manner corresponding to each other, and in one implementation, the center of the storage unit 300a is aligned with the center of the pixel unit 100a. Further, in a group of pixel units 100a and storage units 300a, the storage unit 300a can be used to implement the use of the pixel units 100a corresponding to the same group. Of course, in other implementations, sharing or other methods can also be used.

[0133] Among them, Fig.16 As shown, in an optional example, four photoelectric conversion elements share a pixel unit 100a, and the storage units 300a in the storage element layer 300 are arranged in an array, one pixel unit 100a corresponds to one storage unit 300a, and the two are arranged in a corresponding position up and down, and the centers of the two are aligned. Based on the corresponding storage units 300a and pixel units 100a, it is beneficial to achieve a reasonable layout of the device space, and to achieve optimization of signal transmission and wiring design.

[0134] In addition, if Fig.17As shown, in one example, the pixel unit 100a has a capacitor connection point 208a', and the storage unit 300a has a pixel connection point, and the pixel connection point includes an electrical lead-out point of a first plate structure and a second plate structure, for example, the second plate lead-out structure 208a is shown in the figure, and the capacitor connection point 208a' is electrically connected to the corresponding pixel connection point through an interconnection layer. The figure also shows that there is a metal wiring layer in other interconnection layers between the semiconductor substrate and the storage element layer, and the connection between the pixel and the storage element can be further realized based on the intermediate connection point 208a" thereon. The design method of this example can be conducive to interconnecting pixels and storage units based on corresponding settings, which can improve parasitic effects and improve the signal-to-noise ratio.

[0135] It should be noted that the storage element in the storage element unit can be used for signal accumulation, storage, and quantization, etc. For example, the pixel unit may have a conversion gain control element, and the storage element is used to realize signal quantization under the corresponding gain (such as a lower gain); the pixel unit may have an overflow path, and during the exposure process, the charge signal generated in the photoelectric conversion element overflows to the corresponding storage element for storage of the exposure signal; it may also be used for storing low-sensitivity photoelectric conversion element signals in a circuit that achieves dynamic range improvement or solves LED flicker suppression through photoelectric conversion elements with different high and low sensitivities, so as to adapt to the generation of charge signals for long-term exposure; in addition, it may also be in a global exposure circuit, including a globally transferred charge signal and / or a reset signal, and the storage element can be used for temporary storage of the above-mentioned signals, so as to read out and quantize them from the storage element in the subsequent quantization step.

[0136] Continue to see Fig.14 and Fig.15 As shown, the storage unit 300a includes a first plate structure 305 and a second plate structure 309. The first plate structure 305 includes a receiving area, and the second plate structure 309 is electrically led out through the receiving area and based on the interconnection layer. The design of the receiving area is conducive to flexible electrical lead-out of the first plate structure 305 and the second plate structure 309, which is convenient for compact lead-out, thereby forming a compact correspondence with the pixel unit, and is convenient for lead-out through the interconnection layer, which is conducive to alleviating the parasitic capacitance caused by the lead-out structure.

[0137] like Fig.14As shown, in this embodiment, the first plate structure 305 includes an accommodating opening 305a and a plate body 305b surrounding the accommodating opening 305a, the accommodating opening 305a defines an accommodating area, the first plate structure 305 realizes electrical lead-out based on the plate body 305b, and the second plate structure 309 realizes electrical lead-out through the accommodating opening 305a. In this example, the accommodating area is formed by defining an opening, so that the accommodating area corresponding to the accommodating opening and the plate body 305 used for electrical lead-out of the first plate structure are separated, so that the depth design and process selection of the electrical lead-out structure of the second plate structure 309 can be flexibly performed.

[0138] In a further example, the electrode body 305b includes a capacitor configuration portion and an electrical lead-out portion, which can be seen in Fig.14 In the dotted line in the first plate structure 305, the left side is the capacitor configuration part, and the right side is the electrical lead-out part, wherein the capacitor configuration part is arranged opposite to the second plate structure 309, and the electrical lead-out part extends from the side of the second plate structure 309 and realizes the electrical lead-out of the first plate structure 305 based on the electrical lead-out part.

[0139] In this example, when the electrode body 305b includes the capacitor configuration portion and the electrical lead-out portion, the electrode body has an electrical lead-out portion extending from the second electrode structure 309, so that the position of the electrical lead-out portion can be flexibly designed based on the electrical lead-out portion to achieve electrical lead-out of the first electrode structure 305. In this example, the electrical lead-out portion extends from the side of the second electrode structure 309 toward the direction of the semiconductor substrate to form a position control area. Through the position control area in this example, the first electrode structure can be moved toward the part of the second electrode structure where an electrical lead-out connection is required, such as Fig.14 As shown, the moving distance of the first electrode plate structure is s, so that the height difference between the first electrode plate structure and the bottom second electrode plate layer is reduced, wherein, to realize the electrical lead-out of the second electrode plate structure, it is necessary to prepare the second electrode lead-out structure 208a to the bottom second electrode plate layer 302, which can be beneficial to the realization of the electrical lead-out of the two electrode plate structures and the design of their preparation process, and can also be beneficial to the arrangement of the first interlayer dielectric material layer 303 and the second interlayer dielectric material layer 306 between the electrodes.

[0140] Continue to see Fig.14 As shown, the memory cell includes a first electrode lead-out structure 208b, and the first electrode lead-out structure 208b and the first electrode plate structure 305 have a first contact region 305c, so as to realize electrical lead-out of the first electrode plate structure 305 based on the first contact region 305c, and the first contact region may be a region corresponding to electrical interconnection.

[0141] Continue to see Fig.14As shown, the memory cell includes a second electrode lead-out structure 208a, the second electrode lead-out structure 208a and the second electrode plate structure 309 have a second contact area 302a, and the orthographic projection of the second contact area 302a on the surface of the semiconductor substrate is located within the orthographic projection of the accommodation area (accommodation opening 305a) on the surface of the semiconductor substrate, so as to realize the electrical lead-out of the second electrode plate structure 309 based on the second contact area 302a. Among them, forming the accommodation opening based on the etching process and forming the second electrode lead-out structure 208a based on the etching and filling process is conducive to accurately defining the position corresponding to the second contact area 302a, thereby improving the product yield.

[0142] In an optional example, for the second plate structure 309, there is an interlayer dielectric layer between two adjacent lead-out portions in each lead-out portion of the corresponding accommodation area. In this example, there are a first interlayer dielectric material layer 303 and a second interlayer dielectric material layer 306, and the interlayer dielectric layer also exists between the sidewalls of the first plate structure 305 and the corresponding second plate structure 309, which can further increase the capacitance value and improve the area utilization rate.

[0143] Continue to see Fig.14 As shown, in one example, the interconnection layer includes a transition layer 204 located on the semiconductor substrate, the second plate structure 309 includes a bottom second plate layer disposed on the surface of the transition layer, that is, the bottom second plate layer 302, the first plate structure 305 includes a bottom first plate layer located on the bottom second plate layer, and the bottom first plate layer extends from the surface of the bottom second plate layer to the transition layer 204 to form a bottom contact portion, so as to realize the electrical lead-out of the first plate structure 305 based on the bottom contact portion. Further, there is a first interlayer dielectric material layer 303 between the bottom first plate layer and the transition layer 204, and the formation of the transition layer 204 can be beneficial to the mutual influence between the blocking and the lower material layer, and in addition, it is beneficial to prepare different material layers based on the compatibility of the transition layer 204, so that different material layers with good performance can be obtained on its upper surface.

[0144] See also Fig.15 As shown, in one example, the storage unit includes at least two storage sub-elements, that is, they may have different plate structures for potential connection to form at least two capacitors. Of course, in other examples, a storage unit may have only one storage sub-element, including a first plate structure and a second plate structure. The arrangement of the at least two storage sub-elements includes:

[0145] Each storage sub-element is independently arranged. For example, taking two storage sub-elements as an example, it includes two independent first plate structures and corresponding two independent second plate structures, which are respectively connected to form two storage sub-elements. Alternatively, the arrangement can also be: there are at least two storage sub-elements with a shared first plate structure, that is, for two of the storage sub-elements, the first plate structure is shared and the second plate structure is independently arranged, and two storage sub-elements are formed by applying different voltages to the second plate structure. Of course, in this arrangement, there are at least two unshared first plate structures, that is, the first plate structure in a storage unit is not completely shared, and there is a spacing area, which can also realize the separation of storage sub-elements. Alternatively, the arrangement can also be: the first plate structure of each storage sub-element is shared and includes at least two second plate structures, so that in this arrangement, the independent division of the storage sub-element is realized by the second plate structure. Wherein, when storing in the shared first plate structure, the first plate structure includes a corresponding number of accommodation areas as the second plate structure. Of course, it should be noted that the discrete storage sub-elements can also play the role of the same storage sub-element through the connection of potentials and the electrical connection of contact points. Fig.15 In the example shown, the memory cell 300a includes a shared first plate structure 305 and two second plate structures 309 , and the first plate structure 305 includes two receiving areas (eg, receiving openings 305a ) corresponding to the number of the first plate structure 305 to obtain two memory sub-elements.

[0146] Continue to see Fig.15 As shown, in one example, the first plate structure 305 also includes a wiring area 305d spaced apart from the accommodation area, and the interconnection layer includes a plurality of interconnection contact pillars 208c, and the interconnection contact pillars 208c are arranged corresponding to the wiring area 305d to achieve electrical connection of the device to be connected. The spacing arrangement can be considered as an opening in two different first plate structures. In this example, the accommodation area opening is surrounded by the material layer of the first plate structure, and the opening corresponding to the wiring layer is a recessed opening extending inward from the edge of the first plate structure.

[0147] In this example, for the storage unit 300a, by effectively arranging various areas, for example, the accommodating area (accommodating opening 305a) located in the first plate structure 305, the area corresponding to the first contact area 305c, the wiring area 305d, etc., it is beneficial to achieve a reasonable layout of the storage unit, while realizing the electrical connection of the capacitor plates, further realizing the arrangement of the interconnection contact pillars in the interconnection layer to realize the electrical connection of the image sensor device.

[0148] In a further example, the depths of the first electrode lead-out structure 208b and the second electrode lead-out structure 208a are consistent, and further, the interconnection contact pillar 208c and the first electrode lead-out structure 208b and the second electrode lead-out structure 208a are consistent in depth. The consistent depth can be understood as the lowest depth of each structure (shown in the figure as the depth position close to the first interconnect wiring layer 202 side) can be within a fluctuation range, and this fluctuation range can be designed in actual process, which is conducive to the three being prepared based on the same process and completing the functions of their respective structures. Of course, the three can have exactly the same depth and stop at the same depth surface.

[0149] In one example, the interconnection layer includes a first wiring structure layer 202, and the first electrode lead structure 208b, the second electrode lead structure 208a and the interconnection contact pillar 208c all extend to the first wiring structure layer 202, see Fig.14 As shown, the electrical connection of the first electrode lead-out structure 208b, the second electrode lead-out structure 208a and the interconnection contact pillar 208c is respectively realized through the first wiring structure layer 202. In this example, all three are connected to the first wiring structure layer 202 and contact the corresponding first wiring blocks 202a, 202b, and 202c, so that the electrical lead-out of the storage element capacitor plate structure can be realized based on the process conditions of the interconnection contact pillar 208c.

[0150] Continue to see Fig.15 As shown, in one example, the storage unit has a symmetry axis along a first direction, as shown by the dot-dash line in the figure, the wiring area and the first contact area 305c are arranged along the first direction, and are further symmetrically arranged relative to the symmetry axis. When the storage unit includes at least two storage sub-elements, each storage sub-element is arranged along a second direction different from the first direction and is arranged on both sides of the symmetry axis, wherein, when there are two shared first plate structures, the corresponding first contact areas 305c are shared, that is, the electrical lead-out of the first plate structure is realized based on the same position, and the figure includes a shared first plate structure 305 and two independent second plate structures 309, and the second plate structures 309 are distributed on both sides of the symmetry axis, and are symmetrically distributed in this example. The first direction and the second direction are different, and the two can be respectively for the row direction and column direction of the pixel array.

[0151] See also Fig.18 and Fig.19 As shown, Fig.18It is shown as a configuration mode of a storage sub-element in a storage unit 300a. In this example, there are two first plate structures 305 and four second plate structures 309. The four second plate structures 309 share two first plate structures in pairs, thereby obtaining four corresponding storage sub-elements. For the four storage sub-elements, the two first plate structures 305 can be connected to the same potential, and the two second plate structures 309 corresponding to different first plate structures 305 can be connected to the same potential, thereby actually forming two effective storage sub-element working modes, that is, each first plate structure corresponds to one storage sub-element. Of course, other application modes can also be used, which are set according to actual needs.

[0152] in, Fig.19 The middle curve is compared Fig.15 Layout of storage units and Fig.18 The change trend of the capacitance value and readout noise corresponding to the layout of the storage unit as the size of the storage unit changes. The horizontal axis represents the change of the size of the storage unit, the solid line represents the change trend of the capacitance value of the storage element as the size of the storage unit changes, and the solid line represents the change trend of the readout noise in the pixel unit corresponding to the change of the size of the storage unit. Fig.18 The curve obtained by the storage cell layout shown is on the right Fig.15 The curve obtained by the storage cell layout shown in FIG. 1 is a graph showing the storage cell layout of FIG. 1 . During operation, the potential applied to the first plate structure in the two layout structures is the same. Fig.18 In the embodiment, two second plate structures sharing the same first plate structure apply the same potential, so that two different potentials (the values ​​may be the same or different) are applied to the four second plate structures, thereby obtaining two effective storage sub-elements. Fig.15 In the embodiment, all the second plate structures share the same first plate structure, and different potentials (the values ​​can be the same or different) are applied to the two second plate structures, thereby obtaining two effective storage sub-elements. It should be noted that, except for the different configurations of the first plate structure and the second plate structure, the other features of the two layouts can refer to the design of the prior art memory. It can be seen that the total capacitance of the two storage sub-elements sharing the same first plate structure on the right has an obvious trend of increasing as the size of the storage unit increases, and the total read noise of the two storage sub-elements has an obvious trend of decreasing as the size of the storage unit increases, which is beneficial to the improvement of device performance. That is to say, in this arrangement, different storage sub-elements are obtained by sharing the first plate structure throughout the pixel unit and by setting different second plate structures, and arranging the accommodation area corresponding to the second plate structure for electrical extraction and arranging the wiring area separated from the accommodation area, so as to realize the configuration and interconnection wiring of the capacitor, which is beneficial to increase the effective area of ​​the capacitor when the size of the storage unit changes, and improve the device performance.

[0153] See also Fig. 20 As shown, in one example, the second electrode plate structure 309 includes at least two second electrode plate layers 302, 308, and each second electrode plate layer 302, 308 includes a lead-out portion corresponding to the accommodating area, and the lead-out portion of each second electrode plate layer 302, 308 is electrically connected through the second electrode lead-out structure 208a.

[0154] In this example, the first plate structure 305 also includes a first plate layer 310. That is, the first plate structure 309 includes a number of first plate layers corresponding to the number of second plate layers of the second plate structure 309, thereby increasing the capacitance of the storage element and improving the area utilization rate based on the layout design of the present application in a limited space.

[0155] Also, see Fig. 27 As shown, in one example, the first plate structure 305 has an inclined portion, which is arranged on the peripheral side of the accommodation area. That is to say, the first plate structure 305 is configured to have a side portion with an inclined structure. In this example, the side portion is formed when the accommodation opening 305a is formed. The formation of the inclined portion is conducive to improving the storage capacity of the storage element. In addition, it is conducive to the realization of the accommodation opening. For example, in this example, it can be realized on the bottom second plate layer through the first interlayer dielectric material layer 303 and the first plate material layer 307, so as to facilitate the etching process, and then facilitate the direct contact between the upper second plate layer 308 and the bottom second plate layer 302. Optionally, the acute angle of the inclination between the semiconductor substrate surface is greater than or equal to 30° and less than 90°, for example, it can be selected as 45°, 60°, 80°, etc.

[0156] Embodiment 2:

[0157] See also Figure 21-26 As shown, this embodiment provides another method for preparing an image sensor and a corresponding structure. The same parts of this embodiment 2 as those of embodiment 1 can refer to the description in embodiment 1. The following mainly introduces the main differences between this embodiment 2 and embodiment 1 in the preparation method and the obtained structure.

[0158] In the second embodiment, during the preparation of the first plate structure 305 and the second plate structure 309:

[0159] like Fig.21 As shown, after etching the first electrode material layer 304 to obtain the first electrode layer 305, the first interlayer dielectric material layer 303 is also etched to obtain a first interlayer dielectric layer 303', and the first interlayer dielectric layer 303' reveals the surface of the bottom second electrode layer 302;

[0160] like Fig. 22As shown, a second interlayer dielectric material layer 306 is prepared on the structure formed with the first electrode layer 305 and the first interlayer dielectric layer 303', and the second interlayer dielectric material layer 306 is in contact with the exposed surface of the second electrode layer 302;

[0161] like Fig.23 As shown, the second interlayer dielectric material layer 306 is etched to obtain a second interlayer dielectric layer 306', and the second interlayer dielectric layer 306' exposes the surface of the bottom second electrode layer 302;

[0162] like Fig.24 As shown, an upper second electrode material layer 307 is deposited on the structure with the exposed second electrode layer 302 surface;

[0163] like Fig.25 As shown, the upper second electrode material layer 307 is etched to obtain an upper second electrode layer 308 .

[0164] like Fig.26 As shown, a second interconnection layer 200b is further prepared to obtain an image sensor.

[0165] In this embodiment, for the second electrode structure 309, the bottom second electrode layer 302 is in direct contact with the upper second electrode layer 308, and there is direct contact between two adjacent lead-out areas in the lead-out areas of each second electrode structure in the corresponding accommodating area, thereby simplifying device preparation and facilitating the connection of capacitor signals and layout optimization.

[0166] Embodiment three:

[0167] The utility model also provides an electronic device, including the image sensor described in any one of the above-mentioned embodiments 1 and 2. The electronic device can be a security monitoring, vehicle-mounted electronics, mobile phone camera, machine vision and other equipment, and the image sensor based on the utility model can obtain high-quality image information.

[0168] In summary, the utility model can improve the compactness of the device layout by arranging the storage element layer in the interconnection layer and making the storage unit correspond to the pixel unit, effectively realize the arrangement of the storage element in the image sensor, and based on the design of the accommodation area, realize the lead-out method of the other plate structure through the interconnection layer in the existing image sensor, and further optimize the layout design of the storage element and the lead-out structure, improve the storage capacity of the storage element, and optimize the image quality. Therefore, the utility model effectively overcomes various shortcomings in the prior art and has a high industrial utilization value.

[0169] The above embodiments are merely illustrative of the principles and effects of the present invention, and are not intended to limit the present invention. Anyone familiar with the technology may modify or change the above embodiments without violating the spirit and scope of the present invention. All equivalent modifications or changes made by those with ordinary knowledge in the relevant technical field without departing from the spirit and technical ideas disclosed in the present invention shall still be covered by the claims of the present invention.

Claims

1. An image sensor, characterized in that: The image sensor comprises: A semiconductor substrate comprising a plurality of pixel units arranged in an array; an interconnection layer, located on the semiconductor substrate; A storage element layer is located on the semiconductor substrate, and the storage element layer includes a plurality of storage units arranged in an array, and the storage units correspond to the pixel units; wherein: The storage unit includes a first plate structure and a second plate structure, the first plate structure includes a receiving area, and the second plate structure is electrically led out through the receiving area and based on the interconnection layer.

2. The image sensor according to claim 1, wherein: The first electrode plate structure includes a receiving opening and a electrode plate main body surrounding the receiving opening, wherein the receiving opening defines the receiving area, and the first electrode plate structure realizes electrical lead-out based on the electrode plate main body.

3. The image sensor according to claim 2, wherein: The main body of the electrode plate includes a capacitor configuration portion and an electrical lead-out portion, the capacitor configuration portion is arranged opposite to the second electrode plate structure, the electrical lead-out portion extends from the side of the second electrode plate structure and the electrical lead-out of the first electrode plate structure is realized based on the electrical lead-out portion; and / or, the storage unit includes a first electrode lead-out structure, a first contact area is provided between the first electrode lead-out structure and the first electrode plate structure, and the electrical lead-out of the first electrode plate structure is realized based on the first contact area and through the main body of the electrode plate.

4. The image sensor according to claim 3, wherein: When the electrode plate main body includes the capacitor configuration portion and the electrical lead-out portion, the electrical lead-out portion extends from a side portion of the second electrode plate structure toward the semiconductor substrate to form a position control region.

5. The image sensor according to claim 1, wherein: The storage unit includes a second electrode lead-out structure, a second contact area is provided between the second electrode lead-out structure and the second electrode plate structure, and the orthographic projection of the second contact area on the surface of the semiconductor substrate is located within the orthographic projection of the accommodating area on the surface of the semiconductor substrate, so as to realize the electrical lead-out of the second electrode plate structure based on the second contact area.

6. The image sensor according to claim 5, characterized in that The second electrode plate structure includes at least two second electrode plate layers, and each of the second electrode plate layers includes a lead-out region corresponding to the accommodating region, and the lead-out regions of each of the second electrode plate layers are electrically connected through the second electrode lead-out structure.

7. The image sensor according to claim 6, wherein: In each of the lead-out areas corresponding to the accommodating area, there are two adjacent lead-out areas that are in direct contact with each other or have an interlayer dielectric layer; and / or, the first electrode plate structure includes at least two first electrode plate layers corresponding to at least two second electrode plate layers.

8. The image sensor according to claim 1, wherein: The interconnection layer includes a transition layer located on the semiconductor substrate, the second electrode structure includes a bottom second electrode layer located on the surface of the transition layer, the first electrode structure includes a bottom first electrode layer located on the bottom second electrode layer, the bottom first electrode layer extends from the surface of the bottom second electrode layer to the transition layer to form a bottom contact portion, at least a capacitor dielectric layer is formed between the bottom contact portion and the surface of the transition layer; and / or the first electrode structure has an inclined portion, and the inclined portion is arranged on the peripheral side of the accommodating area.

9. The image sensor according to claim 1, wherein: The storage unit and the pixel unit are arranged in correspondence with each other, including that the center of the storage unit and the center of the pixel unit using the storage unit are arranged in correspondence with each other up and down; and / or, the pixel unit has a capacitor connection point, the storage unit has a pixel connection point, the pixel connection point includes the electrical lead-out point of the first plate structure and the second plate structure, and the capacitor connection point is electrically connected to the corresponding pixel connection point through the interconnection layer.

10. The image sensor according to claim 1, wherein: The storage unit includes at least two storage sub-elements, and the arrangement of the at least two storage sub-elements includes: Each of the storage sub-elements is independently arranged, or there are at least two storage sub-elements that share the first plate structure, or the first plate structure of each storage sub-element is shared and correspondingly includes at least two second plate structures, and the shared first plate structure includes a accommodating area corresponding to the number of second plate structures.

11. The image sensor according to any one of claims 1 to 10, characterized in that: The first electrode structure further includes a wiring area spaced apart from the accommodation area, and the interconnection layer includes a plurality of interconnection contact pillars, which are arranged corresponding to the wiring area to realize electrical connection of the devices to be connected.

12. The image sensor according to claim 11, wherein: The interconnection layer includes a first wiring structure layer, and the storage unit includes a first electrode lead-out structure and a second electrode lead-out structure; wherein the first electrode lead-out structure, the second electrode lead-out structure and the interconnection contact column all extend to the first wiring structure layer, and / or the depths of the interconnection contact column, the first electrode lead-out structure and the second electrode lead-out structure are all consistent.

13. The image sensor according to claim 11, wherein: The storage cell has a symmetry axis along a first direction, and the wiring area and the lead-out area of ​​the first plate structure are arranged along the first direction, wherein when the storage cell includes at least two storage sub-elements, each of the storage sub-elements is arranged along a second direction different from the first direction and is disposed on both sides of the symmetry axis.

14. An electronic device, characterized in that: The electronic device comprises the image sensor as claimed in any one of claims 1-13.

Images