Servo control system

Abstract

The utility model relates to a servo control system, and the system comprises a CPU which is used for connecting an upper computer, receiving a position instruction of the upper computer, and converting the position instruction into a current instruction; the FPGA is connected with the CPU, is connected with each unit in the FOC module, and is used for receiving the current instruction and carrying out data processing on parameters of each unit in the FOC module to obtain target parameters; and the FOC module is used for performing field-oriented control processing based on the target parameter output by the FPGA and outputting a voltage control signal. By adopting the system, the servo control response speed can be improved.

Description

Technical Field

[0001] The present application relates to the technical field of servo control, and in particular to a servo control system. Background Art

[0002] The servo control system, also known as the follow-up system, is an automatic control system that enables the output of an object's position, orientation, state, etc. to change with any change in the input quantity. From the inside to the outside, the servo control includes three control systems: the current loop, the speed loop, and the position loop. The performance of the outer loop often depends on the performance of the inner loop, so the bottom current loop is the key to affecting the servo control effect.

[0003] FOC (Field-Oriented Control) is an efficient and widely used motor control algorithm, which is responsible for the control part of the current loop in the servo motor control system. In addition to the standard FOC, the control algorithm of the current loop is complex and varied, involving various calculation symbols such as addition, subtraction, multiplication, division, trigonometric functions, inverse trigonometric functions, square root, etc., which requires high flexibility. The common implementation method is to use MCU (Microcontroller Unit) for calculation. Although it meets the flexibility requirements, it is limited by the serial processing method of the CPU (Central Processing Unit) core, and it is difficult to meet the response speed requirements. Utility Model Content

[0004] Based on this, it is necessary to provide a servo control system to improve the servo response speed in response to the above technical problems.

[0005] A servo control system, comprising:

[0006] CPU, used for connecting to a host computer, receiving a position instruction from the host computer, and converting the position instruction into a current instruction;

[0007] FPGA, connected to the CPU and to each unit in the FOC module, for receiving the current instruction and performing data processing on the parameters of each unit in the FOC module to obtain target parameters;

[0008] The FOC module is used to perform magnetic field oriented control processing based on the target parameters output by the FPGA and output a voltage control signal.

[0009] In the above-mentioned servo control system, the CPU is connected to the host computer, the FPGA is connected to the CPU and is used to process the data of the parameters required by each unit in the FOC module to obtain the target parameters, and the FOC module is used to perform magnetic field oriented control processing based on the target parameters and output a voltage control signal; since the traditional CPU is a serial processing method with a slow response speed, in each embodiment of the present application, the parameters originally calculated by the CPU are handed over to the FPGA for processing, and the FPGA participates in the intermediate data processing process of each unit of the FOC module, applying the advantage of FPGA's parallel processing, which greatly improves the response speed of servo control; in addition, correction algorithms can be added to the programmable FPGA as required, and the parameters required by each unit in the FOC module during calculation can also be modified, etc., to improve the flexibility of data processing and the accuracy of servo control; the current loop with the most frequent calculations and the lowest level of control is separated from the CPU and works independently, so that the CPU can completely handle the rest of the affairs without excessive intervention in the current loop control part, which not only improves the servo response speed, but also allows the CPU to have sufficient computing power to realize other functions. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Figure 1 A schematic diagram of the structure of a servo control system in one embodiment;

[0011] Figure 2 is a schematic structural diagram of a servo control device in another embodiment;

[0012] Figure 3 A schematic diagram of the connection relationship between the eFPGA and each unit in the FOC module in one embodiment;

[0013] Figure 4 FIG. 4 is a schematic diagram of the connection relationship between the eFPGA and external devices in an embodiment. DETAILED DESCRIPTION

[0014] It should be understood that the specific embodiments described herein are only used to explain the present application and are not used to limit the present application.

[0015] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0016] It should be noted that all directional indications in the embodiments of the present application (such as up, down, left, right, front, back, etc.) are only used to explain the relative position relationship, movement status, etc. between the components under a certain specific posture (as shown in the accompanying drawings). If the specific posture changes, the directional indication will also change accordingly. The connection can be a direct connection or an indirect connection.

[0017] In addition, in this application, descriptions such as "first", "second", etc. are only used for descriptive purposes and cannot be understood as indicating or implying their relative importance or implicitly indicating the number of technical features indicated. Therefore, the features defined as "first" and "second" may explicitly or implicitly include at least one of the features. In addition, the technical solutions between the various embodiments can be combined with each other, but they must be based on the ability of ordinary technicians in this field to implement them. When the combination of technical solutions is contradictory or cannot be implemented, it should be deemed that such combination of technical solutions does not exist and is not within the scope of protection required by this application.

[0018] The terms "first", "second", etc. used in this application may be used in this article to describe various elements, but these elements are not limited by these terms. These terms are only used to distinguish a first element from another element. For example, without departing from the scope of this application, a first unit may be referred to as a second unit, and similarly, a second unit may be referred to as a first unit. Both the first unit and the second unit are units, but they are not the same unit.

[0019] It can be understood that the “connection” in the following embodiments should be understood as “electrical connection”, “communication connection”, etc. if the connected circuits, modules, units, etc. have transmission of electrical signals or parameters with each other.

[0020] In one embodiment, Figure 1 FIG. 1 is a schematic diagram of the structure of a servo control system in one embodiment. Figure 1 The system includes a CPU 100, an FPGA 200 and a FOC module 300, and the FOC module 300 includes a first unit, a second unit, a third unit, etc. The CPU 100 is used to connect to a host computer, receive a position instruction from the host computer, and convert the position instruction into a current instruction; the FPGA 200 is connected to the CPU 100 and to each unit in the FOC module 300, and is used to receive a current instruction and perform data processing on the parameters of each unit in the FOC module 300 to obtain a target parameter; the FOC module 300 is used to perform a magnetic field oriented control process based on the target parameter output by the FPGA 200, and output a voltage control signal of the motor.

[0021] Specifically, FPGA200 may be eFPGA (embedded FPGA) or the like.

[0022] Specifically, the servo control system includes three control systems from the outside to the inside, namely, a position loop, a speed loop, and a current loop. The position loop and the speed loop are located in the CPU 100, and the current loop is located in the FPGA 200 (Field Programmable Gate Array). The CPU 100 is used to connect to the host computer, receive the position instruction containing the target position sent by the host computer, convert the position instruction into a speed instruction containing the target speed through the position loop, and convert the speed instruction into a current instruction containing the target current through the speed loop.

[0023] FPGA200 is connected to CPU100 and each unit in FOC module 300, and is used to receive current instructions and input the current instructions into FOC module 300; or perform data processing on the current instructions to obtain target parameters and input the target parameters into FOC module 300. Also, perform data processing on the parameters of each unit in FOC module 300 to obtain target parameters and output the target parameters to FOC module 300. Among them, the target parameters refer to the parameters after data processing by FPGA200. The data processing process is performed according to the algorithm added to FPGA200. For example, FPGA200 performs parameter compensation on the parameters output by the first unit in FOC module 300 according to the parameter compensation algorithm and then inputs them into the second unit. Alternatively, FPGA200 performs amplitude limiting processing on the parameters output by the second unit in FOC module 300 according to the amplitude limiting processing algorithm and then inputs them into the third unit, etc. Therefore, the control process can be corrected or adjusted by FPGA200. The parameter processing of each unit by FPGA200 and the processing in FOC module 300 are both part of the current loop control.

[0024] The FOC module 300 can be independent of the FPGA 200 or embedded in the FPGA 200. The FOC module 300 is used to perform field oriented control (FOC) processing based on the target parameters output by the FPGA 200, and finally convert it into a voltage control signal of the motor, that is, a PWM (Pulse Width Modulation) pulse signal, which is input into the three-phase inverter for voltage conversion, and the three-phase inverter outputs the voltage of the motor.

[0025] In this embodiment, the CPU is connected to the host computer, and the FPGA is connected to the CPU and is used to process the data of the parameters required by each unit in the FOC module to obtain the target parameters. The FOC module is used to perform magnetic field oriented control processing based on the target parameters and output a voltage control signal. Since the traditional CPU is a serial processing method with a slow response speed, in this embodiment, the parameters originally calculated by the CPU are handed over to the FPGA for processing, and the FPGA participates in the intermediate data processing process of each unit of the FOC module, applying the advantage of FPGA's parallel processing, which greatly improves the response speed of servo control. In addition, correction algorithms can be added to the programmable FPGA as required, and the parameters required by each unit in the FOC module during calculation can also be modified, etc., to improve the flexibility of data processing and the accuracy of servo control. The current loop with the most frequent calculations and the lowest level of control is separated from the CPU and works independently, so that the CPU can completely handle the rest of the affairs without excessive intervention in the current loop control part, which not only improves the servo response speed, but also allows the CPU to have sufficient computing power to realize other functions.

[0026] In one embodiment, the FPGA 200 is used to control the triggering of each unit in the FOC module 300 .

[0027] Specifically, the FPGA 200 may be used to control the triggering moment, delay time, etc. of each unit in the FOC module 300 , so that each unit in the FOC module 300 performs function triggering according to the trigger signal sent by the FPGA 200 .

[0028] In this embodiment, the triggering of each unit in the FOC module is implemented through FPGA, making the servo control system more flexible and versatile.

[0029] In one embodiment, the FOC module 300 is a hardware module, including a Clark transformation unit, a Park transformation unit, a PID regulator, an iPark transformation unit and a SVPWM unit connected in sequence.

[0030] Specifically, FPGA200 is connected to the Clark transform unit, Park transform unit, PID (Proportion Integration Differentiation, proportional-integral-differential) regulator, iPark transform unit and SVPWM (Space Vector Pulse Width Modulation, space vector pulse width modulation) vector control unit. The FOC module 300 is a hardware module, and the Clark transform unit, Park transform unit, PID regulator, iPark transform unit and SVPWM unit contained therein are also hardware units. There are also direct connection signals between the five hardware units. The calculation end signal of the previous hardware unit can trigger the calculation start of the next hardware unit, and automatically use the output result as the input parameter of the next hardware unit.

[0031] In this embodiment, FPGA 200 may obtain the voltage value output by PID, perform amplitude limiting processing on the voltage value, and input the voltage value after amplitude limiting processing into the iPark conversion unit.

[0032] In this embodiment, FPGA200 can obtain the three-phase duty cycle output by the SVPWM unit, perform dead zone compensation and then input the duty cycle into the three-phase inverter.

[0033] In this embodiment, the FOC module is made into a hardware module, which greatly improves the servo response speed.

[0034] In one embodiment, FPGA 200 is used to connect to an external device and communicate with the external device.

[0035] Specifically, FPGA 200 is connected to external devices via the peripheral bus, and accesses and controls the external devices, which is equivalent to a peripheral directly connected to the peripheral bus.

[0036] In this embodiment, a programmable FPGA is used to connect with external devices, and a new algorithm can be written into the FPGA to correct or adjust the control process, thereby improving the flexibility of servo control.

[0037] In one embodiment, FPGA 200 includes an encoder interface, which is used to communicate with the encoder through the encoder interface, obtain position feedback data of the encoder, and transmit the position feedback data to CPU 100 .

[0038] Specifically, the encoder is used to feedback the current position of the motor. This position value is an essential feedback data in servo control and will directly participate in the calculation of the three loops. The encoder interface is configured on FPGA200, and the encoder is communicated with the encoder through the encoder interface to obtain the encoder's position feedback data, and the position feedback data is transmitted to CPU100, so that CPU100 performs position loop control based on the position feedback data and the target position.

[0039] In this embodiment, there are currently a variety of encoder protocols, including incremental ABZ, bus-type ENDAT (bidirectional digital interface encoder) protocol, BISS protocol, SSI (Synchronous Serial interface), UART (Universal Asynchronous Receiver Transmitter) and private protocols of some encoder manufacturers, etc., so how to adapt to various types of encoder interface protocols is also a difficulty; and by setting the encoder communication interface in eFPGA200, due to the programmability of eFPGA200, it is easy to add various encoder interface protocols to achieve adaptation of any encoder interface protocol.

[0040] In one embodiment, FPGA200 includes an encoder interface for communicating with the encoder through the encoder interface, obtaining position feedback data of the encoder, performing speed calculation according to the position feedback data, obtaining speed feedback data, and transmitting the speed feedback data to CPU100.

[0041] Specifically, FPGA200 communicates with the encoder through the encoder interface to obtain position feedback data returned by the encoder, and performs speed calculation based on the position feedback data, such as position divided by time equals speed, to obtain speed feedback data. FPGA200 is used to transmit speed feedback data to CPU100.

[0042] In this embodiment, the speed calculation process is handed over to FPGA for processing, which can improve the servo response speed.

[0043] In one embodiment, FPGA 200 is used to connect to an ADC, receive current feedback data from the ADC, and perform data processing according to the current instruction and the current feedback data to obtain target parameters.

[0044] Specifically, FPGA200 is used to connect to ADC through the peripheral bus, and receive current feedback data obtained by ADC sampling the motor current, perform compensation processing, limiting processing, or filtering processing according to the current instruction containing the target current and the current feedback data, so as to obtain the target parameters and input them into the PID unit in the FOC module 300.

[0045] In this embodiment, the current feedback data processing of the ADC is separated from the CPU, and the FPGA is used to perform the intermediate data processing process to improve the servo control rate.

[0046] In one embodiment, FPGA 200 is used to connect to a wave-generating peripheral device, and is used to control the duty cycle and wave-generating time of the wave-generating peripheral device.

[0047] Specifically, FPGA200 is connected to the pulsating peripheral via the peripheral bus, and is used to control the duty cycle of the pulsating peripheral so that the pulsating peripheral sends a corresponding PWM signal according to the duty cycle. FPGA200 is also used to control the pulsating timing of the pulsating peripheral so that the pulsating peripheral sends a signal according to the pulsating timing.

[0048] In this embodiment, the FPGA controls the duty cycle and the timing of the waving peripheral. Since the FPGA is programmable, the duty cycle and the timing of the waving can be modified more easily.

[0049] In one embodiment, the device includes an interrupt controller, which is connected to the FOC module 300 and the FPGA 200 respectively, and is used to receive an interrupt request and send an interrupt request to the CPU 100 .

[0050] Specifically, the interrupt controller is used to connect to the FOC module 300 and FPGA200 respectively. When the magnetic field oriented control processing of the FOC module 300 is completed, the interrupt controller can be used to receive the interrupt request sent by the FOC module 300, send the interrupt request to the CPU100 through the FPGA200, or the interrupt controller directly sends the interrupt request to the CPU100, and the interrupt request is used to instruct the CPU100 to perform other operations.

[0051] In this embodiment, an interrupt controller is provided to receive an interrupt request sent by the FOC module and send the interrupt request to the CPU, so that the CPU can execute other operations in time, thereby improving the servo response speed.

[0052] In one embodiment, FPGA 200 includes registers for storing target parameters, as well as input parameters, output parameters, and calculation states of each unit of FOC module 300 .

[0053] Specifically, the calculation state may include the calculation process, the executed algorithm, etc. The input parameters of each unit of the FOC module 300 are directly mapped by the register of FPGA200, and the parameters of each unit can be modified or the trigger can be started by operating the register. The output results and calculation state of each unit are also mapped in the register of FPGA200 for reading. The parameters of each unit of the FOC module 300 can not only be directly controlled by the programmable logic of FPGA200, but also through the register mapping method, in conjunction with the interrupt controller, the CPU 100 can also directly access and control it through the peripheral bus, which is equivalent to the peripherals directly hung on the peripheral bus.

[0054] Optionally, the register may also store sampling current parameters of the ADC, such as current feedback data.

[0055] Optionally, the registers can also store position feedback data from the encoder.

[0056] In this embodiment, the FPGA stores target parameters, as well as input parameters, output parameters and calculation status of each unit of the FOC module through registers, and can quickly read parameters for calculation, thereby improving the servo control rate.

[0057] In one embodiment, FPGA 200 is used to implement one or more of over-current protection, speed calculation, and position compensation.

[0058] Specifically, one or more of the overcurrent protection function, speed calculation function, and position compensation function in the servo control system can be implemented through FPGA200, and most of the calculations are completed by FPGA200, which reduces the calculation time and greatly reduces the development difficulty.

[0059] In one embodiment, the conventional method uses CPU100 to perform magnetic field oriented control processing, but the conventional method is limited by the serial processing method of the CPU100 core and is difficult to meet the requirements of control accuracy and response speed. Therefore, each embodiment of the present application proposes an MCU chip with CPU100+FPGA200 as the basic architecture, which is suitable for the servo control field, and makes the five FOC-related algorithms into hardware, and the programmable FPGA200 participates in the intermediate interaction process, and the algorithm can be added as needed, thereby reducing the calculation time and the difficulty of FOC control development, and the chip area and performance requirements will not be very high. Figure 2As shown, it is a structural schematic diagram of a servo control device in another embodiment. Take FPGA200 as eFPGA200 for explanation. CPU100 and eFPGA200 can be integrated in MCU, and FOC module 300 is independent of eFPGA200. eFPGA200 contains an algorithm for data processing of each unit of FOC module 300. CPU100 receives the position instruction sent by the host computer through the host computer interface peripheral, performs position loop control processing on the position instruction, converts it into a speed instruction, and then performs speed loop control processing on the speed instruction, and converts the speed instruction into a current instruction. eFPGA200 receives the current instruction and inputs the current instruction into the FOC module 300; or performs current loop data processing on the current instruction to obtain the target parameter, and inputs the target parameter into the FOC module 300. The FOC module 300 is used to perform field oriented control (FOC) processing based on the target parameters output by the eFPGA 200, obtain the three-phase duty cycle, and finally convert it into a voltage control signal of the motor, that is, a three-phase PWM pulse signal, which is output to an external drive circuit such as a three-phase inverter to output a voltage for controlling the motor, which matches the position command. During this period, speed feedback, position feedback and current feedback are included. The eFPGA 200 receives the analog current signal of the external drive circuit through the ADC peripheral and obtains the current feedback data. Then, the eFPGA 200 can perform data processing based on the current command and the current feedback data to obtain the target parameters. The encoder position feedback data is obtained through the encoder interface, the position feedback data is transmitted to the CPU 100, and the position feedback data is subjected to speed calculation to obtain the speed feedback data, and the speed feedback data is transmitted to the CPU 100.

[0060] For the connection relationship between the eFPGA 200 and each unit in the FOC module 300, such as Figure 3As shown, it is a schematic diagram of the connection relationship between each unit in the eFPGA200 and the FOC module 300 in an embodiment. The FOC module 300 is a hardware module, including a Clark conversion unit, a Park conversion unit, a PID regulator, an iPark conversion unit and a SVPWM unit connected in sequence. The CPU100 interacts with the register list in the eFPGA200 through the peripheral bus interface. The interrupt register is connected to each unit of the FOC module 300 respectively, for receiving the interrupt request of each unit, and can send the interrupt request to the CPU100 through the eFPGA200 or directly send the interrupt request to the CPU100. The input parameters of each unit are directly mapped by the register of the eFPGA200, and the parameters of the unit can be modified or the trigger can be started by operating the register. The output parameters and calculation status of each unit are also mapped in the register of the eFPGA200 for reading. These five units can not only be directly controlled by the programmable logic of the eFPGA200, but also can be directly accessed and controlled by the CPU100 through the peripheral bus through the register mapping method, in conjunction with the interrupt controller, which is equivalent to five peripherals directly hung on the peripheral bus.

[0061] For the connection relationship between eFPGA200 and external devices, such as Figure 4 As shown, it is a schematic diagram of the connection relationship between eFPGA200 and external devices in one embodiment. Like other general MCUs, CPU100, eFPGA200 and various peripherals can be connected through the peripheral interconnect bus. eFPGA200 can be connected to the interrupt controller through the peripheral bus. The sampling current parameters (current feedback) of the ADC can be directly read by eFPGA200 and stored in the register list. eFPGA200 can also directly control the three-phase duty cycle size and update time of the wave-generating peripheral. eFPGA200 can directly communicate with the external encoder through the encoder interface and write the parameters to the bus register list. Each hardware unit in the FOC hardware module is directly connected to eFPGA200 to further improve the current loop response speed. The eFPGA200 has a built-in current loop control algorithm, and the parameters of each unit of the FOC module 300 are processed based on the current loop control algorithm to obtain the target parameters, and the target parameters are input into the corresponding unit to complete the magnetic field oriented control processing. The logic of overcurrent protection, speed calculation, position compensation, etc. is handed over to eFPGA200 for processing and the calculation results are written into the register list.

[0062] Therefore, the technical effects of this embodiment include the following five points:

[0063] (1) If applied to low-cost, low-precision control scenarios, the five algorithms can be set to direct connection mode. For example, after the Clark unit completes the calculation, the output parameters are directly transmitted to the Park unit and trigger its calculation, thus eliminating the need for users to perform secondary development.

[0064] (2) If there is a requirement for control accuracy, a new correction algorithm can be inserted between any two algorithms through eFPGA to improve the control effect. In this way, the control algorithm of the current loop can be modified anytime and anywhere, instead of being completely fixed like a dedicated IC.

[0065] (3) The current loop, which performs the most frequent calculations and has the lowest level of control, is made to work independently, allowing the CPU to completely handle the rest of the tasks without excessive intervention in the current loop control part. This not only improves control efficiency, but also allows the CPU to have sufficient computing power to implement more other functions.

[0066] (4) Scalability: eFPGA can access other peripherals (such as ADC, PWM, encoder interface, etc.) through the bus.

[0067] (5) Utilize the programmability of eFPGA to adapt to any encoder interface protocol.

[0068] The above description is only a preferred embodiment of the present application, and does not limit the patent scope of the present application. Any equivalent structure or equivalent process transformation made using the contents of the present application specification and drawings, or directly or indirectly applied in other related technical fields, are also included in the patent protection scope of the present application.

Claims

1. A servo control system, characterized in that: include: CPU, used for connecting to a host computer, receiving a position instruction from the host computer, and converting the position instruction into a current instruction; FPGA, connected to the CPU and to each unit in the FOC module, for receiving the current instruction and performing data processing on the parameters of each unit in the FOC module to obtain target parameters; The FOC module is used to perform magnetic field oriented control processing based on the target parameters output by the FPGA and output a voltage control signal.

2. The system according to claim 1, characterized in that The FPGA is used to control the triggering of each unit in the FOC module.

3. The system according to claim 1, characterized in that The FOC module is a hardware module, including a Clark conversion unit, a Park conversion unit, a PID regulator, an iPark conversion unit and a SVPWM unit which are connected in sequence.

4. The system according to claim 1, characterized in that The FPGA is used to connect to an external device and communicate with the external device.

5. The system according to claim 4, characterized in that The FPGA includes an encoder interface, which is used to communicate with an encoder through the encoder interface, obtain position feedback data of the encoder, and transmit the position feedback data to the CPU.

6. The system according to claim 4, characterized in that The FPGA includes an encoder interface, which is used to communicate with the encoder through the encoder interface, obtain position feedback data of the encoder, perform speed calculation according to the position feedback data, obtain speed feedback data, and transmit the speed feedback data to the CPU.

7. The system according to claim 4, characterized in that The FPGA is used to connect to the ADC, receive current feedback data from the ADC, perform data processing according to the current instruction and the current feedback data, and obtain target parameters.

8. The system according to claim 4, characterized in that The FPGA is used to connect to a wave-generating peripheral device, and is used to control the duty cycle and wave-generating time of the wave-generating peripheral device.

9. The system according to claim 1, characterized in that The system comprises an interrupt controller, which is connected to the FOC module and is used for receiving an interrupt request and sending the interrupt request to the CPU.

10. The system according to claim 1, characterized in that The FPGA includes registers, and the registers are used to store the target parameters, and input parameters, output parameters and calculation states of each unit of the FOC module.

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