Broadband single-ended to differential low noise amplifier and radio frequency receiver

Abstract

The utility model provides a broadband single-ended to differential low noise amplifier and a radio frequency receiver. The low-noise amplifier comprises a first-stage circuit and a second-stage circuit, wherein the first-stage circuit comprises a first-stage input end, two first-stage cascode output nodes, a first complementary cascode amplification structure and a first amplification output end; the two first-stage cascode output nodes generate two paths of output signals with similar amplitudes and opposite phases to the second-stage circuit based on an input signal of a first-stage input end, and generate an amplified first-stage output signal; the second-stage circuit comprises two second-stage input nodes, a second complementary cascode amplification structure and a second amplification output end; an amplified second-stage output signal is generated; two first stage cascode output nodes of the first stage circuit are cross-coupled to two second stage input nodes of the second stage circuit. The low-noise amplifier has the advantages of low power consumption, low noise, low cost, small area, high linearity and the like.

Description

Technical Field

[0001] The present disclosure relates to the technical field of radio frequency integrated circuits, and in particular to a broadband single-ended to differential low noise amplifier and a radio frequency receiver. Background Art

[0002] With the development of wireless communication, the role of RF receiving technology is becoming more and more important. In particular, broadband communication system is the development trend of wireless communication technology today, and it is also a hot research topic at home and abroad. A broadband receiver system can be applied to various communication standards and frequency bands, with the characteristics of low cost, configurability and high flexibility.

[0003] In the design of RF receivers, in order to suppress common-mode noise and improve the isolation between RF and local oscillator, fully differential orthogonal mixers, differential filters, and differential analog-to-digital converters are widely used. Fully differential mixers require differential RF inputs, but the RF signal received from the antenna is a single-ended signal, so a single-ended to differential low-noise amplifier is required to convert the single-ended signal into a differential signal. Low-noise amplifiers (LNAs) are widely used, and the performance of LNAs directly affects the quality of the communication system.

[0004] In order to realize the function of converting single-ended signal to differential signal, the input signal must be converted into two signals of the same phase and the opposite phase. In the prior art, some methods are used to realize the function of converting single-ended signal to differential signal.

[0005] For example, patent CN101807883A discloses a single-ended input differential output single-turn dual CMOS low noise amplifier (LNA), which can be used in ultra-wideband (UWB) RF front ends of 3.1-4.8GHz and 3.1-10.6GHz. It consists of three parts: input parasitic parameter equivalent stage, input stage, and load stage. The input parasitic parameter equivalent stage is composed of a series inductor and a parallel capacitor, the input stage is composed of a common-gate tube, an input inductor and a common-source tube, and the load stage is composed of a series resistor and a series inductor, thereby realizing the function of single-ended input differential output. However, although the circuit is suitable for broadband applications, the common-source amplifier and the common-gate amplifier each consume one current, and only a single-stage gain is achieved with two currents.

[0006] For another example, patent CN102647157A discloses a single-ended input differential output radio frequency low noise amplifier, including a main amplifier circuit I with a single-ended input; an amplifier II for realizing another reverse equal amplitude signal output; and an AC signal addition feedback circuit is used to further adjust the balance of the two output signals. However, the input matching method using the gate and source inductors increases the area of ​​the device, and the structure using inductors is not suitable for broadband applications.

[0007] For another example, a low-noise amplifier with an RF balun naturally has the characteristics of single-ended to differential conversion, but the balun has the defects of narrow operating frequency band, large area and high cost. Therefore, it is widely used in narrowband RF receivers and cannot be applied to RF broadband receivers. The active single-ended to differential circuit using an inductor-free solution has broadband characteristics. The single-transistor structure can achieve single-to-dual functions by carefully designing the load resistance of its source and drain. However, due to the use of gate input, in order to achieve broadband input matching, an additional 50 ohm input resistor is required to achieve broadband input matching, which deteriorates the noise coefficient. The source and drain of the single-transistor structure are differential outputs, and thus, the isolation is naturally poor.

[0008] In summary, the problem with the prior art is that it is difficult for a broadband single-ended to differential low noise amplifier to simultaneously achieve low power consumption, low noise, low cost, small area, and high linearity.

[0009] Therefore, the prior art still needs to be improved and enhanced. Utility Model Content

[0010] In order to solve at least one of the above problems and one or more of other potential problems, the present disclosure proposes a broadband single-ended to differential low-noise amplifier, which has the characteristics of low power consumption, low noise, low cost, small area, high linearity, etc.

[0011] In a first aspect of the present disclosure, a broadband single-ended to differential low-noise amplifier is provided, which comprises: a first-stage circuit and a second-stage circuit, wherein the first-stage circuit comprises a first-stage input terminal (VIN), two first-stage cascode output nodes, a first complementary cascode amplification structure and a first amplification output terminal (VOUTP); the first-stage input terminal (VIN) is configured to receive an input signal from a signal input terminal, and the amplitude of the input signal is greater than an overdrive voltage of a transistor; the two first-stage cascode output nodes generate two output signals with similar amplitudes and opposite phases to the second-stage circuit based on the input signal from the first-stage input terminal (VIN), and the first complementary cascode amplification structure converts the first-stage input signal into an output signal. The input signal of the first-stage input terminal (VIN) generates an amplified first-stage output signal and outputs it at the first amplified output terminal (VOUTP); the first complementary cascode amplification structure includes a first cascode structure composed of a first transistor (N0) and a second transistor (N1), and a first complementary structure composed of a third transistor (P0) and a fourth transistor (P1), wherein the first transistor (N0) and the second transistor (N1) are NMOS transistors, and the third transistor (P0) and the fourth transistor (P1) are PMOS transistors; wherein the input signal of the first-stage input terminal (VIN) includes an upper input signal and a lower input signal; the first cascode structure is connected to the first transistor (N0) through the first transistor (N1). 0) inputs the lower input signal through the gate of the first complementary structure; the upper input signal is input through the gate of the third transistor (P0); the second stage circuit includes two second stage input nodes, a second complementary cascode amplifier structure and a second amplifier output terminal (VOUTN); the two second stage input nodes are used to receive output signals from the two first stage cascode output nodes of the first stage circuit, and the second complementary cascode amplifier structure generates an amplified second stage output signal from the input signals of the two second stage input nodes and outputs it at the second amplifier output terminal (VOUTN); the second complementary cascode amplifier structure includes a fifth transistor (N2) and a sixth transistor (N3) composed of a second cascode structure, and a second complementary structure consisting of a seventh transistor (P2) and an eighth transistor (P3), wherein the fifth transistor (N2) and the sixth transistor (N3) are NMOS transistors, and the seventh transistor (P2) and the eighth transistor (P3) are PMOS transistors; a first-level upper cascode output node (VP1) of the two first-level cascode output nodes is arranged between the drain of the third transistor (P0) and the source of the fourth transistor (P1); and a first-level lower cascode output node (VN1) of the two first-level cascode output nodes is arranged between the drain of the first transistor (N0) and the source of the second transistor (N1);The second-stage upper input node of the two second-stage input nodes is connected to the first-stage lower cascode output node (VN1) of the two first-stage cascode output nodes, and the second-stage lower input node of the two second-stage input nodes is connected to the first-stage upper cascode output node (VP1) of the two first-stage cascode output nodes; wherein the two second-stage input nodes are used to receive output signals from the two first-stage cascode output nodes of the first-stage circuit, namely: the input of the second-stage upper input node comes from the output of the first-stage lower cascode output node (VN1), and the input of the second-stage lower input node comes from the output of the first-stage upper cascode output node (VP1); the first-stage lower cascode output node (VN1) is coupled to the gate of the seventh transistor (P2) of the second complementary structure through a fourth capacitor (C3); and the first-stage upper cascode output node (VP1) is coupled to the gate of the fifth transistor (N2) of the second cascode structure through a third capacitor (C2). ;

[0012] Furthermore, the first common-source common-gate structure is configured such that the drain of the first transistor (N0) is connected to the source of the second transistor (N1); and the first complementary structure is configured such that the drain of the third transistor (P0) is connected to the source of the fourth transistor (P1).

[0013] Furthermore, the second common-source common-gate structure is configured such that the drain of the fifth transistor (N2) is connected to the source of the sixth transistor (N3); and the second complementary structure is configured such that the drain of the seventh transistor (P2) is connected to the source of the eighth transistor (P3).

[0014] Further, the gate of the first transistor (N0) is respectively connected to the second end of the first capacitor (C0) and the second end of the first resistor (R0); the drain of the first transistor (N0) is respectively connected to the source of the second transistor (N1) and the first-stage lower cascode output node (VN1) of the two first-stage cascode output nodes; the source of the first transistor (N0) is connected to the ground terminal;

[0015] The gate of the second transistor (N1) is connected to the second voltage source (VB1); the drain of the second transistor (N1) is respectively connected to the second end of the second resistor (R1), the drain of the fourth transistor (P1), and the first amplified output end (VOUTP).

[0016] Further, the gate of the third transistor (P0) is respectively connected to the second end of the second capacitor (C1) and the first end of the second resistor (R1); the source of the third transistor (P0) is connected to the power supply voltage (VDD); the drain of the third transistor (P0) is respectively connected to the source of the fourth transistor (P1) and the first-level common-source common-gate output node (VP1) of the two first-level common-source common-gate output nodes; the gate of the fourth transistor (P1) is connected to the third voltage source (VB2); the first end of the first resistor (R0) is connected to the first voltage source (VB0); and the first-level input terminal (VIN) is respectively connected to the first end of the first capacitor (C0) and the first end of the second capacitor (C1).

[0017] Further, the gate of the fifth transistor (N2) is respectively connected to the second end of the third capacitor (C2) and the second end of the third resistor (R2); the drain of the fifth transistor (N2) is connected to the source of the sixth transistor (N3); the source of the fifth transistor (N2) is connected to the ground terminal; the gate of the sixth transistor (N3) is connected to the second voltage source (VB1); the drain of the sixth transistor (N3) is respectively connected to the second end of the fourth resistor (R3), the drain of the eighth transistor (P3), and the second amplified output terminal (VOUTN);

[0018] Further, the gate of the seventh transistor (P2) is respectively connected to the second end of the fourth capacitor (C3) and the first end of the fourth resistor (R3); the source of the seventh transistor (P2) is connected to the power supply voltage (VDD); the drain of the seventh transistor (P2) is connected to the source of the eighth transistor (P3); the gate of the eighth transistor (P3) is connected to the third voltage source (VB2); and the first end of the third resistor (R2) is connected to the first voltage source (VB0).

[0019] Furthermore, the first-stage upper common-source common-gate output node (VP1) among the two second-stage input nodes is connected to the first end of the third capacitor (C2), and the first-stage lower common-source common-gate output node (VN1) among the two second-stage input nodes is connected to the first end of the fourth capacitor (C3).

[0020] Furthermore, the above input signal is a radio frequency signal, and its frequency range is 0.01-11.5 GHz.

[0021] According to a second aspect of the present disclosure, a radio frequency receiver is provided, which includes: the low noise amplifier as described above.

[0022] Compared with the prior art, the present disclosure has the following beneficial effects:

[0023] (1) In the broadband single-ended to differential low noise amplifier embodiment, both the first stage circuit and the second stage circuit adopt a complementary common source and common gate amplifier structure, in particular, PMOS and NMOS are used as amplification transistors at the same time, the bias current is fully utilized, low power consumption and low noise are achieved, and the common source and common gate structure has high isolation;

[0024] (2) Further, in the broadband single-ended to differential low noise amplifier embodiment, the first stage circuit uses resistive negative feedback instead of inductors and other devices to achieve input matching, further saving the area occupied by the entire circuit;

[0025] (3) Further, in the broadband single-ended to differential low noise amplifier embodiment, the first stage circuit uses the common source and common gate node to achieve signal inversion, and transmits the inverted signal to the second stage input. Since the output impedance of the common source and common gate node is low, broadband single-ended to differential conversion is achieved;

[0026] (4) Further, in the broadband single-ended to differential low noise amplifier embodiment, the common source and common gate nodes of the PMOS and NMOS of the first stage and the gates of the PMOS and NMOS of the second stage adopt a cross-coupling structure, which improves the output 1dB compression point and achieves high linearity;

[0027] (5) Furthermore, in the exemplary embodiment, the cross-coupling method used is that PMOS and NMOS are cross-coupled with each other to drive the second-stage amplifier to achieve signal amplification, rather than using the same type of MOS tubes for cross-coupling, because the use of the same type of MOS tubes for cross-coupling can only achieve a negative resistance structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] The above and other features, advantages and aspects of the embodiments of the present disclosure will become more apparent with reference to the following detailed description in conjunction with the accompanying drawings, in which:

[0029] Figure 1 An input and output schematic diagram of a broadband single-ended to differential low noise amplifier according to an embodiment of the present disclosure is shown;

[0030] Figure 2 A schematic diagram of a preferred circuit structure of a broadband single-ended to differential low noise amplifier according to an embodiment of the present disclosure is shown;

[0031] Figure 3 Shows Figure 2 A diagram showing the noise figure and gain simulation results of a broadband single-ended to differential low noise amplifier according to an exemplary embodiment;

[0032] Figure 4 Shows Figure 2 A linearity simulation result diagram of a broadband single-ended to differential low noise amplifier according to an exemplary embodiment; and

[0033] In the various drawings, the same or corresponding reference numerals denote the same or corresponding parts. DETAILED DESCRIPTION

[0034] Embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. Although certain embodiments of the present disclosure are shown in the accompanying drawings, it should be understood that the present disclosure can be implemented in various forms and should not be construed as being limited to the embodiments described herein. On the contrary, these embodiments are provided to provide a more thorough and complete understanding of the present disclosure. It should be understood that the drawings and embodiments of the present disclosure are only for exemplary purposes and are not intended to limit the scope of protection of the present disclosure.

[0035] In the description of the embodiments of the present disclosure, the term "including" and similar terms should be understood as open inclusion, that is, "including but not limited to". The term "based on" should be understood as "based at least in part on". The term "one embodiment" or "the embodiment" should be understood as "at least one embodiment". The terms "first", "second", etc. may refer to different or the same objects. Other explicit and implicit definitions may also be included below.

[0036] In the design of RF receivers, in order to suppress common-mode noise and improve the isolation between RF and local oscillator, fully differential orthogonal mixers, differential filters, and differential analog-to-digital converters are generally used. Fully differential mixers require differential RF inputs, but the RF signal received from the antenna is a single-ended signal, so a single-ended to differential low-noise amplifier is required to convert the single-ended signal into a differential signal. For example, a low-noise amplifier with an RF balun naturally has the characteristics of single-ended to differential, but the balun has the defects of narrow operating frequency band and large area. Therefore, it is widely used in narrowband RF receivers and cannot be applied to RF broadband receivers. Therefore, an active single-ended to differential circuit using an inductor-free solution has the characteristics of broadband, so it was proposed, and it also has the characteristics of small area and simple structure. The simplest of them is a single-transistor structure, and a single-to-dual function can be achieved by carefully designing the load resistance of its source and drain. Due to the use of gate input, in order to achieve broadband input matching, an additional 50 ohm input resistor is required to achieve broadband input matching, which deteriorates the noise figure. The source and drain of the single transistor structure are differential outputs, so the natural isolation is poor. The common source and common gate differential pair structure has low power consumption and good isolation, but due to the low matching gain, the noise is relatively poor, and it is difficult to achieve high linearity. Most importantly, the source of the common gate requires a current source or a large inductor for RF choking, which limits the practicality of low-frequency communication, and greatly increases the cost while worsening the noise. Existing active broadband single-ended to differential low-noise amplifiers are difficult to achieve low power consumption, low noise, low cost, small area, and high linearity at the same time.

[0037] In order to solve at least one of the above problems, as well as one or more of other potential problems, an example embodiment of the present disclosure proposes a broadband single-ended to differential low noise amplifier, which utilizes a two-stage common-source broadband single-ended to differential low noise amplifier to solve the problem in the prior art that it is difficult to simultaneously achieve low power consumption, low noise, low cost, small area, and high linearity.

[0038] It should be noted that the low noise amplifier is generally a component of the RF receiver. In addition to the low noise amplifier, the RF receiver also includes a mixer, an intermediate frequency filter, a digital-to-analog converter, etc. Among them, the role of the low noise amplifier is to amplify the RF signal without significantly deteriorating the signal quality (signal-to-noise ratio). The mixer adopts a fully differential double-balanced structure, which has the advantages of high linearity, low noise, low RF, and low local oscillator leakage. Therefore, the low noise amplifier needs to convert the received single-ended RF signal into a differential RF signal and give it to the mixer.

[0039] The present disclosure is further described in detail below in conjunction with the accompanying drawings and various embodiments.

[0040] Figure 1 The input and output schematic diagram of the broadband single-ended to differential low noise amplifier according to the embodiment of the present disclosure is shown. In this exemplary embodiment, a broadband single-ended to differential low noise amplifier is provided, wherein VIN is a signal input terminal, VOUTP and VOUTN are output terminals, and further, a signal waveform schematic diagram is also shown in the figure, and the small signal at the input terminal is amplified to the output terminal after passing through the single-ended to differential low noise amplifier, thereby obtaining two large signals with a phase difference of 180°.

[0041] Figure 2A schematic diagram of a preferred circuit structure of a broadband single-ended to differential low noise amplifier according to an embodiment of the present disclosure is shown. In this exemplary embodiment, the broadband single-ended to differential low noise amplifier includes: a two-stage circuit structure of a first-stage circuit and a second-stage circuit, wherein the first-stage circuit includes a first-stage input terminal VIN, two first-stage cascode output nodes, a first complementary cascode amplification structure, and a first amplification output terminal VOUTP; wherein the first-stage input terminal VIN is used to receive the input signal of the signal input terminal, and the two first-stage cascode output nodes are the intersection points where the two circuits are connected, and based on the input signal of the first-stage input terminal VIN, two output signals with opposite phases (i.e., a phase difference of 180°) can be generated to the second-stage circuit; in particular, the first complementary cascode amplification structure included in the first-stage circuit generates an amplified first-stage output signal from the input signal of the first-stage input terminal VIN and outputs it at the first amplification output terminal VOUTP (it should be noted that, as shown in the figure, it is in phase with the first-stage input terminal VIN, i.e., the phase difference is 0°, and it is an amplified signal). Further, the second-stage circuit includes two second-stage input nodes, a second complementary cascode amplifier structure and a second amplifier output terminal VOUTN; wherein the two second-stage input nodes can receive output signals from two first-stage cascode output nodes of the first-stage circuit, and the second complementary cascode amplifier structure generates an amplified second-stage output signal from the input signals of the above two second-stage input nodes and outputs it at the second amplifier output terminal VOUTN (it should be noted that, as shown in the figure, it is opposite in phase to the first-stage input terminal VIN, that is, the phase difference is 180°, and it is an amplified signal). And, as shown in the figure, the two first-stage cascode output nodes of the first-stage circuit are cross-coupled to the two second-stage input nodes of the second-stage circuit.

[0042] Further, the exemplary embodiment is described in detail, wherein the first stage circuit includes, in addition to the above-mentioned first stage input terminal VIN, the first amplification output terminal VOUTP, and the two first stage cascode output nodes, a first transistor N0, a second transistor N1, a third transistor P0, and a fourth transistor P1 to form a first complementary cascode amplifier structure. Specifically, the first complementary cascode amplifier structure is composed of a first cascode structure and a first complementary structure; wherein the first cascode structure is composed of a first transistor N0 and a second transistor N1, and the first complementary structure is composed of a third transistor P0 and a fourth transistor P1. With respect to the first transistor N0, the gate of the first transistor N0 is connected to the lower path of the first stage input terminal VIN through the first capacitor C0, and is connected to the first voltage source VB0 through the first resistor R0; and the drain of the first transistor N0 is directly connected to the source of the second transistor N1, and is connected to the second stage upper input node of the second stage circuit through the first stage lower cascode output node VN1; and the source of the first transistor N0 is connected to the ground terminal. Regarding the second transistor N1, the gate of the second transistor N1 is directly connected to the second voltage source VB1; the drain of the second transistor N1 is connected to the gate of the third transistor P0 through the second resistor R1, connected to the upper path of the first-stage input terminal VIN through the second resistor R1 and the second capacitor C1, directly connected to the drain of the fourth transistor P1, and directly connected to the first amplified output terminal VOUTP. Regarding the third transistor P0, the gate of the third transistor P0 is connected to the upper path of the first-stage input terminal VIN through the second capacitor C1, connected to the drain of the second transistor N1 through the second resistor R1, connected to the drain of the fourth transistor P1 through the second resistor R1, and connected to the first amplified output terminal VOUTP through the second resistor R1; the source of the third transistor P0 is directly connected to the power supply voltage VDD; the drain of the third transistor P0 is directly connected to the source of the fourth transistor P1, and connected to the second-stage lower input node of the second-stage circuit through the first-stage upper common-source and common-gate output node VP1. Regarding the fourth transistor P1, the gate of the fourth transistor P1 is directly connected to the third voltage source VB2; the source of the fourth transistor P1 is directly connected to the drain of the third transistor P0, and is connected to the second-stage lower input node of the second-stage circuit through the first-stage upper common-source common-gate output node VP1. Therefore, the resistive negative feedback used in the first-stage circuit further saves the area occupied by the entire circuit because it does not require devices such as inductors to achieve input matching; in addition, the first-stage circuit uses the common-source common-gate node to achieve signal inversion, and the inverted signal is passed to the second-stage input. Since the output impedance of the common-source common-gate node is low, broadband single-ended to differential conversion is achieved.

[0043] Furthermore, in addition to the two second-stage input nodes and the second amplifier output terminal VOUTN, the second-stage circuit also includes: a fifth transistor N2, a sixth transistor N3, a seventh transistor P2, and an eighth transistor P3 to form a second complementary cascode amplifier structure. Specifically, the second complementary cascode amplifier structure is composed of a second cascode structure and a second complementary structure; wherein the second cascode structure is composed of a fifth transistor N2 and a sixth transistor N3, and the second complementary structure is composed of a seventh transistor P2 and an eighth transistor P3. With respect to the fifth transistor N2, the gate of the fifth transistor N2 is connected to the second-stage lower input node through the third capacitor C2 and to the first voltage source VB0 through the third resistor R2; the drain of the fifth transistor N2 is directly connected to the source of the sixth transistor N3; and the source of the fifth transistor N2 is directly connected to the ground terminal. Regarding the sixth transistor N3, the gate of the sixth transistor N3 is directly connected to the second voltage source VB1; the drain of the sixth transistor N3 is connected to the gate of the seventh transistor P2 through the fourth resistor R3, connected to the second-stage input node through the fourth resistor R3 and the fourth capacitor C3, directly connected to the source of the eighth transistor P3, and directly connected to the second amplified output terminal VOUTN; the source of the sixth transistor N3 is directly connected to the drain of the fifth transistor N2. Regarding the seventh transistor P2, the gate of the seventh transistor P2 is connected to the second-stage input node through the fourth capacitor C3, connected to the drain of the sixth transistor N3 through the fourth resistor R3, connected to the source of the eighth transistor P3 through the fourth resistor R3, and connected to the second amplified output terminal VOUTN through the fourth resistor R3; the drain of the seventh transistor P2 is directly connected to the power supply voltage VDD; and the source of the seventh transistor P2 is directly connected to the drain of the eighth transistor P3. Regarding the eighth transistor P3, the gate of the eighth transistor P3 is directly connected to the third voltage source VB2; the drain of the eighth transistor P3 is directly connected to the source of the seventh transistor P2; and the source of the eighth transistor P3 is connected to the gate of the seventh transistor P2 through the fourth resistor R3, connected to the input node on the second stage through the fourth resistor R3 and the fourth capacitor C3, directly connected to the drain of the sixth transistor N3, and directly connected to the second amplification output terminal VOUTN.

[0044] It should be noted that in the illustrated embodiment, the coupling mode of the first-stage circuit and the second-stage circuit is that the second-stage upper input node of the two second-stage input nodes is connected to the first-stage lower cascode output node VN1 of the two first-stage cascode output nodes, and the second-stage lower input node of the two second-stage input nodes is connected to the first-stage upper cascode output node VP1 of the two first-stage cascode output nodes; then the two first-stage cascode output nodes of the first-stage circuit are cross-coupled to the two second-stage input nodes of the second-stage circuit. That is, the first-stage lower cascode output node VN1 is connected to the first end (left end) of the fourth capacitor C3, and the first-stage upper cascode output node VP1 is connected to the first end (left end) of the third capacitor C2. This is to allow the second-stage transistors N2 and P2 to be driven by a higher peak value, and not driven by the clamped horizontal signal, and adopt a cross-coupling structure to cross-give the clamped first-stage lower cascode output node VN1 and the first-stage upper cascode output node VP1 signals to transistors P2 and N2, respectively. At this time, the transistors N2 and P2 can still be driven by higher peak and valley signals, thereby obtaining a larger output signal of the second amplified output terminal VOUTN, thereby improving the 1 dB compression point.

[0045] It should be understood that Figure 2 As shown, in the first stage circuit, the first transistor N0 and the second transistor N1 are NMOS transistors, and the third transistor P0 and the fourth transistor P1 are PMOS transistors. In the second stage circuit, the fifth transistor N2 and the sixth transistor N3 are NMOS transistors, and the seventh transistor P2 and the eighth transistor P3 are PMOS transistors. Therefore, both the first stage circuit and the second stage circuit adopt a complementary cascode amplifier structure, on this basis, in particular, PMOS and NMOS are used as amplifier transistors at the same time, and the bias current is fully utilized to achieve low power consumption and low noise, and the cascode structure has high isolation. Furthermore, the cascode nodes of the PMOS and NMOS of the first stage and the PMOS and NMOS gates of the second stage adopt a cross-coupling structure, which improves the output 1dB compression point and achieves high linearity.

[0046] It should be understood that Figure 2In the example implementation, the common gate nodes VN1 and VP1 of the complementary common source and common gate amplifier are close to the input signal in amplitude and opposite in phase (i.e., the phase difference is 180°), and the signals of VN1 and VP1 are transmitted to the common source input terminal (gate) of the second-stage complementary common source and common gate amplifier, and finally the differential outputs VOUTN and VOUTP are obtained. Compared with the traditional common source and common gate single-ended to differential structure, the ground inductor is omitted, which greatly saves the area. Compared with the traditional active single-ended to differential structure, each level of current participates in the amplification of the signal, and adopts the complementary structure of PMOS and NMOS, which improves the current utilization efficiency and realizes low noise in low power consumption mode. The first-stage feedback resistor provides an input impedance of 50ohm to achieve broadband input matching. The output impedance of the common gate nodes VN1 and VP1 is equal to the inverse of the transconductance of P1 and N1, which is generally less than 50ohm. Therefore, the RC time constant of the node is very small and the bandwidth is large, which can realize broadband single-ended to differential conversion.

[0047] It should be understood that in the prior art, a typical negative resistance pair cross-coupling structure (ie, this cross-coupling refers to the cross-coupling of two MOS transistors of the same type) implements a negative resistance structure. Figure 2 The cross-coupling in the exemplary embodiment is completely different from the typical negative resistance pair cross-coupling structure. Figure 2 The cross coupling in the exemplary embodiment is the mutual cross coupling of PMOS and NMOS, and the functions are completely different regardless of the implementation method or purpose; specifically, Figure 2 In the example embodiment, the first-stage circuit (front stage) adopts a complementary common source and common gate structure, and utilizes the characteristics of similar amplitude and opposite phase of the common source and common gate nodes to couple to the second-stage circuit (back stage) to realize the single-ended to differential function; the improved cross-coupling structure based on this can have better linearity.

[0048] Figure 3 Shows Figure 2 The noise figure and gain simulation results of the broadband single-ended to differential low noise amplifier of the exemplary embodiment are shown in FIG. Figure 2 The values ​​of the circuit components in the exemplary embodiment are as follows: the values ​​of capacitors C0, C1, C2, and C3 are 1.8 pF; the resistance values ​​of resistors R0 and R2 are 12 k ohms, the resistance value of resistor R1 is 900 ohms, and the resistance value of resistor R3 is 15 k ohms; the width-to-length ratio (W / L) of transistors N0 and N2 is 128 um / 30 nm, the width-to-length ratio (W / L) of transistors N1 and N3 is 96 um / 30 nm, the width-to-length ratio (W / L) of transistors P0 and P2 is 160 um / 30 nm, and the width-to-length ratio (W / L) of transistors P1 and P3 is 120 um / 30 nm; and thus: Figure 3 The simulation results show that Figure 2The circuit structure of the exemplary embodiment has demonstrated the advantages of broadband, low power consumption, and small area. In particular, it realizes broadband single-ended to differential conversion of 0.01 GHz to 11.5 GHz.

[0049] However, broadband low-noise amplifiers usually receive RF signals in a wide frequency band, and the signals vary in size. In other special cases, such as when the input is a large signal, the linearity of ordinary broadband single-ended to differential low-noise amplifiers faces challenges. Figure 3 As shown in the figure, when the amplitude of the input signal is greater than the overdrive voltage (Vov) of the CMOS transistor, the threshold voltage (Vth) of the transistor plays a clamping role, and the peaks and valleys of the signals at the common gate nodes VN1 and VP1 are respectively limited, that is, close to the horizontal line. Driven by a large signal, the PMOS is mainly driven by the signal valley to generate an amplified signal, and the NMOS is mainly driven by the signal peak to generate an amplified signal. Therefore, in the second-stage circuit, when transistors N2 and P2 are driven by a distorted signal (mainly a horizontal signal), the amplitude of the output signal at the second amplified output terminal VOUTN will be reduced and smaller than the output signal at the first amplified output terminal VOUTP, resulting in Figure 2 The 1 dB compression point (P1dB) of the low noise amplifier in the exemplary embodiment is lowered, thereby improving the P1dB of the structure by 2 dB.

[0050] Figure 4 Shows Figure 2 The simulation result diagram of the linearity of the broadband single-ended to differential low noise amplifier of the exemplary embodiment in FIG. Figure 2 The values ​​of the circuit components in the exemplary embodiment are as follows: the values ​​of capacitors C0, C1, C2, and C3 are 1.8 pF; the resistance values ​​of resistors R0 and R2 are 12 k ohms, the resistance value of resistor R1 is 900 ohms, and the resistance value of resistor R3 is 15 k ohms; the width-to-length ratio (W / L) of transistors N0 and N2 is 128 um / 30 nm, the width-to-length ratio (W / L) of transistors N1 and N3 is 96 um / 30 nm, the width-to-length ratio (W / L) of transistors P0 and P2 is 160 um / 30 nm, and the width-to-length ratio (W / L) of transistors P1 and P3 is 120 um / 30 nm; and thus: Figure 4 The simulation results are shown in Figure 2. Figure 4 The simulation results show that Figure 2 The saturated output power (indicated by the solid line) of the broadband single-ended to differential low noise amplifier circuit structure in the exemplary embodiment is higher than the saturated output power (indicated by the dotted line) of the general single-ended to differential low noise amplifier circuit structure. When the input power exceeds -11dBm, the linearity is still good, especially about 2dB higher at around -6dBm. Figure 2In the exemplary embodiment, the broadband single-ended to differential low noise amplifier can effectively improve the linearity of large signals. Figure 2 The simulation result data of the broadband single-ended to differential low noise amplifier circuit structure in the example embodiment shows that it simultaneously achieves low power consumption, low noise, low cost, small area and high linearity from the perspective of its power consumption, noise figure, area, isolation, 1dB compression point (P1dB), etc.

[0051] Table 1

[0052]

[0053] In Table 1, it should be understood that the broadband single-ended to differential low noise amplifier in the prior art generally has a power consumption greater than 3 mW, a bandwidth of about 0.1 to 1.2 GHz, a noise figure of about 3.2 dB, and an area greater than 0.021 mm 2 , isolation is about 44dBc, IP1dB / dBm (linearity) is about -8; or it cannot have both Figure 2 Example embodiments have the advantages of low power consumption, low noise, low cost, small area, and high linearity.

[0054] Furthermore, the present disclosure also provides a radio frequency receiver, which includes: the low noise amplifier in the above embodiment, and also includes a mixer, an intermediate frequency filter, a digital-to-analog converter, etc.

[0055] The embodiments of the present disclosure have been described above, and the above description is exemplary, not exhaustive, and is not limited to the disclosed embodiments. Many modifications and changes will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the described embodiments. The selection of terms used herein is intended to best explain the principles of the embodiments, practical applications, or technical improvements in the market, or to enable other persons of ordinary skill in the art to understand the embodiments disclosed herein.

[0056] The above description is only an optional embodiment of the present disclosure and is not intended to limit the present disclosure. For those skilled in the art, the present disclosure may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present disclosure shall be included in the protection scope of the present disclosure.

Claims

1. A broadband single-ended to differential low noise amplifier, characterized in that: include: The first and second circuits, The first-stage circuit includes a first-stage input terminal (VIN), two first-stage cascode output nodes, a first complementary cascode amplifier structure and a first amplifier output terminal (VOUTP); the first-stage input terminal (VIN) is configured to receive an input signal from a signal input terminal, and the amplitude of the input signal is greater than an overdrive voltage of the transistor; the two first-stage cascode output nodes generate two output signals with similar amplitudes and opposite phases to the second-stage circuit based on the input signal from the first-stage input terminal (VIN), and the first complementary cascode amplifier structure generates an amplified first-stage output signal from the input signal from the first-stage input terminal (VIN) and outputs it at the first amplifier output terminal (VOUTP); the first The complementary cascode amplifier structure comprises a first cascode structure composed of a first transistor (N0) and a second transistor (N1), and a first complementary structure composed of a third transistor (P0) and a fourth transistor (P1), wherein the first transistor (N0) and the second transistor (N1) are NMOS transistors, and the third transistor (P0) and the fourth transistor (P1) are PMOS transistors; wherein the input signal of the first-stage input terminal (VIN) comprises an upper input signal and a lower input signal; the first cascode structure inputs the lower input signal through the gate of the first transistor (N0); and the first complementary structure inputs the upper input signal through the gate of the third transistor (P0); The second-stage circuit includes two second-stage input nodes, a second complementary cascode amplifier structure and a second amplifier output terminal (VOUTN); the two second-stage input nodes are used to receive output signals from two first-stage cascode output nodes of the first-stage circuit, and the second complementary cascode amplifier structure generates an amplified second-stage output signal from the input signals of the two second-stage input nodes and outputs it at the second amplifier output terminal (VOUTN); the second complementary cascode amplifier structure includes a second cascode structure composed of a fifth transistor (N2) and a sixth transistor (N3), and a second complementary structure composed of a seventh transistor (P2) and an eighth transistor (P3), wherein the fifth transistor (N2) and the sixth transistor (N3) are NMOS transistors, and the seventh transistor (P2) and the eighth transistor (P3) are PMOS transistors; A first-stage upper cascode output node (VP1) of the two first-stage cascode output nodes is arranged between the drain of the third transistor (P0) and the source of the fourth transistor (P1); a first-stage lower cascode output node (VN1) of the two first-stage cascode output nodes is arranged between the drain of the first transistor (N0) and the source of the second transistor (N1); The second-stage upper input node of the two second-stage input nodes is connected to the first-stage lower cascode output node (VN1) of the two first-stage cascode output nodes, and the second-stage lower input node of the two second-stage input nodes is connected to the first-stage upper cascode output node (VP1) of the two first-stage cascode output nodes; wherein the two second-stage input nodes are used to receive output signals from the two first-stage cascode output nodes of the first-stage circuit, namely: the input of the second-stage upper input node comes from the output of the first-stage lower cascode output node (VN1), and the input of the second-stage lower input node comes from the output of the first-stage upper cascode output node (VP1); The first-stage lower common-source common-gate output node (VN1) is coupled to the gate of the seventh transistor (P2) of the second complementary structure through a fourth capacitor (C3); the first-stage upper common-source common-gate output node (VP1) is coupled to the gate of the fifth transistor (N2) of the second common-source common-gate structure through a third capacitor (C2).

2. The low noise amplifier according to claim 1, characterized in that: The first cascode structure is configured such that the drain of the first transistor (N0) is connected to the source of the second transistor (N1); the first complementary structure is configured such that the drain of the third transistor (P0) is connected to the source of the fourth transistor (P1).

3. The low noise amplifier according to claim 2, characterized in that: The second common-source common-gate structure is configured such that the drain of the fifth transistor (N2) is connected to the source of the sixth transistor (N3); and the second complementary structure is configured such that the drain of the seventh transistor (P2) is connected to the source of the eighth transistor (P3).

4. The low noise amplifier according to claim 1, characterized in that: The gate of the first transistor (N0) is respectively connected to the second end of the first capacitor (C0) and the second end of the first resistor (R0); the drain of the first transistor (N0) is respectively connected to the source of the second transistor (N1) and the first lower cascode output node (VN1) of the two first-stage cascode output nodes; the source of the first transistor (N0) is connected to the ground terminal; The gate of the second transistor (N1) is connected to a second voltage source (VB1); the drain of the second transistor (N1) is respectively connected to the second end of the second resistor (R1), the drain of the fourth transistor (P1), and the first amplified output end (VOUTP).

5. The low noise amplifier according to claim 4, characterized in that: The gate of the third transistor (P0) is respectively connected to the second end of the second capacitor (C1) and the first end of the second resistor (R1); the source of the third transistor (P0) is connected to the power supply voltage (VDD); the drain of the third transistor (P0) is respectively connected to the source of the fourth transistor (P1) and the first-stage cascode output node (VP1) of the two first-stage cascode output nodes; The gate of the fourth transistor (P1) is connected to a third voltage source (VB2); A first end of the first resistor (R0) is connected to a first voltage source (VB0); The first stage input terminal (VIN) is connected to the first end of the first capacitor (C0) and the first end of the second capacitor (C1) respectively.

6. The low noise amplifier according to claim 5, characterized in that: The gate of the fifth transistor (N2) is connected to the second end of the third capacitor (C2) and the second end of the third resistor (R2) respectively; the drain of the fifth transistor (N2) is connected to the source of the sixth transistor (N3); and the source of the fifth transistor (N2) is connected to the ground terminal; The gate of the sixth transistor (N3) is connected to the second voltage source (VB1); the drain of the sixth transistor (N3) is respectively connected to the second end of the fourth resistor (R3), the drain of the eighth transistor (P3), and the second amplified output end (VOUTN).

7. The low noise amplifier according to claim 6, characterized in that: The gate of the seventh transistor (P2) is connected to the second end of the fourth capacitor (C3) and the first end of the fourth resistor (R3) respectively; the source of the seventh transistor (P2) is connected to the power supply voltage (VDD); the drain of the seventh transistor (P2) is connected to the source of the eighth transistor (P3); The gate of the eighth transistor (P3) is connected to the third voltage source (VB2); A first end of the third resistor (R2) is connected to the first voltage source (VB0).

8. The low noise amplifier according to claim 7, characterized in that: The first-stage upper common-source common-gate output node (VP1) of the two second-stage input nodes is connected to the first end of the third capacitor (C2), and the first-stage lower common-source common-gate output node (VN1) of the two second-stage input nodes is connected to the first end of the fourth capacitor (C3).

9. The low noise amplifier according to any one of claims 1 to 8, characterized in that: The input signal is a radio frequency signal, and its frequency range is 0.01-11.5 GHz.

10. A radio frequency receiver, characterized in that: include: A low noise amplifier as claimed in any one of claims 1 to 9.

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