Silicon carbide-based electronic device

Abstract

The utility model relates to silicon carbide-based electronic devices. A device includes: a first polycrystalline SiC substrate including a first surface and a second surface opposite the first surface, the first polycrystalline SiC substrate having a first cubic structure; and a second polycrystalline SiC substrate coupled to the second surface of the first polycrystalline SiC substrate, the second polycrystalline SiC substrate having a second cubic structure.

Description

Technical Field

[0001] The present disclosure relates to a polycrystalline silicon carbide (SiC) substrate. Background Art

[0002] The semiconductor industry has shown considerable interest in silicon carbide (SiC), particularly for use in the manufacture of electronic devices or components (eg, diodes, transistors, or other similar power applications).

[0003] The development and manufacture of electronic devices based on silicon carbide are limited by factors such as the electrical and mechanical properties of the formed silicon carbide wafers. At least one problem is the amount of stress or strain that the wafer is subjected to when the wafer is manufactured. The stress and strain are the result of the thermal mismatch between the carrier and the material forming the wafer when the wafer is formed on the carrier. The stress and strain may cause the propagation of mechanical defects, such as cracks, warping, cracking, breakage or other similar or similar mechanical defects, which may cause the manufactured wafer to exceed the selected tolerance, so that the wafer manufactured beyond the tolerance is discarded, which increases the manufacturing and waste costs. In addition, after the wafer is formed on the carrier, when further processing and refinement steps (e.g., polishing, thinning, heating, etc.) are performed to manufacture semiconductors and electronic devices, the thermal mismatch between the wafer and the carrier may cause mechanical defects to propagate in the carrier, the wafer, or both, due to the temperature changes (i.e., temperature increase or temperature decrease) to which the wafer, the carrier, or both are exposed during these additional processing and refinement steps. Utility Model Content

[0004] One aspect of the present disclosure provides a silicon carbide-based electronic device, including: a first polycrystalline SiC substrate including a first surface and a second surface opposite to the first surface, the first polycrystalline SiC substrate having a first cubic structure; and a second polycrystalline SiC substrate coupled to the second surface of the first polycrystalline SiC substrate, the second polycrystalline SiC substrate having a second cubic structure.

[0005] In some embodiments of the present disclosure, the first polycrystalline SiC substrate has a first sidewall; and the second polycrystalline SiC substrate has a second sidewall that is substantially coplanar with the first sidewall.

[0006] In some embodiments of the present disclosure, the first polycrystalline SiC substrate has a first coefficient of thermal expansion; the second polycrystalline SiC substrate has a second coefficient of thermal expansion; and the first coefficient of thermal expansion is substantially equal to the second coefficient of thermal expansion.

[0007] In some embodiments of the present disclosure, the second polycrystalline SiC substrate includes a third surface facing away from the first surface.

[0008] In some embodiments of the present disclosure, the second polycrystalline SiC substrate includes a third surface facing away from the first polycrystalline SiC substrate, and the third surface of the second polycrystalline SiC substrate has a surface area less than or equal to 5 angstroms. Roughness. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Figure 1 is a flow chart of an embodiment of a method of forming or manufacturing a carrier polycrystalline SiC substrate and a method of forming or manufacturing a polycrystalline SiC substrate using the carrier polycrystalline SiC substrate;

[0010] Figure 2A-2C is a side view of various intermediate structures during an embodiment of a method of forming a carrier polycrystalline SiC substrate and a method of forming a polycrystalline SiC substrate using the carrier polycrystalline SiC substrate;

[0011] Figure 3 is a perspective side view of an embodiment of a carrier polycrystalline SiC substrate for forming a polycrystalline SiC substrate;

[0012] Figure 4 Yes Figure 3 A perspective side view of an embodiment of a polycrystalline SiC substrate on an embodiment of a carrier polycrystalline SiC substrate shown in FIG. 1 ; and

[0013] Figure 5 is a perspective side view of an embodiment of a polycrystalline SiC substrate. DETAILED DESCRIPTION

[0014] At least one embodiment of the formation or manufacturing method of the present disclosure includes forming a first polycrystalline silicon carbide (SiC) substrate by sintering a powder semiconductor material (e.g., a mixture of powdered silicon (Si) and powdered carbon (C), or powdered SiC) using a sintering process. After forming the first polycrystalline SiC substrate using a sintering process, a second polycrystalline SiC substrate is formed using the first polycrystalline silicon carbide SiC substrate by a chemical vapor deposition (CVD) process. The second polycrystalline SiC substrate is formed on the surface of the first polycrystalline SiC substrate by depositing SiC on the surface of the first polycrystalline SiC substrate using a CVD process. Since the first polycrystalline SiC substrate and the second polycrystalline SiC substrate are made of the same or similar semiconductor material (e.g., SiC), the first coefficient of thermal expansion (CTE) of the first polycrystalline SiC substrate is the same or similar to the second CTE of the second polycrystalline SiC substrate. These same or similar first CTE and second CTE prevent or reduce the possibility of mechanical defects (e.g., cracks, warpage, etc.) present in the second polycrystalline SiC substrate when the second polycrystalline SiC substrate is manufactured using the first polycrystalline SiC substrate.

[0015] During the CVD process of forming the second polycrystalline SiC substrate, the first polycrystalline SiC substrate is exposed to heat, which causes the first polycrystalline SiC substrate to thermally expand (i.e., increase in volume). When the second polycrystalline SiC substrate is formed on the first polycrystalline SiC substrate, the SiC deposited on the surface of the first polycrystalline SiC substrate is exposed to heat, which causes the SiC deposited on the surface of the first polycrystalline SiC substrate to thermally expand. Since the first polycrystalline SiC substrate is made of SiC and the second polycrystalline SiC substrate is formed of SiC, the first polycrystalline SiC substrate and the SiC used to form the polycrystalline SiC substrate have the same or similar coefficient of thermal expansion (CTE). Since the expansion in both the first polycrystalline SiC substrate and the SiC used to form the second polycrystalline SiC substrate when exposed to heat has the same or similar thermal expansion, the stress and strain in the first polycrystalline SiC substrate and the SiC used to form the second polycrystalline SiC substrate are relieved, thereby preventing or reducing the possibility of mechanical defects propagating within the second polycrystalline SiC substrate when the second polycrystalline SiC substrate is formed.

[0016] The same or similar CTE causes the first polycrystalline SiC substrate and the SiC used to form the second polycrystalline SiC substrate to have the same or similar thermal expansion when exposed to heat (i.e., the temperature increases) or the same or similar thermal contraction when cooled (i.e., the temperature decreases). When the first polycrystalline SiC substrate is used to form the second polycrystalline SiC substrate, the similarity between the thermal expansion and contraction of the first polycrystalline SiC substrate and the second polycrystalline SiC substrate prevents or reduces the possibility of mechanical defects propagating within the second polycrystalline SiC substrate. For example, if the first polycrystalline SiC substrate is replaced with a graphite or graphene substrate on which the second polycrystalline SiC substrate is formed, the graphite or graphene substrate will have a third CTE that is different from the second CTE of the second polycrystalline SiC substrate. This difference in the second CTE and the third CTE will result in a more significant difference between the thermal expansion and contraction of the graphite or graphene substrate and the second polycrystalline SiC substrate relative to when the first polycrystalline SiC substrate is used to form the second polycrystalline SiC substrate. This greater difference in thermal expansion between the graphite or graphene substrate and the second polycrystalline SiC substrate results in an increased likelihood of mechanical defects propagating within the second polycrystalline SiC substrate when the second polycrystalline SiC substrate is formed, due to increased stress or strain caused by these differences in thermal expansion and contraction between the graphite or graphene substrate and the second polycrystalline SiC substrate. In view of this discussion, when utilizing at least one embodiment of the formation or manufacturing method of the present disclosure, forming a second polycrystalline SiC substrate having a second CTE on a first polycrystalline SiC substrate having a first CTE (which may be the same as or similar to the second CTE) prevents or reduces the likelihood of mechanical defects (e.g., cracks, warpage, etc.) present in the manufactured second polycrystalline SiC substrate propagating.

[0017] Once the second polycrystalline SiC substrate is formed on the surface of the first polycrystalline SiC substrate, the first polycrystalline SiC substrate and the second polycrystalline SiC substrate are allowed to cool, thereby causing the first polycrystalline SiC substrate and the second polycrystalline SiC substrate to thermally shrink (i.e., reduce in volume). Since the first polycrystalline SiC substrate and the second polycrystalline SiC substrate have the same or similar first CTE and second CTE to each other, when the first polycrystalline SiC substrate and the second polycrystalline SiC substrate are cooled, the first polycrystalline SiC substrate and the second polycrystalline SiC substrate thermally shrink by the same or similar amount. The similarity between the thermal shrinkage of the first polycrystalline SiC substrate and the second polycrystalline SiC substrate prevents or reduces the possibility of mechanical defects propagating within the second polycrystalline SiC substrate when the second polycrystalline SiC substrate is formed. For example, if the first polycrystalline SiC substrate is replaced with a graphite or graphene substrate on which the second polycrystalline SiC substrate is formed, the graphite or graphene substrate will have a third CTE that is different from the second CTE of the second polycrystalline SiC substrate. This difference in the second CTE and the third CTE results in a more significant difference between the thermal contraction of the graphite or graphene substrate and the second polycrystalline SiC substrate relative to when the second polycrystalline SiC substrate is formed using the first polycrystalline SiC substrate. This difference in thermal contraction between the graphite or graphene substrate and the second polycrystalline SiC substrate results in an increased likelihood of mechanical defects propagating within the second polycrystalline SiC substrate when the second polycrystalline SiC substrate is formed, because stress or strain increases due to the difference in thermal contraction between the graphite or graphene substrate and the second polycrystalline SiC substrate. In view of this discussion, when utilizing at least one embodiment of the manufacturing method of the present disclosure, forming a second polycrystalline SiC substrate having a second CTE on a first polycrystalline SiC substrate having a first CTE (which may be the same as or similar to the second CTE) prevents or reduces the likelihood of mechanical defects (e.g., cracks, warpage, etc.) present in the manufactured second polycrystalline SiC substrate propagating.

[0018] At least one embodiment of the method of the present disclosure is summarized as follows. The method includes forming a carrier polycrystalline silicon carbide (SiC) substrate having a surface. Forming the carrier polycrystalline SiC substrate includes sintering one or more powder materials to form a carrier polycrystalline SiC substrate, and forming a polycrystalline SiC substrate on the surface of the carrier polycrystalline SiC substrate, and forming the polycrystalline SiC substrate includes depositing SiC onto the surface of the carrier polycrystalline SiC substrate using a chemical vapor deposition (CVD) process.

[0019] At least one embodiment of the device disclosed herein is summarized as follows: The device includes a first polycrystalline SiC substrate and a second polycrystalline SiC substrate, the first polycrystalline SiC substrate including a first surface and a second surface opposite to the first surface, the second polycrystalline SiC substrate coupled to the second surface of the first polycrystalline SiC substrate.

[0020] At least one embodiment of the method of the present disclosure is summarized as follows. The method includes forming a polycrystalline SiC substrate having a first thermal expansion coefficient on a first surface of a polycrystalline SiC carrier substrate having a second thermal expansion coefficient substantially equal to the first thermal expansion coefficient, the forming of the polycrystalline SiC substrate including forming a second surface of the polycrystalline SiC substrate facing away from the carrier polycrystalline SiC substrate. After forming the polycrystalline SiC substrate, the polycrystalline SiC substrate is removed from the carrier polycrystalline SiC substrate.

[0021] Figure 1 1 is a flow chart 100 of an embodiment of a method of manufacturing a polycrystalline SiC substrate 114 using a carrier polycrystalline SiC substrate 108, which may have been formed using a sintering process, to manufacture the polycrystalline SiC substrate 114. Figure 1 As shown in the flowchart 100 in FIG. 1 , the flowchart 100 includes a first step 102 (i.e., an upper step based on the orientation of the flowchart), a second step 104 (i.e., an intermediate step based on the orientation of the flowchart), and a third step 106 (i.e., a lower step based on the orientation of the flowchart).

[0022] In a first step 102, a carrier polycrystalline SiC substrate 108 is formed, which may be formed using a sintering process. The carrier polycrystalline SiC substrate 108 may be a support substrate, a carrier substrate, a support wafer, a carrier wafer, a dummy wafer, or some other similar type of wafer or substrate. In at least one embodiment, the carrier polycrystalline SiC substrate 108 is formed by a sintering process. Forming the carrier polycrystalline SiC substrate 108 using the sintering process may be cheaper than forming the carrier polycrystalline SiC substrate 108 using another method, such as, for example, a chemical vapor deposition (CVD) process or some other known substrate manufacturing technology. For example, when the carrier polycrystalline SiC substrate 108 is formed using the sintering process, a mixture of powdered silicon (Si) and powdered carbon (C) forming the carrier polycrystalline SiC substrate 108 is sintered together using a sintering furnace, or powdered silicon carbide (SiC) forming the carrier polycrystalline SiC substrate 108 is sintered together using a sintering furnace. In other words, the carrier polycrystalline SiC substrate 108 may be formed using a sintering process known in the silicon carbide (SiC) substrate manufacturing industry. Figure 2A , Figure 2B , Figure 3 and Figure 4 This will be discussed in detail later in this article.

[0023] After forming the carrier polycrystalline SiC substrate 108 in the first step, the carrier polycrystalline SiC substrate 108 is cooled and removed from the sintering furnace. After the carrier polycrystalline SiC substrate 108 has cooled and has been removed from the sintering furnace, the carrier polycrystalline SiC substrate 108 is positioned within the chamber of a chemical vapor deposition (CVD) tool.

[0024] In an alternative embodiment, the carrier polycrystalline SiC substrate 108 may be formed from a sintered body previously formed using the above-described sintering process. After forming the sintered body, the carrier polycrystalline SiC substrate 108 may be formed by refining all or a portion of the sintered body to form the carrier polycrystalline SiC substrate 108. For example, in some embodiments, after forming the sintered body, a portion of the sintered body may be split or cut away from the sintered body, and the portion of the sintered body may be polished, ground, or subjected to further processing and refining steps or a combination of processing and refining steps to process and refine it into the carrier polycrystalline SiC substrate 108. For example, in some alternative embodiments, after forming the sintered body, the sintered body may be polished, ground, or subjected to further processing and refining steps or a combination of processing and refining steps to process and refine it into the carrier polycrystalline SiC substrate 108.

[0025] The carrier polycrystalline SiC substrate 108 has a cubic structure. For example, the carrier polycrystalline SiC substrate 108 has a 3C-SiC structure. The carrier polycrystalline SiC substrate 108 may have a resistivity less than or equal to 500 mohm-cm, or preferably within a range of 25 to 250 mohm-cm or equal to the upper and lower ends of the range.

[0026] After positioning the carrier polycrystalline SiC substrate 108 within the chamber of the CVD tool, the following steps are performed: Figure 1 In the second step 104 of the flowchart 100 shown in FIG. 1 , a polycrystalline SiC substrate 114 is formed on the carrier polycrystalline SiC substrate 108. Figure 2A As shown in FIG. 1 , a CVD process is performed so that SiC is formed on a surface 110 of a carrier polycrystalline SiC substrate 108. The surface 110 of the carrier polycrystalline SiC substrate 108 is a sintered surface. The surface 110 of the carrier polycrystalline SiC substrate 108 is based on Figure 2A The orientation of the carrier polycrystalline SiC substrate 108 shown in FIG.

[0027] In some embodiments, the surface 110 of the carrier polycrystalline SiC substrate 108 may be polished before the polycrystalline SiC substrate 114 is formed on the surface 110 of the carrier polycrystalline SiC substrate 108. In some alternative embodiments, the polycrystalline SiC substrate 114 is formed on the surface 110 of the carrier polycrystalline SiC substrate 108 without polishing the surface 110 of the carrier polycrystalline SiC substrate 108, so that the surface 110 of the carrier polycrystalline SiC substrate 108 may be rough compared to when the surface 110 is polished. In still other alternative embodiments, when the carrier polycrystalline SiC substrate 108 is formed by cutting away a portion of a sintered body (see the previous discussion herein), the surface 110 of the carrier polycrystalline SiC substrate 108 may be a surface formed by cutting away the portion from the sintered body to form the carrier polycrystalline SiC substrate 108, so that the surface 110 of the carrier polycrystalline SiC substrate 108 is a cut surface. In other words, surface 110 of carrier polycrystalline SiC substrate 108 may be a polished surface, a roughened surface compared to when surface 110 is polished, a sintered surface, a cut surface, or some other type of corresponding surface on which polycrystalline SiC substrate 114 may be formed.

[0028] The polycrystalline SiC substrate 114 may have a resistivity less than or equal to 10 mohm-cm, or preferably within a range of 1 to 5 mohm-cm or equal to the upper and lower ends of the range.

[0029] like Figure 2A As shown in , the formation or deposition of SiC on the surface 110 of the carrier polycrystalline SiC substrate 108 to form a polycrystalline SiC substrate 114 on the carrier polycrystalline SiC substrate 108 is represented by corresponding arrows 112. For example, in at least one embodiment of this CVD process for forming the polycrystalline SiC substrate 114 on the carrier polycrystalline SiC substrate 108, silicon carbide (SiC) or silicon (Si) and carbon (C) particles or atoms are introduced onto the surface 110 of the carrier polycrystalline SiC substrate 108. Over time, these atoms or particles accumulate on the surface 110 of the carrier polycrystalline SiC substrate 108, thereby forming the polycrystalline SiC substrate 110.

[0030] This CVD process for forming the polycrystalline SiC substrate 114 on the carrier polycrystalline SiC substrate 108 exposes the carrier polycrystalline SiC substrate 108 and the SiC or Si and C particles and atoms to heat, causing the carrier polycrystalline SiC substrate 108 and the SiC or Si and C particles to expand during the manufacture of the polycrystalline SiC substrate 114 on the carrier polycrystalline SiC substrate 108. However, since the carrier polycrystalline SiC substrate 108 and the polycrystalline SiC substrate 114 formed on the surface 110 of the carrier polycrystalline SiC substrate 108 are made of silicon carbide material, the first coefficient of thermal expansion (CTE) of the carrier polycrystalline SiC substrate 108 is substantially equal to or similar to the second CTE of the polycrystalline SiC substrate 114 formed on the surface 110 of the carrier polycrystalline SiC substrate 108. Since the first CTE and the second CTE are substantially equal to one another, the carrier polycrystalline SiC substrate 108 and the polycrystalline SiC substrate 114 formed on the surface of the carrier polycrystalline SiC substrate 108 expand by substantially the same or similar amounts to one another when exposed to heat during this CVD process.

[0031] When the polycrystalline SiC substrate 114 is formed on the carrier polycrystalline SiC substrate 108, such same or similar expansion between the carrier polycrystalline SiC substrate 108 and the polycrystalline SiC substrate 114 prevents or reduces the likelihood of mechanical defects propagating within the polycrystalline SiC substrate 114 when the polycrystalline SiC substrate 114 is formed. Because the carrier polycrystalline SiC substrate 108 and the polycrystalline SiC substrate 114 expand by substantially the same or similar amounts, the stresses and strains generated due to any minor thermal expansion differences between the carrier polycrystalline SiC substrate 108 and the polycrystalline SiC substrate 114 are relatively low. For example and in the alternative, if a first substrate (e.g., a graphite or graphene substrate) has a first CTE that is significantly different from a second CTE of a second substrate (e.g., a silicon carbide (SiC) substrate) formed on the first substrate, then the difference in thermal expansion between the first substrate and the second substrate, which may be referred to as a thermal mismatch, causes a significant amount of stress and strain to occur within the second substrate when the second substrate is formed. When forming the second substrate, such increased or high stress and strain that occurs within the second substrate due to the difference in thermal expansion in the first substrate and the second substrate increases the likelihood that mechanical defects (e.g., cracks, warpage, etc.) will propagate within the second substrate when forming the second substrate. In view of this discussion, since the carrier polycrystalline SiC substrate 108 and the polycrystalline SiC substrate 114 formed on the carrier polycrystalline SiC substrate 108 have substantially equal CTEs to each other, when forming the polycrystalline SiC substrate 114, the thermal expansion of the carrier polycrystalline SiC substrate 108 and the polycrystalline SiC substrate 114 will be substantially the same, thereby preventing or reducing the likelihood of mechanical defects propagating within the polycrystalline SiC substrate 114. When forming the polycrystalline SiC substrate 114, preventing or reducing the likelihood of mechanical defects propagating within the polycrystalline SiC substrate 114 reduces waste costs and manufacturing costs because fewer defective polycrystalline SiC substrates 114 formed outside of selected tolerances are manufactured, which in turn increases the yield when manufacturing the polycrystalline SiC substrates 114.

[0032] The results of this CVD process can be found in Figure 2B 1 , where a polycrystalline SiC substrate 114 is present on a surface 110 of a carrier polycrystalline SiC substrate 108. In at least one embodiment, a first thickness T1 of the carrier polycrystalline SiC substrate 108 may be substantially equal to or the same as a second thickness T2 of the polycrystalline SiC substrate 114. In some alternative embodiments, the first thickness T1 of the carrier polycrystalline SiC substrate 108 may be greater than the second thickness T2 of the polycrystalline SiC substrate 114, such that the polycrystalline SiC substrate 114 is thinner than the carrier polycrystalline SiC substrate 108.

[0033] The first thickness T1 may be in the range of 200 microns (μm) to 1500 microns (μm), or may be equal to the upper and lower ends of the range. In some embodiments, the second thickness T2 may be in the range of 80 microns to 180 microns, or may be equal to the upper and lower ends of the range. In some embodiments, the second thickness T2 may be in the range of 120 microns to 180 microns, or may be equal to the upper and lower ends of the range. The second thickness T2 may be less than or equal to 300 microns. However, it is readily appreciated that, depending on the purpose and application for which the polycrystalline SiC substrate 114 will be utilized, the process may be adapted to form a polycrystalline SiC substrate 114 having different varying thicknesses.

[0034] like Figure 2BAs shown in , after forming the polycrystalline SiC substrate 114 on the surface 110 of the carrier polycrystalline SiC substrate 108, the polycrystalline SiC substrate 114 and the carrier polycrystalline SiC substrate 108 are allowed to cool after the CVD process is completed. Since the first CTE of the carrier polycrystalline SiC substrate 108 and the second CTE of the polycrystalline SiC substrate 114 are substantially the same or equal to each other, the carrier polycrystalline SiC substrate 108 and the polycrystalline SiC substrate 114 thermally shrink by substantially the same or equal amounts. Since the carrier polycrystalline SiC substrate 108 and the polycrystalline SiC substrate 114 shrink by substantially the same or similar amounts, the stress and strain that occur due to any minor thermal shrinkage differences between the carrier polycrystalline SiC substrate 108 and the polycrystalline SiC substrate 114 are relatively low. For example and in the alternative, if a first substrate (e.g., a graphite or graphene substrate) has a first CTE that is significantly different from a second CTE of a second substrate (e.g., a silicon carbide (SiC) substrate) formed on the first substrate, then the difference in thermal contraction between the first substrate and the second substrate, which may be referred to as a thermal mismatch, causes a large amount of stress and strain to occur within the second substrate when the second substrate is formed. When the first and second substrates are cooled, such increased or high stress and strain that occurs within the second substrate due to the difference in thermal contraction in the first and second substrates increases the likelihood that mechanical defects (e.g., cracks, warpage, etc.) will propagate within the second substrate when the first and second substrates are cooled. In view of this discussion, since the carrier polycrystalline SiC substrate 108 and the polycrystalline SiC substrate 114 formed on the carrier polycrystalline SiC substrate 108 have substantially equal CTEs to each other, the thermal contraction of the carrier polycrystalline SiC substrate 108 and the polycrystalline SiC substrate 114 will be substantially the same, thereby preventing or reducing the likelihood that mechanical defects will propagate within the polycrystalline SiC substrate 114 when the polycrystalline SiC substrate 114 and the carrier polycrystalline SiC substrate 108 are cooled. When forming the polycrystalline SiC substrate 114 , preventing or reducing the likelihood of mechanical defects propagating within the polycrystalline SiC substrate 114 reduces waste costs and manufacturing costs because fewer defective polycrystalline SiC substrates 114 formed outside of selected tolerances are manufactured, which in turn increases the yield when manufacturing the polycrystalline SiC substrate 114 .

[0035] The polycrystalline SiC substrate 114 is formed to have a cubic structure that is the same as or similar to the cubic structure of the carrier polycrystalline SiC substrate 108 .

[0036] After the second step of forming the polycrystalline SiC substrate 114 on the surface 110 of the carrier polycrystalline SiC substrate 108 using a CVD process or technique, Figure 1In the third step of the flowchart 100 shown in FIG. 1 , the polycrystalline SiC substrate 114 is removed from the carrier polycrystalline SiC substrate 108. For example, the polycrystalline SiC substrate 108 may be removed from the carrier polycrystalline SiC substrate 108 by removing (e.g., grinding away) the carrier polycrystalline SiC substrate 108 to expose the surface 116 of the polycrystalline SiC substrate 114 on the surface 110 of the carrier polycrystalline SiC substrate 108 on which the polycrystalline SiC substrate 114 was previously formed. The result of this removal step may be Figure 2C , where the polycrystalline SiC substrate 114 remains and has been removed from the carrier polycrystalline SiC substrate 108. In other words, Figure 2C is a side view of the polycrystalline SiC substrate 114 after being removed from the carrier polycrystalline SiC substrate 108. In some alternative embodiments of the method of forming or manufacturing the polycrystalline SiC substrate 114, the polycrystalline SiC substrate 114 may be removed from the carrier polycrystalline SiC substrate 108 by another technique, such as, for example, a segmentation technique, a dicing technique, or some other type of technique for removing the polycrystalline SiC substrate 114 from the carrier polycrystalline SiC substrate 108.

[0037] In some embodiments, the diameter of the polycrystalline SiC substrate 114 is in the range of 150 mm to 300 mm, or the diameter may be equal to the upper and lower ends of the range. In some embodiments, the diameter may be substantially equal to 200 mm.

[0038] The polycrystalline SiC substrate 114 has a cubic structure. For example, in at least one embodiment, the polycrystalline SiC substrate 114 is composed of 90% or more 3C-SiC, or in a preferred embodiment, 95% or more 3C-SiC. The remainder of the polycrystalline SiC substrate, if present or present, is composed of polytypes such as, for example, 4H-SiC, 6H-SiC, and 15R-SiC, and there is no polytype greater than a unit cell greater than 15.

[0039] In an alternative embodiment of the method of forming or manufacturing the polycrystalline SiC substrate 114 , the polycrystalline SiC substrate 114 may remain coupled to the carrier polycrystalline SiC substrate 108 rather than being separated from the carrier polycrystalline SiC substrate 108 .

[0040] In some embodiments, a surface 118 of the polycrystalline SiC substrate 114 facing away from the carrier polycrystalline SiC substrate 108 may be polished by chemical mechanical polishing technology so that the surface 118 of the polycrystalline SiC substrate 114 facing away from the carrier polycrystalline SiC substrate 108 has a surface thickness less than or equal to 20 angstroms. In some embodiments, a surface 118 of the polycrystalline SiC substrate 114 facing away from the carrier polycrystalline SiC substrate 108 may be polished to have a roughness of less than or equal to 5 angstroms. In some embodiments, an opposing surface 116 of the polycrystalline SiC substrate 114 that is opposite to a surface 118 of the polycrystalline SiC substrate 114 that faces away from the carrier polycrystalline SiC substrate 108 may be polished to have a roughness of less than or equal to 20 angstroms. In some embodiments, the opposite surface 116 of the polycrystalline SiC substrate 108 may be polished to have a roughness of less than or equal to 5 angstroms. Roughness.

[0041] The polycrystalline SiC substrate 114 has a second thickness T2 extending from the opposite surface 116 of the polycrystalline SiC substrate 114 to the surface 118 of the polycrystalline SiC substrate 114. In some embodiments, the second thickness T2 of the polycrystalline SiC substrate 114 is less than or equal to 150 micrometers (μm). In some embodiments, the second thickness T2 may be in the range of 50 micrometers (μm) to 150 micrometers (μm), or may be equal to the upper and lower ends of the range (i.e., equal to 50 micrometers (μm) or equal to 150 micrometers (μm)). In some embodiments, the second thickness T2 may be in the range of 100 micrometers (μm) to 150 micrometers (μm), or may be equal to the upper and lower ends of the range (i.e., equal to 100 micrometers (μm) or equal to 150 micrometers (μm)). In some embodiments, the second thickness T2 of the polycrystalline SiC substrate 114 may be equal to 150 micrometers (μm).

[0042] In some embodiments, polycrystalline SiC substrate 114 is formed to have a greater density than carrier polycrystalline SiC substrate 108. In some embodiments, polycrystalline SiC substrate 114 may have the same or similar density as a single crystal SiC substrate that may subsequently be formed on polycrystalline SiC substrate 114.

[0043] In some embodiments, the opposite surface 116 of the polycrystalline SiC substrate 114 that was previously coupled to the surface 110 of the carrier polycrystalline SiC substrate 108 may be polished before the carrier polycrystalline SiC substrate 108 is removed from the polycrystalline SiC substrate 114. For example, when the opposite surface 116 of the polycrystalline SiC substrate 114 that was previously coupled to the carrier polycrystalline SiC substrate 108 is polished, the opposite surface 116 of the polycrystalline SiC substrate 114 that was previously coupled to the carrier polycrystalline SiC substrate 108 may have a relative thickness of less than or equal to 20 angstroms. In some embodiments, the opposing surface 116 of the polycrystalline SiC substrate 114 previously coupled to the carrier polycrystalline SiC substrate 108 may be polished to have a roughness of less than or equal to 5 angstroms. Roughness.

[0044] After forming the polycrystalline SiC substrate 114, additional semiconductor materials, dielectric materials, conductive materials, or non-conductive materials may be formed on the polycrystalline SiC substrate 108 when manufacturing various electronic devices. For example, these electronic devices may include semiconductor dies, semiconductor packages, or some other similar types of semiconductor or electrical devices. For example, in at least one embodiment, another semiconductor material may be a single crystal SiC substrate or layer formed on a surface 118 of the polycrystalline SiC substrate 114 facing away from the carrier polycrystalline SiC substrate 108. In some embodiments, the single crystal SiC substrate or layer may be physically and directly bonded to the surface 118 of the polycrystalline SiC substrate 114 facing away from the carrier polycrystalline SiC substrate 108. In some embodiments, a bonding layer may exist between the single crystal SiC substrate or layer and the surface 118 of the polycrystalline SiC substrate 114 facing away from the carrier polycrystalline SiC substrate 108. For example, in some embodiments, the bonding layer may be an adhesive or may be some other suitable type of bonding layer that bonds or couples the single crystal SiC substrate or layer to the polycrystalline SiC substrate or layer 114.

[0045] For example, in a so-called direct bonded SiC substrate, a single crystal SiC substrate or layer may be bonded to, coupled to, or formed on a surface 118 of the polycrystalline SiC substrate 114 facing away from the carrier polycrystalline SiC substrate 108. In some embodiments, when the single crystal SiC substrate or layer is a single crystal SiC substrate, the single crystal SiC substrate may be bonded to or coupled to a surface 118 of the polycrystalline SiC substrate 114 facing away from the carrier polycrystalline SiC substrate 108. In some embodiments, the single crystal SiC substrate may be coupled to the surface 118 of the polycrystalline SiC substrate 114 facing away from the carrier polycrystalline SiC substrate 108 by a bonding layer, which may be, for example, an adhesive or some other suitable type of material for coupling the single crystal SiC substrate to the surface 118 of the polycrystalline SiC substrate 114.

[0046] In some embodiments, the single crystal SiC substrate may have been previously singulated from a thicker single crystal SiC base substrate, such that the single crystal SiC substrate bonded or coupled to the surface 118 of the polycrystalline SiC substrate 114 has a thickness of less than or equal to 1 micrometer (μm), which is less than the thickness of the thicker single crystal SiC base substrate from which the single crystal SiC substrate was singulated. In other words, the thicker single crystal SiC base substrate may be singulated multiple times (e.g., 10 to 50 times) such that multiple thinner single crystal SiC substrates are formed, which are then coupled to multiple respective surfaces of respective polycrystalline SiC substrates 114 facing away from respective surfaces 118 of respective carrier polycrystalline SiC substrates 108.

[0047] Forming at least one embodiment of the polycrystalline SiC substrate 114 and using it to form electronic devices and semiconductor packages reduces the “on” resistivity (Ron ). Reduce the “on” resistivity (R on ) reduces the resistance so that electrical signals are less hindered when passing through the polycrystalline SiC substrate 114 within electronic devices and semiconductor devices incorporated into and present on the polycrystalline SiC substrate 114.

[0048] In view of the above discussion, because the first CTE of the carrier polycrystalline SiC substrate 108 is substantially the same or equal to the second CTE of the polycrystalline SiC substrate 114 formed on the carrier polycrystalline SiC substrate 108, the polycrystalline SiC substrate 114 can be formed much thinner than when the carrier substrate is instead made of a different material having a CTE different from the first and second CTEs.

[0049] When manufacturing the polycrystalline SiC substrate 114, the following method is used: Figure 1 The method of flowchart 100 shown in FIG. 1 forms a polycrystalline SiC substrate 114 on a carrier polycrystalline SiC substrate 108 to maintain warpage within the polycrystalline SiC substrate 114 , the carrier polycrystalline SiC substrate 108 , or both to less than or equal to 75 micrometers (μm).

[0050] Figure 3 A perspective view of a carrier polycrystalline SiC substrate 108 is shown including a first surface 110 (ie, surface 110) and a second surface 119 opposite the first surface 110. The first surface 110 is the surface 110 on which a polycrystalline SiC substrate 114 is to be formed on the carrier polycrystalline SiC substrate 108. Figure 1 The method in the flowchart 100 shown in FIG. 1 forms a polycrystalline SiC substrate 114 on a carrier polycrystalline SiC substrate 108. The carrier polycrystalline SiC substrate 108 includes a first sidewall 120 that is transverse to a first surface 110 and a second surface 119 and extends from the first surface 110 to the second surface 119. Figure 3 In the embodiment shown in , the carrier polycrystalline SiC substrate 108 has a cylindrical profile. However, in some alternative embodiments, the carrier polycrystalline SiC substrate 108 may have some other type of 3D polygonal profile or some other type of 3D profile.

[0051] Figure 4A perspective view of a stacked polycrystalline SiC assembly is illustrated, wherein a polycrystalline SiC substrate 114 has been formed on a first surface 110 of a carrier polycrystalline SiC substrate 108 such that the polycrystalline SiC substrate 114 is coupled to the first surface 110 of the carrier polycrystalline SiC substrate 108. The polycrystalline SiC substrate 114 has a third surface 116 (i.e., opposing surface 116) coupled to the first surface 110 of the carrier polycrystalline SiC substrate 108 and a fourth surface 118 (i.e., surface 118) facing away from the carrier polycrystalline SiC substrate 108. The fourth surface 118 may be the surface 118 of the polycrystalline SiC substrate 114 facing away from the carrier polycrystalline SiC substrate 108, which may be polished as described above. A second surface 119 of the carrier polycrystalline SiC substrate 108 faces away from the polycrystalline SiC substrate 114. Figure 4 In the embodiment shown in , the first thickness T1 of the carrier polycrystalline SiC substrate 108 is substantially equal to the second thickness T2 of the polycrystalline SiC substrate 114. In some alternative embodiments, the first thickness T1 may be less than or greater than the second thickness T2, or the first thickness T1 may be greater than the second thickness T2. The polycrystalline SiC substrate 114 includes a second sidewall 122 that is transverse to the third surface 116 and the fourth surface 118, and the second sidewall 122 extends from the third surface 116 to the fourth surface 118. The second sidewall 122 of the polycrystalline SiC substrate 114 is coplanar with the first sidewall 120 of the carrier polycrystalline SiC substrate 108.

[0052] Figure 5 1 is a perspective view of an embodiment of the polycrystalline SiC substrate 114 after the carrier polycrystalline SiC substrate 108 is removed from the third surface 116 of the polycrystalline SiC substrate 114. After the carrier polycrystalline SiC substrate 108 is removed from the polycrystalline SiC substrate 114, each of the respective surfaces 116, 118 of the polycrystalline SiC substrate 114 may be polished to have a surface area of ​​less than or equal to 20 angstroms. In some embodiments, after the carrier polycrystalline SiC substrate 108 is removed from the polycrystalline SiC substrate 114, each of the respective surfaces 116, 118 of the polycrystalline SiC substrate 114 may be polished to have a roughness of less than or equal to 5 angstroms. Roughness.

[0053] At least one embodiment of the method of the present disclosure can be summarized as including: forming a carrier polycrystalline silicon carbide (SiC) substrate having a surface, the forming of the carrier polycrystalline SiC substrate including: sintering one or more powder materials to form a carrier polycrystalline SiC substrate; forming a polycrystalline SiC substrate on the surface of the carrier polycrystalline SiC substrate including: depositing SiC on the surface of the carrier polycrystalline SiC substrate using a chemical vapor deposition (CVD) process.

[0054] The method may further include cooling the polycrystalline SiC substrate and the carrier polycrystalline SiC substrate.

[0055] The carrier polycrystalline SiC substrate may have a first coefficient of thermal expansion (CTE), and the polycrystalline SiC substrate may have a second CTE, and the first CTE may be substantially equal to the second CTE.

[0056] The method may further include polishing a surface of the polycrystalline SiC substrate facing away from the surface of the carrier polycrystalline SiC substrate to have a surface thickness less than or equal to 5 angstroms. Roughness.

[0057] The method may further include removing the polycrystalline SiC substrate from the carrier polycrystalline SiC substrate.

[0058] Removing the polycrystalline SiC substrate from the carrier polycrystalline SiC substrate may include grinding away the carrier polycrystalline SiC substrate.

[0059] Grinding away the carrier polycrystalline SiC substrate may also include exposing a surface of the polycrystalline SiC substrate.

[0060] At least one embodiment of a device of the present disclosure can be summarized as including: a first polycrystalline SiC substrate including a first surface and a second surface opposite the first surface; and a second polycrystalline SiC substrate coupled to the second surface of the first polycrystalline SiC substrate.

[0061] The first polycrystalline SiC substrate may have a first sidewall; and the second polycrystalline SiC substrate may have a second sidewall substantially coplanar with the first sidewall.

[0062] The first polycrystalline SiC substrate may have a first coefficient of thermal expansion (CTE); the second polycrystalline SiC substrate may have a second CTE; and the first CTE may be substantially equal to the second CTE.

[0063] The second polycrystalline SiC substrate may include a third surface facing away from the first surface.

[0064] The second polycrystalline SiC substrate may include a third surface facing away from the first polycrystalline SiC substrate, and the third surface of the second polycrystalline SiC substrate may have a thickness less than or equal to 5 angstroms. Roughness.

[0065] In view of the discussion herein, the present disclosure relates to a polycrystalline SiC base substrate that is formed and then used or utilized to directly bond another polycrystalline SiC substrate to or to form another polycrystalline SiC substrate on a polycrystalline SiC base substrate. For example, in at least one embodiment, another polycrystalline SiC substrate is formed on or to a polycrystalline SiC base substrate by forming or bonding a polycrystalline SiC substrate to a corresponding surface of a polycrystalline SiC base substrate. This direct bonding or formation of another polycrystalline SiC substrate on a corresponding surface of a polycrystalline SiC base substrate can be used to replace the standard formation process of SiC substrates or polycrystalline SiC substrates known within the SiC device industry.

[0066] In view of the above discussion herein, polycrystalline SiC substrates known in the semiconductor industry can be manufactured by CVD (i.e., chemical vapor deposition) growth or PVT (i.e., physical vapor transport) growth processes or techniques. Sintered substrates are known in the semiconductor industry and can have a lower density than substrates produced by CVD or PVT, which can have the same or similar density as single crystal (e.g., single crystal) silicon carbide (SiC) substrates known in the semiconductor industry. In order to grow CVD and PVT substrates, a graphite substrate is used as a starting substrate (e.g., a carrier or base substrate). As discussed herein, this causes several problems, the main problem being the stress and strain caused by the different thermal expansion of graphite and the grown silicon carbide (SiC). This difference in thermal expansion can cause large warping, cracks, or additional complications (e.g., other types of mechanical defects), thereby increasing material processing costs (e.g., waste costs and reduced yields). Graphite also needs to be completely removed and cannot be retained on the back side of the polycrystalline silicon carbide (SiC) substrate, which always requires a fairly thick layer to be manufactured on the graphite substrate. When removing the graphite substrate from the polycrystalline SiC substrate, this thick layer manufacturing requirement increases the process cost of avoiding the propagation of mechanical defects within the polycrystalline SiC substrate formed on the graphite substrate. The embodiments of the present disclosure regarding forming the polycrystalline SiC substrate 114 of the present disclosure solve these problems regarding forming the corresponding polycrystalline SiC substrate using these known formation processes.

[0067] Although the above disclosure discusses at least one embodiment of forming the polycrystalline SiC substrate 114 on the surface 110 of the carrier polycrystalline SiC substrate 108 using a CVD process, another SiC substrate forming technology, such as a PVT (i.e., physical vapor transport) process or some other suitable process known in the semiconductor industry, may also be used to form the polycrystalline SiC substrate 114 on the surface 110 of the carrier polycrystalline SiC substrate 108.

[0068] Forming a polycrystalline SiC substrate using a formation process known in the semiconductor industry may result in thermal expansion mismatches, thereby generating mechanical defects (e.g., warpage, cracks, etc.), thereby reducing yield. Formation processes known in the semiconductor industry may require additional processing steps, such as having to remove the starting substrate from the backside surface of the polycrystalline SiC substrate before incorporating it into an electronic device or semiconductor package, which increases manufacturing costs. Formation processes known in the semiconductor industry may be limited because the polycrystalline SiC substrate must be made relatively thick so that the possibility of damaging the polycrystalline SiC substrate is reduced or prevented when the starting substrate is removed from the polycrystalline SiC substrate. Embodiments of the polycrystalline SiC substrate 114 of the present disclosure solve these shortcomings and problems with the formation process of polycrystalline SiC substrates known in the semiconductor industry. For example, embodiments of the polycrystalline SiC substrate 114 as discussed herein can be made thinner than those known in the semiconductor industry, can be formed to avoid any thermal mismatch between embodiments of the polycrystalline SiC substrate 114 and a carrier or starting substrate (e.g., a polycrystalline carrier SiC substrate 108), and can be formed to have low bow and warpage. Furthermore, embodiments of the polycrystalline SiC substrate 114 may be manufactured more cheaply than using processes known within the semiconductor industry.

[0069] As discussed herein, in at least one embodiment, the present disclosure is directed to forming a stacked structure having a sintered polycrystalline silicon carbide (SiC) starting substrate, with a dense CVD-grown polycrystalline silicon carbide layer or substrate on top of the starting substrate (e.g., based on the orientation of the sintered polycrystalline (SiC) starting substrate). The dense CVD-grown polycrystalline silicon carbide layer or substrate can have a typical thickness of at least 50-100 microns (μm) or equal to 150 microns (μm). The CVD-grown polycrystalline silicon carbide layer or substrate can then be polished, and a thin layer or substrate of single crystal SiC can be bonded to, coupled to, or formed on the CVD-grown polycrystalline silicon carbide layer or substrate of the present disclosure. The stacked substrate can then be used for electronic or semiconductor device manufacturing. In some embodiments, the process can include removing the sintered substrate in a back grinding step.

[0070] The present disclosure relates to at least one embodiment of a stacked structure that includes a sintered carrier SiC substrate (e.g., a polycrystalline carrier SiC substrate 108) on which a CVD-grown SiC layer or substrate (e.g., a polycrystalline SiC substrate 114) is formed or grown. For example, a surface (e.g., surface 110 of the polycrystalline SiC substrate 108) may be a top surface (e.g., based on the orientation of the sintered carrier SiC substrate) on which a CVD-grown SiC layer or substrate is formed or grown using a CVD (i.e., chemical vapor deposition) process or technique. The CVD-grown SiC layer or substrate may have a first density that is equal to the density of a single crystal SiC layer or substrate subsequently formed on the CVD-grown SiC layer or substrate. The sintered carrier SiC substrate may have a lower density than the CVD-grown SiC layer or substrate. The CVD-grown SiC layer or substrate may have been polished to have a thickness of less than or equal to 5 angstroms. The roughness of the surface.

[0071] At least one embodiment of the manufacturing method disclosed herein includes forming a first polycrystalline silicon carbide (SiC) substrate by sintering a powdered semiconductor material (e.g., a mixture of powdered silicon (Si) and powdered carbon (C), or powdered SiC) using a sintering process. After forming the first polycrystalline SiC substrate using the sintering process, forming a second polycrystalline SiC substrate using the first polycrystalline silicon carbide SiC substrate by a chemical vapor deposition (CVD) process. The second polycrystalline SiC substrate is formed on the surface of the first polycrystalline SiC substrate by depositing SiC on the surface of the first polycrystalline SiC substrate using a CVD process. Since the first polycrystalline SiC substrate and the second polycrystalline SiC substrate are made of the same or similar semiconductor material (e.g., SiC), the first coefficient of thermal expansion (CTE) of the first polycrystalline SiC substrate is the same or similar to the second CTE of the second polycrystalline SiC substrate.

[0072] Unlike when there is a thermal mismatch between a corresponding carrier (e.g., a graphite or graphene carrier) and a corresponding wafer (e.g., a silicon carbide (SiC) wafer) formed on the corresponding carrier, which may cause mechanical defects to propagate within the corresponding carrier, the corresponding wafer, or both when further processing and refinement steps (e.g., polishing, thinning, heating, etc.) are performed to manufacture corresponding semiconductor and electronic devices, in at least one embodiment of the manufacturing method of the present disclosure, the first and second CTEs of each of the first (e.g., carrier) and second (e.g., wafer) polycrystalline SiC substrates are substantially the same (e.g., equal) or similar to each other to prevent, mitigate or reduce the possibility of propagation of mechanical defects (e.g., cracks, warping, chipping, breakage, etc.) that propagate or occur within the first polycrystalline SiC substrate and the second polycrystalline SiC substrate when the second polycrystalline SiC substrate (e.g., wafer) is manufactured using the first polycrystalline SiC substrate (e.g., carrier). For example, stresses caused by exposure to increases and decreases in heat (i.e., increases in temperature or decreases in temperature) in either of the first polycrystalline SiC substrate and the second polycrystalline SiC substrate will be further mitigated in other processing and refinement steps that may occur at later stages during manufacturing. In at least one embodiment of a method of manufacturing a second polycrystalline SiC substrate, the first polycrystalline SiC substrate may be ground so that a surface of the second polycrystalline SiC substrate is exposed. The grinding process may cause an increase in temperature of both the first polycrystalline SiC substrate and the second polycrystalline SiC substrate; however, since the first and second CTEs are the same or similar, any propagation of mechanical defects will be prevented or the likelihood of propagation will be reduced.

[0073] In view of the above discussion, embodiments of the present disclosure prevent, mitigate or reduce the possibility of mechanical defects propagating within the first polycrystalline SiC substrate and the second polycrystalline SiC substrate when the first polycrystalline SiC substrate is used to form the second polycrystalline SiC substrate. Moreover, in view of the above discussion, embodiments of the present disclosure prevent or reduce the possibility of mechanical defects propagating within both the first polycrystalline SiC substrate and the second polycrystalline SiC substrate when the first polycrystalline SiC substrate and the second polycrystalline SiC substrate are further refined or processed.

[0074] One aspect of the present disclosure provides a method, comprising: forming a carrier polycrystalline silicon carbide (SiC) substrate having a surface, wherein forming the carrier polycrystalline SiC substrate comprises: sintering one or more powder materials to form the carrier polycrystalline SiC substrate; and forming a polycrystalline SiC substrate on the surface of the carrier polycrystalline SiC substrate, wherein forming the polycrystalline SiC substrate comprises: depositing SiC onto the surface of the carrier polycrystalline SiC substrate using a chemical vapor deposition (CVD) process.

[0075] In some embodiments of the present disclosure, the method further includes cooling the polycrystalline SiC substrate and the carrier polycrystalline SiC substrate.

[0076] In some embodiments of the present disclosure, the carrier polycrystalline SiC substrate has a first coefficient of thermal expansion (CTE), and the polycrystalline SiC substrate has a second CTE, and the first CTE is substantially equal to the second CTE.

[0077] In some embodiments of the present disclosure, the method further includes polishing a surface of the polycrystalline SiC substrate facing away from the surface of the carrier polycrystalline SiC substrate to have a surface roughness less than or equal to 5 angstroms. Roughness.

[0078] In some embodiments of the present disclosure, the method further includes removing the polycrystalline SiC substrate from the carrier polycrystalline SiC substrate.

[0079] In some embodiments of the present disclosure, removing the polycrystalline SiC substrate from the carrier polycrystalline SiC substrate includes grinding away the carrier polycrystalline SiC substrate.

[0080] In some embodiments of the present disclosure, grinding away the carrier polycrystalline SiC substrate further includes exposing a surface of the polycrystalline SiC substrate.

[0081] In some embodiments of the present disclosure, the method further includes forming one or more semiconductor layers on a surface of the polycrystalline SiC substrate.

[0082] In some embodiments of the present disclosure, the one or more semiconductor layers include at least one single crystalline layer.

[0083] In some embodiments of the present disclosure, the at least one single crystal layer is a single crystal SiC layer.

[0084] Another aspect of the present disclosure provides a method, comprising: forming a polycrystalline SiC substrate having a second thermal expansion coefficient substantially equal to a first thermal expansion coefficient on a first surface of a polycrystalline SiC carrier substrate, the forming of the polycrystalline SiC substrate comprising forming a second surface of the polycrystalline SiC substrate facing away from the carrier polycrystalline SiC substrate; and after forming the polycrystalline SiC substrate, removing the polycrystalline SiC substrate from the carrier polycrystalline SiC substrate.

[0085] In some embodiments of the present disclosure, the method further includes polishing the second surface of the polycrystalline SiC substrate to have a surface roughness less than or equal to 20 angstroms. Roughness.

[0086] In some embodiments of the present disclosure, the method further includes forming a single crystal SiC layer on the second surface of the polycrystalline SiC substrate.

[0087] In some embodiments of the present disclosure, the polycrystalline SiC substrate has a first density, and the single crystal SiC layer has a second density substantially equal to the first density.

[0088] In some embodiments of the present disclosure, the method further includes wherein the polycrystalline SiC substrate and the polycrystalline SiC carrier substrate have a cubic structure.

[0089] The various embodiments described above can be combined to provide further embodiments. Aspects of the embodiments can be modified, if necessary to employ concepts of the various patents, applications and publications to provide further embodiments.

[0090] In light of the above detailed description, these and other changes may be made to the embodiments. In general, in the appended claims, the terms used should not be interpreted as limiting the claims to the specific embodiments disclosed in the specification and claims, but should be interpreted to include all possible embodiments and the full range of equivalent forms given to these embodiments. Therefore, the claims are not limited by the present disclosure.

Claims

1. An electronic device based on silicon carbide, characterized in that include: A first polycrystalline SiC substrate including a first surface and a second surface opposite to the first surface, wherein the first polycrystalline SiC substrate has a first cubic structure; as well as A second polycrystalline SiC substrate is coupled to the second surface of the first polycrystalline SiC substrate, the second polycrystalline SiC substrate having a second cubic structure.

2. The silicon carbide-based electronic device of claim 1, wherein: The first polycrystalline SiC substrate has a first sidewall; and The second polycrystalline SiC substrate has a second sidewall substantially coplanar with the first sidewall.

3. The silicon carbide-based electronic device of claim 1, wherein: The first polycrystalline SiC substrate has a first coefficient of thermal expansion; The second polycrystalline SiC substrate has a second coefficient of thermal expansion; and The first coefficient of thermal expansion is substantially equal to the second coefficient of thermal expansion. 4 . The silicon carbide based electronic device of claim 1 , wherein the second polycrystalline SiC substrate comprises a third surface facing away from the first surface.

5. The silicon carbide-based electronic device according to claim 1, wherein the second polycrystalline SiC substrate comprises a third surface facing away from the first polycrystalline SiC substrate, and the third surface of the second polycrystalline SiC substrate has a thickness less than or equal to 5 angstroms. Roughness.

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