CAN (Controller Area Network) chip-based enabling circuit system and electronic equipment

Abstract

The utility model discloses an enabling circuit system based on a CAN chip. The enabling circuit system comprises the CAN chip, a micro-control unit, an SBC chip and an AND gate circuit. The first output end of the micro-control unit is connected with the first input end of the AND gate circuit, and the micro-control unit is used for sending a first signal to the AND gate circuit. A second output end of the micro-control unit is connected with a first input end of the SBC chip, and the micro-control unit is used for inputting a WDI signal to the SBC chip; a third output end of the micro-control unit is connected with a second input end of the SBC chip, and the micro-control unit is used for inputting an SMU signal to the SBC chip; the output end of the SBC chip is connected with the second input end of the AND gate circuit and is used for sending a second signal to the AND gate circuit; the output end of the AND gate circuit is connected with the input end of the CAN chip, and the AND gate circuit is used for sending a third signal to the CAN chip, and the third signal is used for enabling the CAN chip. According to the utility model, the enabling circuit of the CAN chip can be simplified. The utility model also provides an electronic device.

Description

Technical Field

[0001] The utility model relates to the field of electronic circuits, in particular to an enabling circuit system and electronic equipment based on a CAN chip. Background Art

[0002] Controller Area Network (CAN) is a standardized serial communication protocol developed by the International Organization for Standardization (ISO). CAN belongs to the fieldbus category and is a serial communication network that effectively supports distributed control or real-time control. With the vigorous development of the new energy industry and the popularity of electric vehicles, CAN communication technology for automotive system communication has been widely used.

[0003] The enabling circuit of the existing CAN chip requires three signals to be ANDed before the enabling control input can be completed. The three-way signal input makes the enabling circuit of the CAN chip more complicated and the diagnostic strategy is imperfect, which increases the hardware cost. Utility Model Content

[0004] The purpose of the utility model is to solve the technical problem that the enabling circuit of the CAN chip in the prior art is complicated and causes high hardware cost. The utility model provides an enabling circuit system based on the CAN chip, which can simplify the enabling circuit of the CAN chip and save costs.

[0005] In order to solve the above technical problems, the embodiment of the utility model discloses an enabling circuit system based on a CAN chip, comprising:

[0006] A CAN chip, wherein the CAN chip comprises an input terminal;

[0007] A micro control unit, the micro control unit comprising a first output terminal, a second output terminal and a third output terminal;

[0008] An SBC chip, wherein the SBC chip comprises a first input terminal, a second input terminal and an output terminal;

[0009] An AND gate circuit, the AND gate circuit comprising a first input terminal, a second input terminal and an output terminal; wherein,

[0010] The first output terminal of the micro control unit is connected to the first input terminal of the AND gate circuit, and is used to send a first signal to the AND gate circuit;

[0011] The second output terminal of the micro control unit is connected to the first input terminal of the SBC chip, and is used to input a WDI signal to the SBC chip;

[0012] The third output terminal of the micro control unit is connected to the second input terminal of the SBC chip, and is used to input the SMU signal to the SBC chip;

[0013] The output end of the SBC chip is connected to the second input end of the AND gate circuit, and is used to send a second signal to the AND gate circuit;

[0014] The output end of the AND gate circuit is connected to the input end of the CAN chip and is used to send a third signal to the CAN chip, where the third signal is used to enable the CAN chip.

[0015] By adopting the above technical solution, the embodiment of the present application uses an SBC chip to integrate the SMU signal from the microcontroller unit, so that the enabling circuit of the present application can achieve the effect of enabling the CAN chip by only sending a first signal to the AND gate circuit through the microcontroller unit and the SBC chip sending a second signal to the AND gate circuit.

[0016] In other words, compared with the prior art, the AND gate circuit of the embodiment of the present application does not need to compare three signals, but only needs to compare two signals, namely the first signal and the second signal, thereby simplifying the enabling circuit of the CAN chip, simplifying the logic process, reducing the error rate of the enabling circuit, improving the reliability of the circuit, and saving costs.

[0017] According to another specific embodiment of the utility model, the embodiment of the utility model discloses an enabling circuit system based on a CAN chip, if the micro control unit is in a normal working state, and the SBC chip is in a normal working state, the second signal is a high level;

[0018] If the first signal is at a high level, the AND gate circuit sends the third signal to the CAN chip to enable the CAN chip.

[0019] According to another specific embodiment of the utility model, the embodiment of the utility model discloses an enabling circuit system based on a CAN chip, if the micro control unit is in a normal working state and the SBC chip is in a non-working state, the second signal is a low level;

[0020] If the first signal is at a high level, the AND gate circuit does not send the third signal to the CAN chip.

[0021] According to another specific embodiment of the utility model, the embodiment of the utility model discloses an enabling circuit system based on a CAN chip, if the micro control unit is in a non-working state, and the SBC chip is in a normal working state, the second signal is a low level;

[0022] If the first signal is at a high level, the AND gate circuit does not send the third signal to the CAN chip.

[0023] According to another specific embodiment of the utility model, the embodiment of the utility model discloses an enabling circuit system based on a CAN chip, if the micro control unit is in a non-working state and the SBC chip is in a non-working state, the second signal is a low level;

[0024] If the first signal is at a high level, the AND gate circuit does not send the third signal to the CAN chip.

[0025] According to another specific implementation of the present invention, the implementation of the present invention discloses an enabling circuit system based on a CAN chip, and if the first signal is at a low level, the AND gate circuit does not send the third signal to the CAN chip.

[0026] According to another specific embodiment of the utility model, the embodiment of the utility model discloses an enabling circuit system based on a CAN chip, wherein the SBC chip includes a watchdog input pin and an error signal input pin;

[0027] The watchdog input pin of the SBC chip is used to receive the WDI signal, and the error signal input pin of the SBC chip is used to receive the SMU signal to monitor the micro control unit.

[0028] By adopting the above technical solution, the embodiment of the present application also integrates the WDI signal from the micro control unit through the SBC chip, performs watchdog monitoring on the micro control unit, and makes the diagnosis strategy more complete.

[0029] According to another specific embodiment of the utility model, the embodiment of the utility model discloses an enabling circuit system based on a CAN chip, wherein the SBC chip also includes a window door dog monitoring module and a functional watchdog monitoring module, and the window door dog monitoring module and the functional watchdog monitoring module are used to monitor the SBC chip.

[0030] By adopting the above technical solution, the SBC chip of the embodiment of the present application not only integrates the SMU signal and WDI signal from the microcontroller unit inside the chip, but also performs window door dog monitoring and functional watchdog monitoring on the SBC chip itself, further improving the diagnosis strategy.

[0031] According to another specific implementation of the present invention, the implementation of the present invention discloses an enabling circuit system based on a CAN chip, wherein the CAN chip includes a TJA1043T, and the SBC chip includes a TLF35585.

[0032] The embodiment of the utility model further discloses an electronic device, which at least includes the enabling circuit system based on the CAN chip in any one of the above embodiments. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] Figure 1 A schematic diagram showing the structure of an enabling circuit system based on a CAN chip provided in an embodiment of the present application is shown;

[0034] Figure 2 A schematic diagram showing an enabling circuit system based on a CAN chip provided in an embodiment of the present application Figure 1 ;

[0035] Figure 3 A schematic diagram showing an enabling circuit system based on a CAN chip provided in an embodiment of the present application Figure 2 Among them, the SBC chip includes a window watchdog monitoring module and a functional watchdog monitoring module. DETAILED DESCRIPTION

[0036] The following is an explanation of the implementation of the present invention by specific specific embodiments. Those skilled in the art can easily understand other advantages and functions of the present invention from the contents disclosed in this specification. Although the description of the present invention will be introduced in conjunction with the preferred embodiment, this does not mean that the features of this utility model are limited to this implementation. On the contrary, the purpose of introducing the utility model in conjunction with the implementation is to cover other options or modifications that may be extended based on the claims of the present invention. In order to provide a deep understanding of the present invention, the following description will include many specific details. The present invention can also be implemented without using these details. In addition, in order to avoid confusion or blurring the focus of the present invention, some specific details will be omitted in the description. It should be noted that, in the absence of conflict, the embodiments in the present invention and the features in the embodiments can be combined with each other.

[0037] It should be noted that in this specification, similar reference numerals and letters denote similar items in the following drawings, and therefore, once an item is defined in one drawing, it does not need to be further defined and explained in the subsequent drawings.

[0038] In the description of this embodiment, it should be noted that the terms "upper", "lower", "inner", "bottom", etc. indicate orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings, or are the orientations or positional relationships in which the utility model product is usually placed when in use. They are only for the convenience of describing the utility model and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the utility model.

[0039] The terms “first”, “second”, etc. are only used for distinguishing descriptions and should not be understood as indicating or implying relative importance.

[0040] In the description of this embodiment, it is also necessary to explain that, unless otherwise clearly specified and limited, the terms "set", "connected", and "connected" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection, or it can be indirectly connected through an intermediate medium, or it can be the internal communication of two components. For ordinary technicians in this field, the specific meanings of the above terms in this embodiment can be understood according to specific circumstances.

[0041] In order to make the purpose, technical solution and advantages of the present invention more clear, the implementation mode of the present invention will be further described in detail below with reference to the accompanying drawings.

[0042] In the prior art, CAN chips generally require three signals to be ANDed before enabling control input can be completed, namely CAN_WAKE_EN from MCU, / WDA from SBC and / SMU from MCU. That is, the CAN chip can only be enabled when the AND gate circuit receives these three signals.

[0043] However, the CAN chip enabling circuit system in the prior art has the following problems:

[0044] 1) The three-way signal input makes the circuit more complicated and the logic process complicated, resulting in a high error probability of the enabling circuit, low circuit reliability, and high cost.

[0045] 2) The diagnostic strategy is not perfect and the watchdog monitoring of the Microcontroller Unit (MCU) is not performed.

[0046] For the above problems, refer to Figure 1 An embodiment of the present application provides an enabling circuit system 1 based on a CAN chip, and the enabling circuit system 1 can be applied to an electronic device having a CAN chip.

[0047] Figure 1 A schematic diagram of the structure of an enabling circuit system based on a CAN chip provided in an embodiment of the present application is shown.

[0048] like Figure 1As shown, the CAN chip-based enabling circuit system 1 provided in the embodiment of the present application includes: a microcontroller unit 101, an SBC chip 102, an AND gate circuit 103 and a CAN chip 104. For example, the model of the CAN chip 104 in the embodiment of the present application includes TJA1043T, and the model of the SBC chip 102 includes TLF35585.

[0049] Continue to refer Figure 1 Combined with Figure 2 The micro control unit 101 and the SBC chip 102 are connected to each other and are respectively connected to an AND gate circuit 103 , and the AND gate circuit 103 is connected to a CAN chip 104 . Figure 2 A schematic diagram of an enabling circuit system based on a CAN chip provided in an embodiment of the present application is shown.

[0050] Specifically, Figure 2 As shown, the micro control unit 101 includes a first output terminal 1011, a second output terminal 1012 and a third output terminal 1013, the SBC chip 102 includes a first input terminal 1021, a second input terminal 1022 and an output terminal 1023, the AND gate circuit 103 includes a first input terminal 1031, a second input terminal 1032 and an output terminal 1033, and the CAN chip 104 includes an input terminal 1041.

[0051] Among them, the first output terminal 1011 of the micro control unit 101 is connected to the first input terminal 1031 of the AND gate circuit 103, and is used to send a first signal to the AND gate circuit 103. The second output terminal 1012 of the micro control unit 101 is connected to the first input terminal 1021 of the SBC chip 102, and is used to input a WDI signal to the SBC chip 102. The third output terminal 1013 of the micro control unit 101 is connected to the second input terminal 1022 of the SBC chip 102, and is used to input a SMU signal to the SBC chip 102.

[0052] It should be noted that SMU (Safety Management Unit) is a safety management unit of the microcontroller unit (MCU) 101, which is used to detect the system input and output functions and output normal or error signals. WDI (Watchdog Input, WDI) is a watchdog error interrupt signal, which detects the internal system operation status of the microcontroller unit (MCU) 101 through a timer. Exemplarily, the SBC chip 102 of the embodiment of the present application includes a watchdog input pin and an error signal input pin. The watchdog input pin of the SBC chip 102 is used to receive the WDI signal, and the error signal input pin of the SBC chip 102 is used to receive the SMU signal to monitor the status of the microcontroller unit 101.

[0053] The output terminal 1023 of the above-mentioned SBC chip 102 is connected to the second input terminal 1032 of the AND gate circuit 103, and is used to send a second signal to the AND gate circuit 103. The output terminal 1033 of the AND gate circuit 103 is connected to the input terminal 1041 of the CAN chip 104, and is used to send a third signal to the CAN chip 104. The third signal is used to enable the CAN chip 104.

[0054] Through the above circuit connection structure, the embodiment of the present application uses the SBC chip 102 to integrate the SMU signal from the micro control unit 101, so that the enabling circuit of the embodiment of the present application can achieve the effect of enabling the CAN chip only by sending the first signal to the AND gate circuit 103 through the micro control unit 101 and the SBC chip 102 sending the second signal to the AND gate circuit 103. In other words, compared with the prior art, the AND gate circuit 103 of the embodiment of the present application does not need to compare three signals, but only needs to compare two signals of the first signal and the second signal, which simplifies the enabling circuit of the CAN chip 104, simplifies the logic process, reduces the error rate of the enabling circuit, improves the reliability of the circuit, and saves costs.

[0055] Furthermore, the WDI signal from the micro control unit 101 is integrated through the SBC chip 102 to perform watchdog monitoring on the micro control unit 101, thereby making the diagnosis strategy more complete.

[0056] Based on this, in some possible implementations, if the micro control unit 101 is in a normal working state and the SBC chip 102 is in a normal working state, the second signal is at a high level. At this time, if the first signal is at a high level, the AND gate circuit 103 sends a third signal to the CAN chip 104 to enable the CAN chip 104.

[0057] Specifically, Figure 2 As shown, the first input terminal 1021 and the second input terminal 1022 of the SBC chip 102 receive the WDI signal and the SMU signal from the micro control unit 101 respectively, and detect that the micro control unit 101 is in a normal working state, and the SBC chip 102 also detects that it is also in a normal working state, then the second signal (for example, the SS1 signal) sent by the output terminal 1023 of the SBC chip 102 to the second input terminal 1032 of the AND gate circuit 103 is at a high level. At this time, if the first signal (for example, the CAN_EN signal) is at a high level, the AND gate circuit 103 determines to send a third signal to the CAN chip 104 according to the SS1 signal and the CAN_EN signal to enable the CAN chip 104.

[0058] It should be noted that the above-mentioned SS1 signal (ie, the second signal) is the safety state output of the SBC chip 102 , and the above-mentioned CAN_EN signal (ie, the first signal) is the enable signal of the CAN chip 104 of the micro control unit 101 .

[0059] In addition, in some other possible implementations, if the micro control unit 101 is in a normal working state and the SBC chip 102 is in a non-working state, the second signal is at a low level. At this time, if the first signal is at a high level, the AND gate circuit 103 does not send the third signal to the CAN chip 104.

[0060] Specifically, Figure 2 As shown, the first input terminal 1021 and the second input terminal 1022 of the SBC chip 102 receive the WDI signal and the SMU signal from the micro control unit 101 respectively, and detect that the micro control unit 101 is in a normal working state, while the SBC chip 102 also detects that it is in a non-working state, then the second signal (for example, the SS1 signal) sent by the output terminal 1023 of the SBC chip 102 to the second input terminal 1032 of the AND gate circuit 103 is at a low level. At this time, if the first signal (for example, the CAN_EN signal) is at a high level, the AND gate circuit 103 determines not to send the third signal to the CAN chip 104 according to the SS1 signal and the CAN_EN signal.

[0061] Similarly, in some other possible implementations, if the micro control unit 101 is in a non-operating state and the SBC chip 102 is in a normal operating state, the second signal is at a low level. At this time, if the first signal is at a high level, the AND gate circuit 103 does not send the third signal to the CAN chip 104.

[0062] Specifically, Figure 2 As shown, the first input terminal 1021 and the second input terminal 1022 of the SBC chip 102 receive the WDI signal and the SMU signal from the micro control unit 101 respectively, and detect that the micro control unit 101 is in a non-working state, while the SBC chip 102 also detects that it is in a normal working state, then the second signal (for example, the SS1 signal) sent by the output terminal 1023 of the SBC chip 102 to the second input terminal 1032 of the AND gate circuit 103 is at a low level. At this time, if the first signal (for example, the CAN_EN signal) is at a high level, the AND gate circuit 103 determines not to send the third signal to the CAN chip 104 according to the SS1 signal and the CAN_EN signal.

[0063] And, in some other possible implementations, if the micro control unit 101 is in a non-operating state and the SBC chip 102 is in a non-operating state, the second signal is at a low level. If the first signal is at a high level, the AND gate circuit 103 does not send the third signal to the CAN chip 104.

[0064] Specifically, Figure 2 As shown, the first input terminal 1021 and the second input terminal 1022 of the SBC chip 102 receive the WDI signal and the SMU signal from the micro control unit 101 respectively, and detect that the micro control unit 101 is in a non-working state, and the SBC chip 102 also detects that it is in a non-working state, then the second signal (for example, the SS1 signal) sent by the output terminal 1023 of the SBC chip 102 to the second input terminal 1032 of the AND gate circuit 103 is at a low level. At this time, if the first signal (for example, the CAN_EN signal) is at a high level, the AND gate circuit 103 determines not to send the third signal to the CAN chip 104 according to the SS1 signal and the CAN_EN signal.

[0065] Finally, in some other possible implementations, if the first signal sent by the micro control unit 101 to the AND gate circuit 103 is at a low level, the AND gate circuit 103 does not send the third signal to the CAN chip 104 .

[0066] Specifically, Figure 2 As shown, if the first input terminal 1031 of the AND gate circuit 103 receives the first signal (for example, the CAN_EN signal) from the micro control unit 101 at a low level, then at this time, the AND gate circuit 103 judges based on the SS1 signal and the CAN_EN signal. When the SS1 signal is at a low level or a high level, the AND gate circuit 103 does not send the third signal to the CAN chip 104.

[0067] refer to Figure 3 In some possible implementations, the SBC chip 102 further includes a window watchdog monitoring (WWD) module 112 and a functional watchdog monitoring (FWD) module 122 . Figure 3 The schematic diagram of the enabling circuit system based on the CAN chip provided by the embodiment of the present application is shown, wherein the window watchdog monitoring module 112 and the functional watchdog monitoring module 122 are used to monitor the status of the SBC chip 102 .

[0068] Therefore, the SBC chip 102 of the embodiment of the present application not only integrates the SMU signal and the WDI signal from the micro control unit 101 inside the chip, but also performs window watchdog monitoring and functional watchdog monitoring on the SBC chip 102 itself.

[0069] That is, the SBC chip 102 monitors the state of the microcontroller unit 101 by receiving the WDI signal and the SMU signal from the microcontroller unit 101; at the same time, the SBC chip 102 checks its own state through its own window watchdog monitoring module 112 and the functional watchdog monitoring module 122; thereafter, the SBC chip 102 outputs the SS1 signal (i.e., the second signal) according to the state of the microcontroller unit 101 and the state of the SBC chip 102, thereby further improving the diagnostic strategy.

[0070] like Figure 3 As shown, according to the above description, it can be seen that if the micro control unit 101 and the SBC chip 102 are both in normal working state, the SS1 signal (i.e., the second signal) sent by the output terminal 1023 of the SBC chip 102 to the second input terminal 1032 of the AND gate circuit 103 is at a high level. At this time, the CAN_EN signal (i.e., the first signal) sent by the first output terminal 1011 of the micro control unit 101 to the first input terminal 1031 of the AND gate circuit 103 is at a high level, so that the output terminal 1033 of the AND gate circuit 103 sends the third signal to the input terminal 1041 of the CAN chip 104, thereby enabling the CAN chip.

[0071] An embodiment of the present application further provides an electronic device, comprising an enabling circuit system 1 based on a CAN chip as in any one of the above-mentioned implementations.

[0072] Although the present invention has been illustrated and described with reference to certain preferred embodiments of the present invention, it should be understood by those skilled in the art that the above contents are further detailed descriptions of the present invention in combination with specific embodiments, and it cannot be determined that the specific implementation of the present invention is limited to these descriptions. Those skilled in the art may make various changes in form and details, including making several simple deductions or substitutions, without departing from the spirit and scope of the present invention.

Claims

1. An enabling circuit system based on a CAN chip, characterized in that: include: A CAN chip, wherein the CAN chip comprises an input terminal; A micro control unit, the micro control unit comprising a first output terminal, a second output terminal and a third output terminal; An SBC chip, wherein the SBC chip comprises a first input terminal, a second input terminal and an output terminal; An AND gate circuit, the AND gate circuit comprising a first input terminal, a second input terminal and an output terminal; wherein, The first output terminal of the micro control unit is connected to the first input terminal of the AND gate circuit, and is used to send a first signal to the AND gate circuit; The second output terminal of the micro control unit is connected to the first input terminal of the SBC chip, and is used to input a WDI signal to the SBC chip; The third output terminal of the micro control unit is connected to the second input terminal of the SBC chip, and is used to input the SMU signal to the SBC chip; The output end of the SBC chip is connected to the second input end of the AND gate circuit, and is used to send a second signal to the AND gate circuit; The output end of the AND gate circuit is connected to the input end of the CAN chip and is used to send a third signal to the CAN chip, where the third signal is used to enable the CAN chip.

2. The CAN chip-based enabling circuit system according to claim 1, characterized in that: If the micro control unit is in a normal working state and the SBC chip is in a normal working state, the second signal is a high level; If the first signal is at a high level, the AND gate circuit sends the third signal to the CAN chip to enable the CAN chip.

3. The CAN chip-based enabling circuit system according to claim 1, characterized in that: If the micro control unit is in a normal working state and the SBC chip is in a non-working state, the second signal is at a low level; If the first signal is at a high level, the AND gate circuit does not send the third signal to the CAN chip.

4. The CAN chip-based enabling circuit system according to claim 1, characterized in that: If the micro control unit is in a non-working state and the SBC chip is in a normal working state, the second signal is at a low level; If the first signal is at a high level, the AND gate circuit does not send the third signal to the CAN chip.

5. The CAN chip-based enabling circuit system according to claim 1, characterized in that: If the micro control unit is in a non-working state and the SBC chip is in a non-working state, the second signal is at a low level; If the first signal is at a high level, the AND gate circuit does not send the third signal to the CAN chip.

6. The CAN chip-based enabling circuit system according to claim 1, characterized in that: If the first signal is at a low level, the AND gate circuit does not send the third signal to the CAN chip.

7. The CAN chip-based enabling circuit system according to any one of claims 1 to 6, characterized in that: The SBC chip includes a watchdog input pin and an error signal input pin; The watchdog input pin of the SBC chip is used to receive the WDI signal, and the error signal input pin of the SBC chip is used to receive the SMU signal to monitor the micro control unit.

8. The CAN chip-based enabling circuit system according to claim 7, characterized in that: The SBC chip also includes a window door dog monitoring module and a functional watchdog monitoring module, and the window door dog monitoring module and the functional watchdog monitoring module are used to monitor the SBC chip.

9. The CAN chip-based enabling circuit system according to claim 1, characterized in that: The CAN chip includes TJA1043T, and the SBC chip includes TLF35585.

10. An electronic device, characterized in that: It comprises an enabling circuit system based on a CAN chip as described in any one of claims 1 to 9.

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