Semiconductor device

Abstract

In a semiconductor device, in order to reduce the incidence of stress concentration regions in etching openings, a thinner polyimide layer is deposited to minimize gaps formed therein and increase the angle of the surface of a display layer. In this way, the stress is reduced, the occurrence rate of metal contact cracking formed later is reduced, and the overall yield of the semiconductor device manufactured in this way is increased.

Description

Technical Field

[0001] Embodiments of the present disclosure relate generally to a semiconductor device. Background Art

[0002] An integrated circuit (IC) is formed on a semiconductor die that contains millions or billions of individual semiconductor devices. For example, transistor devices are configured to act as switches and / or to generate power gain to enable the logic functions of the IC chip (e.g., functions used to perform logic functions). IC chips also typically contain passive electronic devices, such as capacitors, resistors, inductors, etc. Passive devices are widely used to control chip characteristics (e.g., gain, time constants, etc.) to provide integrated chips with different functions (e.g., combining analog and digital circuits on the same die). Capacitors, such as metal-insulator-metal (MIM) capacitors, which include at least a top metal plate and a bottom metal plate separated by an insulating dielectric, are typically implemented in integrated circuits.

[0003] High-density integrated circuits such as very large scale integration (VLSI) and system on integrated chip (SoIC) single chips are usually formed by interconnect structures (also called interconnects) to properly connect densely packed devices together to form functional circuits. As the level of integration increases, the parasitic capacitance effect between the interconnected metal lines increases accordingly, resulting in signal delay and cross-talk. In order to reduce parasitic capacitance and increase the conduction speed of the interconnect, dielectric materials with low dielectric constant (low-k) are generally used to form interlayer dielectric (ILD) layers and intermetal dielectric (IMD) layers. Metal lines and vias are then formed in these layers. Conductive bumps, such as micro-bumps (μ-bumps) and controlled collapse chip connection (C4) bumps, are formed on top of these interconnect structures for connecting other devices. Utility Model Content

[0004] The present disclosure provides a semiconductor device, comprising: a first protective layer, a metal redistribution layer (RDL), a second protective layer, and a polyimide layer. The first protective layer is disposed above the metal contact. The metal redistribution layer (RDL) is disposed above a portion of the first protective layer. The second protective layer is disposed above a portion of the metal RDL, and the second protective layer has a first opening. The polyimide layer is disposed above the second protective layer, and the polyimide layer has a second opening. Wherein, a vertical cross-section of the second protective layer at the first opening has an inner bottom angle between 75 degrees and 85 degrees, and a vertical cross-section of the polyimide layer at the second opening has a top angle and a bottom angle, the top angle is between 160 degrees and 170 degrees, and the bottom angle is between 75 degrees and 85 degrees.

[0005] The present disclosure provides a semiconductor device having an improved layer opening for supporting a metal bump, the semiconductor device comprising: a metal contact, a protective layer, a metal insulator metal (MIM) capacitor layer, a redistribution layer (RDL), a silicon nitride layer, a polyimide layer, and a metal bump layer. The protective layer is disposed above the metal contact. The metal insulator metal capacitor layer is disposed in the protective layer. The redistribution layer extends through a portion of the protective layer and the MIM capacitor layer. The silicon nitride layer is disposed above a portion of the RDL. The polyimide layer is disposed above the silicon nitride layer. The metal bump layer extends through the silicon nitride layer and the polyimide layer and contacts the RDL, wherein the inner bottom angle at the intersection of the metal bump layer and the polyimide layer is between 60 degrees and 85 degrees.

[0006] The present disclosure provides a semiconductor device, comprising: a protection layer disposed over a metal contact layer of a wafer; a metal redistribution layer (RDL) disposed over a portion of a top surface of the protection layer; a silicon nitride (SiN) layer disposed over a portion of the metal RDL, the SiN layer having a first opening leading to a top of the metal RDL, wherein a cross section of the SiN layer at the first opening has an inner bottom angle between 75 degrees and 85 degrees; and a polyimide layer disposed over the SiN layer, the polyimide layer having a second opening at least partially disposed over the first opening leading to the metal RDL, wherein a cross section of the polyimide layer at the second opening has a top angle between 160 degrees and 170 degrees, and a bottom angle between 75 degrees and 85 degrees. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] The aspects of the present disclosure will be better understood from the following detailed description in conjunction with the accompanying drawings. It should be noted that, in accordance with standard industry practice, the features are not drawn to scale. In fact, the dimensions of the features may be arbitrarily increased or decreased to make the discussion clearer.

[0008] Figure 1A , Figure 1B , Figure 1C , Figure 1D , Figure 1E , Figure 1F , Figure 1G and Figure 1H are cross-sectional views of various stages of a sequential manufacturing process of a semiconductor device according to some embodiments;

[0009] Figure 2A and Figure 2B are cross-sectional views of additional stages of a sequential fabrication process for a semiconductor device according to some embodiments;

[0010] Figure 3A , Figure 3B and Figure 3C is a cross-sectional view of a further stage in a sequential fabrication process of a semiconductor device according to some embodiments;

[0011] Figure 4A and Figure 4B is a cross-sectional view of a further stage of a manufacturing process of a semiconductor device according to some embodiments;

[0012] Figure 5 is a flow chart of a semiconductor manufacturing process according to some embodiments;

[0013] Figure 6 is a cross-sectional view of a wiring diagram of a semiconductor device according to some embodiments.

[0014]

Explanation of symbols

[0015] 10:Semiconductor substrate (wafer)

[0016] 100:Semiconductor device

[0017] 101: Interlayer dielectric layer

[0018] 102: Top metal layer

[0019] 102a: Interconnection structure

[0020] 104: Etching stop layer

[0021] 106: (First) Protective Layer

[0022] 108: Metal-insulator-metal capacitor

[0023] 110: Redistribution through hole

[0024] 112: Barrier layer

[0025] 113: Metal seed layer

[0026] 114: Redistribution layer

[0027] 116: silicon nitride layer, (second) protective layer

[0028] 116a: Silicon nitride layer

[0029] 118: Polyimide layer

[0030] 120: Opening

[0031] 122: Opening

[0032] 124: Opening

[0033] 140: Metal bump layer

[0034] 150: Top exposed surface

[0035] 162:Inner corner

[0036] 172:Inner corner

[0037] 174:Inner corner

[0038] 500: Craftsmanship

[0039] 502,504,506,508,510,512,514,516,518,520,522,524,526,528,530: Operation

[0040] 600: Top view

[0041] XX: Section line DETAILED DESCRIPTION

[0042] The following disclosure provides many different embodiments or examples to implement different features of the subject matter provided. The specific examples of components and arrangements described below are intended to simplify the disclosure. Of course, these are only examples and are not intended to be limiting. For example, in the following description, a first feature is formed on or above a second feature, which may include an embodiment in which the first feature and the second feature are formed in direct contact, and may also include an embodiment in which additional features may be formed between the first feature and the second feature, so that the first and second features may not be in direct contact. In addition, the disclosure may repeat reference numbers and / or letters in each embodiment. Such repetition is for the purpose of simplicity and clarity, and is not itself intended to limit the relationship between the various embodiments and / or configurations discussed.

[0043] In addition, spatially relative terms, such as "under," "below," "below," "above," "above," and similar terms may be used herein to facilitate description of the relationship between one element or component and another element or component(s) as shown in the accompanying drawings. These spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation shown in the drawings. The device / apparatus may be positioned in different ways (rotated 90 degrees or in other orientations), and the spatially relative descriptions used herein may be interpreted accordingly. In addition, the technical term "made of" may mean "comprising" or "consisting of." In the present disclosure, the technical term "one of A, B, and C" means "A, B, and / or C" (A, B, C, A and B, A and C, B and C, or A, B and C), and does not mean one element in A, one element in B, and one element in C, unless otherwise specified.

[0044] Those skilled in the art will readily appreciate that each pair of similar features shown in cross-section on opposite sides of an open gap or via is merely a work depicted in cross-section in the accompanying drawings. In various embodiments, each pair of such features is actually the opposite vertical edges or nearly vertical edges of an originally continuous three-dimensional semiconductor feature.

[0045] As semiconductor technology develops, the geometric size of the interconnect structure is reduced to increase IC density, thereby reducing manufacturing costs and improving device performance. In various embodiments, the interconnect structure includes lateral interconnects and vertical interconnects, lateral interconnects such as metal lines (wiring), and vertical interconnects such as contacts and via plugs. In addition, one or more protective layers are formed to protect the semiconductor device from moisture and the like. One type of semiconductor package is a system on integrated chip (SoIC) single chip package, in which multiple dies are integrated in a single package and a controlled collapse chip connection (C4) device.

[0046] Figure 1A , Figure 1B , Figure 1C , Figure 1D , Figure 1E , Figure 1F , Figure 1G and Figure 1H is a cross-sectional view of an initial stage of a sequential manufacturing process of a semiconductor device 100 according to various embodiments. It should be understood that additional embodiments of this method may be Figures 1A to 1HAdditional operations are provided before, during, and after the processes shown, and some of the operations described below may be replaced or removed. The order of operations / processes may be permuted. As shown in the figures and described in various embodiments herein, semiconductor device 100 includes one or more capacitive devices, transistors, and other electrical components (not shown), but other types of semiconductor devices with suitable configurations are readily contemplated.

[0047] refer to Figure 1A In various embodiments, the semiconductor device 100 includes a semiconductor substrate 10 or wafer, which in various embodiments is a bulk semiconductor substrate, a semiconductor on insulator (SOI) substrate, or another substrate. In various embodiments, the semiconductor material of the semiconductor substrate 10 is doped or undoped, such as with a P-type or N-type dopant. Other types of substrates, such as multilayer or gradient substrates, are also used in various embodiments. In some embodiments, the semiconductor material of the semiconductor substrate 10 may include an elemental semiconductor, such as silicon (Si) (e.g., crystalline silicon, such as Si <100> or Si <111> ) and germanium (Ge); or compound semiconductors including silicon carbide (Si x C y ), Gallium Arsenide (GaAs x As y ), Gallium Phosphide (Ga x P y ), Indium Phosphide (In x P y ), Indium Arsenide (In x As y ) and / or Indium Antimonide (In x Sb y );or contains Si x Ge y , Ga x As y P z 、Aluminum Indium Arsenide (Al x In y As z )、Al x Ga y As z , Ga x ln y As z , Ga x In y P z , Ga w In x As y P z Or an alloy semiconductor of a combination of the foregoing.

[0048] In various embodiments, such as Figure 1B As shown in FIG. 1 , one or more interlayer dielectric (ILD) layers 101 are formed above the semiconductor substrate 10 and the electronic components of the semiconductor substrate 10 . In some embodiments, the ILD layer 101 includes a dielectric material, such as silicon oxide (Si x O y ), silicon nitride (Si x N y ), silicon oxynitride (SiON), silicon oxycarbonitride (SiOCN), silicon carbonitride (SiCN), low-k dielectric materials, or any other suitable dielectric material.

[0049] In various embodiments, such as Figure 1C As shown in , a top metal (TM) layer 102 is disposed in one or more portions of the ILD layer 101, which are proximate to the top surface of the ILD layer 101. In some cases, an interconnect structure 102a is first deposited below the TM layer 102. In various embodiments, the TM layer 102 has a top surface that is coextensive and coplanar with the top surface of the ILD layer 101. In various embodiments, the TM layer 102 is located above and electrically coupled to a transistor or other electrical connection feature (not shown). In some embodiments, the TM layer 102 includes a metal or a metal alloy, such as copper, cobalt, nickel, aluminum, tungsten, titanium, or a combination of the foregoing. In some embodiments, the TM layer 102 is formed by a damascene process including depositing or plating a conductive material, followed by a chemical mechanical planarization (CMP) process. In some embodiments, the TM layer 102 is the topmost conductive layer formed by the damascene process. In some embodiments, the TM layer 102 is a pad electrode.

[0050] In various embodiments, such as Figure 1D As shown in FIG. 1 , an etch stop layer (ESL) 104 is deposited and disposed over the top surface of the ILD layer 101 and the TM layer 102 to protect the underlying layers from moisture and delamination during additional process steps in forming the semiconductor device 100. In some embodiments, the ESL 104 has a thickness between about 0.2 nanometers and about 2 micrometers. In some cases, the ESL 104 may include silicon nitride (Si x N y ) etc. In other embodiments, the ESL 104 includes silicon oxide (SiO), silicon oxynitride (SiO x Ny ), silicon carbonitride (SiCN), silicon oxycarbide (SiOC), silicon carbide (SiC), silicon oxycarbonitride (SiOCN), chromium oxide (CrO), or a combination of the foregoing.

[0051] In various cases, after deposition, the ESL 104 is partially removed from the top surface of the TM layer 102, for example, using a mask and a subsequent etching process or by thinning. In some embodiments, the thickness of the remaining etch stop layer 104 above the ILD layer 101 is in the range of about 10 nanometers to about 300 nanometers, and in other cases, in the range of about 50 nanometers to about 100 nanometers.

[0052] refer to Figure 1E In various embodiments, a first protective layer 106 is then deposited and disposed above the etch stop layer 104. In some cases, the first protective layer 106 is composed of a glass-like material, such as undoped silicate glass (USG), etc. However, the material of the first protective layer 106 is not limited thereto and may include silicon oxide, silicon-doped glass, or any other suitable material. Various insulating materials that provide sufficient support strength and a low roughness top surface are also used in various embodiments. In some embodiments, the first protective layer 106 is formed by two or more separately deposited, coextensive layers of similar materials to accommodate intermediate structures disposed therebetween. In some embodiments, the combined thickness of one or more layers of the first protective layer 106 is between about 0.1 micrometers (μm) and about 2 μm, and in other embodiments between about 0.8 μm and about 1.2 μm.

[0053] In some embodiments, an intermediate metal insulator metal (MIM) capacitor 108 is deposited between two layers of the first protective layer 106. The MIM capacitor 108 is a type of fabricated capacitor. In various embodiments, the MIM capacitor 108 includes at least two terminals or conductive plates, each separated by a dielectric insulating layer. In various embodiments, the MIM capacitor 108 can be used to store potential energy, voltage regulation, and / or mitigate noise on wires.

[0054] In various embodiments, the MIM capacitor 108 includes a bottom terminal (not shown) and a top terminal (not shown) with an insulating layer disposed therebetween. In some embodiments, the material of the bottom terminal and the top terminal includes a conductive material such as titanium nitride (TiN), titanium (Ti), aluminum (Al), indium tin oxide (ITO), tungsten (W), tungsten nitride (WN), tantalum nitride (TaN), tantalum (Ta), rhenium trioxide (ReO 3), rhenium oxide (ReO 2 ), iridium oxide (IrO 2 ), ruthenium (Ru), osmium (Os), palladium (Pd), platinum (Pt), copper (Cu), molybdenum nitride (MoN), molybdenum (Mo), other conductive metals or combinations thereof. In some embodiments, the thickness of the bottom terminal and the top terminal is between about 1 nanometer (nm) and about 1 micrometer, but the disclosure is not limited thereto. In some embodiments, the bottom terminal and the top terminal both include at least one common overlapping portion, thereby forming a capacitor in the capacitor region of the semiconductor device 100.

[0055] In some embodiments, the MIM capacitor 108 also includes a high-k dielectric layer that separates the bottom terminal from the top terminal. In some embodiments, the high-k dielectric layer provides a separation spacing between each of these terminals. In some embodiments, the separation spacing between adjacent terminals within the capacitor region is between about 1 nm and about 1 μm, depending on the thickness of the high-k dielectric layer. In some embodiments, the high-k dielectric layer includes aluminum oxide (Al2O3). x O y )、Zirconium oxide (Zr x O y ), silicon nitride (Si x N y ), Tantalum Nitride (Ta x O y ), titanium oxide (Ti x O y ), strontium titanate (Sr x Ti y O z ), yttrium oxide (Y x O y ), lanthanum oxide (La x O y ), Hafnium Oxide (Hf x O y ) or at least one of a multilayer structure of a combination of the foregoing.

[0056] In some embodiments, the MIM capacitor 108 includes one or more additional terminals and an insulating layer disposed between the bottom terminal and the top terminal, and / or an insulating layer above or below both, and in some embodiments, the terminals of one or more of the MIM capacitors 108 are interconnected or isolated from the electrical contacts. It should be noted that if the total number of terminals is greater than two, the configuration of the MIM capacitor 108 may vary accordingly. In some embodiments where the MIM capacitor 108 has at least three terminals, fewer than all of the terminals are simultaneously connected to the electrical contacts.

[0057] Now refer to Figure 1FIn various embodiments, one or more terminals of the MIM capacitor 108 are connected to one or more of the TM layer 102 and the redistribution layer (RDL) 114 (described later below) through a metal (i.e., aluminum) pad (not shown), through an intermediate redistribution via hole (RV) 110 having a contact metal deposited and disposed therein, as described in detail later below. In various embodiments, the RV 110 extends through the first protection layer 106 and a portion of the MIM capacitor 108 for electrically connecting the TM layer 102 to the MIM capacitor 108 using the contact metal disposed within the RV 110. In some embodiments, the RV 110 has a height between about 0.1 microns and about 2 microns, depending on design requirements and the height of the first protection layer 106. In some embodiments, the RV 110 has a width of about 1 micron to about 10 microns, depending on design requirements.

[0058] In various embodiments, the RV 110 is formed by etching through a portion of the first protection layer 106 and the MIM capacitor 108 to create a continuous opening extending from the top surface of the first protection layer 106 to the top surface of the TM layer 102, as shown in FIG. Figure 1F In some cases, the RV 110 extends through the first protective layer 106 and tapers linearly from the top surface of the first protective layer 106 toward the top surface of the TM layer 102 , as shown in the cross section in the figure.

[0059] Reference to Figure 1G , a barrier layer 112 is deposited and provided over the first protective layer 106 and within the RV 110. In some embodiments, the barrier layer 112 is provided to prevent damage caused by subsequent manufacturing operations by preventing metal from diffusing into underlying layers of the semiconductor device 100. In some cases, the barrier layer is made of titanium (Ti), titanium nitride (TiN), or a combination thereof. x N y ), tantalum (Ta), tantalum nitride (TaN), etc., and can be formed by chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), etc. In some embodiments, the barrier layer 112 has a thickness between 1 nm and 100 nm.

[0060] In various embodiments, a metal seed layer 113 is then deposited and provided over the barrier layer 112. In some embodiments, the metal seed layer 113 is provided to prevent contact metal from migrating between the TM layer 102 and a subsequently deposited metal as described in various embodiments herein. In some embodiments, the metal seed layer 113 is composed of copper. In some cases, the copper content of the metal seed layer 113 is less than the copper content of a metal layer subsequently deposited thereover, as described later herein. In some cases, the metal seed layer 113 is omitted.

[0061] As previously described, in various cases, RV 110 is formed to electrically connect MIM capacitor 108 and TM layer 102. Figure 1H In various embodiments, this is achieved by depositing a contact metal (e.g., metal RDL 114) within RV 110 on metal seed layer 113. In some embodiments, metal RDL 114 is composed of at least one conductive material, such as one or more of aluminum (Al), copper (Cu), aluminum copper (AlCu), gold (Au), tungsten (W), iron (Fe), titanium (Ti), tantalum (Ta), cobalt (Co), tin (Sn), and germanium (Ge), which provide sufficient conductivity at different material costs. In various embodiments, one or more of CVD, PVD, and electrochemical plating (ECP) are used to deposit the conductive material within or around RV 110.

[0062] A metal RDL 114 within the RV 110 is disposed through the first protection layer 106 including the MIM capacitor 108 to provide electrical contact with the underlying TM layer 102. In some embodiments, the RDL 114 is deposited and disposed on the top surface of the protection layer 106 by CVD, ECP, or PVD. In some embodiments, the RDL 114 over the first protection layer 106 has a thickness between about 1 micron and about 5 microns. In some embodiments, the RDL 114 has a width / space (W / S) ratio between about 1 μm / 1 μm and about 10 μm / 10 μm.

[0063] In various embodiments, the RDL 114 is deposited as a single continuous layer over the protective layer 106. In other cases, the RDL 114 is formed from a series of layers and deposition processes. In various cases, the RDL 114 is then etched at different locations to form one or more trenches (not shown) that provide electrical isolation according to design requirements, while other portions of the RDL 114 remain unetched.

[0064] In various cases, the top surface of RDL 114 is rounded. In some embodiments, the rounded top surface of metal RDL 114 is formed by straining of the first protective layer 106 below. In some embodiments, the rounded shape is formed by mask layer trimming. In some embodiments, the rounded shape is adjusted by a curing process. In some cases, the top surface is not rounded.

[0065] As the process geometries required in manufacturing become smaller, more defects (e.g., voids) are generated around the sidewalls of the RDL 114 and between the final structures of the semiconductor device 100. The voids and kinks weaken the mechanical strength of the semiconductor device 100 and are easily filled in subsequent deposition processes, which in some cases changes the electrical characteristics of the RDL 114. Therefore, the production yield of batch semiconductor devices 100 is sensitive to the formation of such defects.

[0066] To avoid such failures, in various embodiments, the process of forming the remaining layers of the semiconductor device 100 reduces the residual stress during subsequent film deposition, curing, and cooling. Since the chances of generating kinks and voids are reduced, the process window of the semiconductor device 100 is expanded and becomes more robust without significantly complicating the manufacture of the semiconductor device 100.

[0067] Figure 2A and Figure 2B 1 is a cross-sectional view of a subsequent stage of a sequential fabrication process of a semiconductor device 100 according to various embodiments. Figure 2A In various embodiments, silicon nitride (Si 2 N 2 ) is disposed and deposited above the metal RDL 114 and above the top surface of the first protection layer 106. x N y ) layer 116 (sometimes referred to as a second protective layer). In various cases, silicon nitride layer 116 includes more than one coextensive capping layer, for example, silicon nitride layer 116a is deposited before silicon nitride layer 116. In some embodiments, the various layers of silicon nitride layer 116 are composed of similar materials, including the materials described above. In some cases, silicon nitride layer 116 is composed of a first layer having a thickness between about 0.1 nm and about 10 μm and a second layer having a thickness between about 0.1 nm and about 10 μm. In some embodiments, the top surface of silicon nitride layer 116 is smoothed by a planarization process or the like to avoid additional stress caused by voids.

[0068] Reference Figure 2BIn various cases, a polyimide layer 118 is then deposited over the silicon nitride layer 116. In some embodiments, the thickness of the polyimide layer 118 disposed over the silicon nitride layer 116 and the metal RDL 114 does not exceed about 4 μm to reduce stress on these underlying layers. In some embodiments, the thickness of the remaining polyimide layer 118 disposed alone over the silicon nitride layer 116 is substantially greater than 4 μm.

[0069] In various embodiments, the design requirements of the semiconductor device 100 will require that the metal RDL 114 be connected to additional semiconductor device components. In many cases, this is achieved by adding metal bumps or other conductive connections that extend to the metal RDL 114 through openings in the polyimide layer 118 and the silicon nitride layer 116 overlying the metal RDL 114. It has been determined through experimentation and practice that when the inner corners of the openings in the polyimide layer 118 and the underlying silicon nitride layer 116 are too shallow, stress may be induced on subsequent metal bump layers, etc., deposited within these openings. Therefore, the following operations have been introduced into the manufacturing process of the semiconductor device 100.

[0070] Figure 3A , Figure 3B and Figure 3C is a cross-sectional view of a further subsequent stage of a sequential manufacturing process of the semiconductor device 100 according to various embodiments. Figure 3A , the opening 120 in the polyimide layer over a portion of the metal RDL 114 is formed by an etching process or by a sequential coating development and curing process followed by a plasma desmear process. In various cases, the plasma desmear process is performed to remove residues left by the patterning process. For example, the plasma desmear process may be performed using a CHF-containing 3 In some cases, a plasma process containing NF 3 In various embodiments, the use of the process gas causes lateral etching until a bottom inner angle obtained at the edge of the opening 120 in the polyimide layer 118 is much greater than 60 degrees, such as 75 degrees to 85 degrees, such as 79 degrees. In some embodiments, the top inner angle of the opening 120 in the polyimide layer 118 at the top edge is much greater than 135 degrees, such as 160 degrees to 170 degrees from the horizontal plane. In some cases, one or more such plasma desmear etching operations are performed until the desired design requirements are achieved. The plasma desmear operation achieves excellent definition of the bottom inner angles at the junctions of the silicon nitride layer 116 and the polyimide layer 118 with the opening 122 and the opening 120, respectively.

[0071] Reference Figure 3B, an etching process is performed to form an opening 122 in the silicon nitride layer 116, the opening 122 being substantially coextensive with the opening 120. In order to reduce stress on the top surface thereof, subsequent cracks formed therein, or delamination of additional layers, in various embodiments, the opening 122 is formed such that the bottom inner angle of the edge of the opening 122 in the silicon nitride layer 116 is much greater than 28 degrees, such as between 75 degrees and 85 degrees, such as 77 degrees. In various embodiments, the edge of the opening 122 is substantially flush with the edge of the opening 120.

[0072] Reference Figure 3C In various embodiments, a pull-back process is performed to widen the opening 120 to form an opening 124 having a wider width or critical dimension (CD) than the opening 122, thereby exposing a portion of the top surface of the silicon nitride layer 116 located below the opening 124. In some embodiments, the pull-back process uses plasma or wet etching to expand the opening 120 to form a wider opening 124. In some cases, a hard mask is used to maintain the upper and lower inner angles of the exposed edge of the polyimide layer 118. In various embodiments, the pull-back process extends the width of the polyimide opening 124 to be much greater than 0.45 μm, such as between 0.55 microns and 0.65 microns, such as 0.6 microns. In various embodiments, the radius or maximum width of the opening 124 is at least 0.6 microns greater than the width of the opening 122, and the diameter of the opening 124 is at least 1.2 microns greater than the diameter of the opening 122.

[0073] Figure 4A and Figure 4B is a cross-sectional view of further stages of an exemplary sequential manufacturing process of the semiconductor device 100 according to various embodiments. Figure 4A In various cases, a metal bump layer 140 is formed in the opening 124 and the opening 122 above the metal RDL 114. In some embodiments, the metal bump layer 140 is composed of a conductive metal such as copper, although the metal RDL 114 can also use other expected conductive materials. In some embodiments, the metal bump layer 140 provides electrical contact between the metal RDL 114, the MIM capacitor layer 108 and the TM layer 102 and other external electrical components on or outside the wafer 10. In various embodiments, the metal bump layer 140 intersects the polyimide layer 118 and the silicon nitride layer 116 at its edge in the opening passing through these layers. In various cases, the metal bump layer 140 extends above the silicon nitride layer 116 and the polyimide layer 118 to achieve such electrical connection. In some cases, the metal bump layer 140 is a single continuous layer. In other cases, the metal bump layer 140 is formed by a series of deposition layers (not shown).

[0074] Over time, the top exposed surface 150 of the silicon nitride layer 116 induces stress on the metal bump layer 140. By forming the exposed edge of the silicon nitride layer 116 such that its bottom internal angle 162 is between about 75 degrees and about 85 degrees, such as 77 degrees, the stress induced at the top exposed surface 150 has been determined to be reduced, thereby reducing the formation of kinks and voids. By forming the exposed edge of the polyimide layer 118 such that the bottom internal angle 172 of the polyimide layer 118 is between about 60 degrees and about 85 degrees (e.g., 79 degrees), and such that the top internal angle 174 of the polyimide layer 118 is between about 160 degrees and about 170 degrees (e.g., 165 degrees), the stress induced at the top exposed surface 150 has been determined to be reduced, such that the formation of kinks and voids and the possibility of delamination or cracking of the metal bump layer 140 are reduced.

[0075] Reference Figure 4B In various embodiments, the relationship between the interior angles 162 , 172 , and 174 is shown with respect to the polyimide layer 118 , the underlying silicon nitride layer 116 , the metal RDL 114 , and the metal bump layer 140 .

[0076] Figure 5 is a flow chart of an exemplary sequential manufacturing process 500 of a semiconductor device 100 according to various non-limiting embodiments. At operation 502, a wafer, such as wafer 10, is provided. Next, at operation 504, an ILD 101 is provided and disposed over the wafer 10. Next, at operation 506, a TM layer 102 is deposited toward the top surface of the ILD 101, and a planarization process may be performed to smooth the top surface of the ILD 101 and to substantially smooth the top surface of the TM layer 102. Next, at operation 508, a protective layer 106 is provided and disposed on top of the ILD 101 and the TM layer 102. Next, at operation 510, a MIM capacitor layer 108 is formed over the protective layer 106, and another protective layer 106 is provided and disposed over the MIM capacitor layer 108. Next, at operation 512, etching is performed to create vias through the protective layer 106 and the MIM capacitor layer 108. Next, at operation 514, a barrier layer 112 is provided and disposed within the via and over the top surface of the protection layer 106. Subsequently, at operation 516, a metal seed layer 113 is provided and disposed over the barrier layer 112.

[0077] Continuing with operation 518, a metal RDL 114 is provided within the via and over the metal seed layer 113. Next, at operation 520, a silicon nitride layer 116 is provided over the metal RDL 114. In a subsequent operation 522, a polyimide layer 118 is provided and disposed over the silicon nitride layer 116, wherein the polyimide layer 118 has an opening 120 therein. At operation 524, a plasma desmear process is performed to adjust the profile of the opening 120 in the polyimide layer 118 over the metal RDL 114. At operation 526, an etching process is performed to create an opening 122 in the silicon nitride layer 116 over the metal RDL 114 and under the opening 120. At operation 528, a pull-back process is performed to laterally etch the polyimide layer 118 using plasma or gas to create a widened opening 124. Finally, at operation 530, a metal bump layer 140 is provided and disposed over the exposed metal RDL 114 to provide electrical connections to the semiconductor device 100 and other electronic components. The process 500 may be repeated for other portions of the wafer 10 or additional wafers 10 in a large-scale manufacturing operation.

[0078] Figure 6 is a top view 600 of a layout of multiple copies of the semiconductor device 100 according to some embodiments, depicting various TM layers 102 and metal bump layers 140 in relation to each other. A portion of the cross-section line XX is shown corresponding to the cross-sections shown in the previous figures.

[0079] In various embodiments, computer simulations predict the stresses generated by increased internal angles of openings in polyimide and silicon nitride layers over existing manufacturing techniques. The present disclosure introduces methods and apparatus for manufacturing a semiconductor device 100 that improves the relief of underlying stresses that are typically caused by kinks and voids resulting from high stress areas of the structure. The solutions described herein have little impact or change to existing manufacturing processes and are beneficial for improving device yields. Although primarily described with respect to capacitor devices, the solutions herein may also be used to manufacture other similar semiconductor devices.

[0080] According to various embodiments, a method of forming a semiconductor device includes: (i) forming a metal redistribution layer (RDL) in a through hole of a first protection layer disposed above a wafer; (ii) depositing a second protection layer above a portion of the metal RDL; (iii) depositing a polyimide layer above the second protection layer; (iv) performing a plasma desmear etching operation to etch a first opening through the polyimide layer to expose a portion of the second protection layer above the metal RDL; and (v) etching a portion of the second protection layer exposed in the first opening to form a second opening leading to the metal RDL, such that a vertical cross-section of the second protection layer at the second opening has a bottom angle of between about 75 degrees and 85 degrees to a horizontal plane. In some embodiments, the method further includes performing a pull-back operation of the polyimide layer to expose a top surface of a second portion of the second protection layer, such that a vertical cross-section of the polyimide layer at the first opening has a top angle or an upper angle of 160 degrees to 170 degrees to a horizontal plane, and has a bottom angle of between 75 degrees and 85 degrees to a horizontal plane. In some embodiments, the method further includes performing a pullback operation until the width of the first opening is at least 1.2 microns greater than the diameter of the second opening. In some embodiments, the method further includes performing a pullback operation until the radius of the first opening is at least 0.6 microns greater than the diameter of the second opening. In some embodiments, the method further includes depositing a metal bump layer over the metal RDL, the first opening, and the second opening. In some embodiments, the method further includes depositing a first protective layer over the wafer, forming a packaged metal insulator metal (MIM) capacitor layer in the first protective layer, and forming a through hole by etching through the first protective layer and the MIM capacitor layer. In some embodiments, the method further includes depositing a barrier layer over the first protective layer and in the through hole. In some embodiments, the method further includes depositing a metal seed layer over the barrier layer. In some embodiments, the method further includes depositing an interlayer dielectric (ILD) over the top surface of the wafer, depositing a top metal layer in a portion of the ILD, and depositing a first protective layer over the top metal layer and the ILD. In some embodiments, the method further includes depositing an etch stop layer over the top surface of the ILD and the top metal layer before depositing the first protective layer, and depositing the first protective layer over the etch stop layer. In some embodiments, the method further comprises exposing the polyimide layer within the first opening to nitrogen trifluoride (NF 3 )gas.

[0081] According to various embodiments, a method of forming a semiconductor device includes: (i) providing a protective layer over a metal contact; (ii) providing a metal insulator metal (MIM) capacitor layer within the protective layer; (iii) providing a redistribution layer (RDL) extending through the protective layer and a portion of the MIM capacitor layer; (iv) providing a silicon nitride layer over a portion of the RDL; (v) providing a polyimide layer over the silicon nitride layer; and (vi) providing a metal bump layer extending through the silicon nitride layer and the polyimide layer and contacting the RDL, the metal bump layer extending through the silicon nitride layer and the polyimide layer and contacting the RDL, wherein an inner bottom angle at an intersection of the metal bump layer and the polyimide layer is between 60 degrees and 85 degrees. In some embodiments, the method further includes providing a first vertically extending edge of the polyimide layer contacting the metal bump layer, the first vertically extending edge having a top angle between 160 degrees and 170 degrees and a bottom angle between 75 degrees and 85 degrees. In some embodiments, the method further includes providing a second vertically extending edge through the silicon nitride layer in contact with the metal bump layer, the second vertically extending edge having a bottom inner angle between 75 degrees and 85 degrees. In some embodiments, the method further includes providing a barrier layer above the protective layer and below the metal RDL. In some embodiments, the method further includes providing a metal seed layer between the barrier layer and the metal RDL. In some embodiments, the method further includes providing a metal bump layer through the silicon nitride layer and the polyimide layer and in contact with the metal RDL.

[0082] According to various embodiments, a semiconductor device includes a protective layer disposed over a metal contact layer of a wafer, a packaged metal insulator metal (MIM) capacitor layer disposed within the protective layer, and a metal redistribution layer (RDL) disposed over a portion of a top surface of the protective layer and extending through the MIM capacitor layer. In various embodiments, the device further includes a silicon nitride (SiN) layer disposed over a portion of the metal RDL, the SiN layer having an inner bottom angle between 75 degrees and 85 degrees at a first opening. In various embodiments, the device further includes a polyimide layer disposed over the SiN layer, the polyimide layer having a second opening at least partially disposed over the first opening leading to the metal RDL, wherein a cross-section of the polyimide layer has a top angle between 160 degrees and 170 degrees at the second opening, and a bottom angle between 75 degrees and 85 degrees. In some embodiments, the vertical thickness of the polyimide layer over the metal RDL is less than 4 microns. In some embodiments, the diameter of the second opening is at least 1.2 microns greater than the diameter of the first opening.

[0083] According to various embodiments, a semiconductor device includes a first protective layer, a metal redistribution layer (RDL), a second protective layer, and a polyimide layer. The first protective layer is disposed above the metal contact. The metal redistribution layer (RDL) is disposed above a portion of the first protective layer. The second protective layer is disposed above a portion of the metal RDL, and the second protective layer has a first opening. The polyimide layer is disposed above the second protective layer, and the polyimide layer has a second opening. Wherein, a vertical cross-section of the second protective layer at the first opening has an inner bottom angle between 75 degrees and 85 degrees, and a vertical cross-section of the polyimide layer at the second opening has a top angle and a bottom angle, the top angle is between 160 degrees and 170 degrees, and the bottom angle is between 75 and 85 degrees.

[0084] According to various embodiments, a semiconductor device has an improved layer opening for supporting a metal bump, the semiconductor device comprising a metal contact, a protective layer, a metal insulator metal (MIM) capacitor layer, a redistribution layer (RDL), a silicon nitride layer, a polyimide layer, and a metal bump layer. The protective layer is disposed above the metal contact. The metal insulator metal capacitor layer is disposed within the protective layer. The redistribution layer extends through a portion of the protective layer and the MIM capacitor layer. The silicon nitride layer is disposed above a portion of the RDL. The polyimide layer is disposed above the silicon nitride layer. The metal bump layer extends through the silicon nitride layer and the polyimide layer and contacts the RDL, wherein the inner bottom angle at the intersection of the metal bump layer and the polyimide layer is between 60 degrees and 85 degrees.

[0085] According to various embodiments, a semiconductor device includes a protection layer disposed over a metal contact layer of a wafer; a metal redistribution layer (RDL) disposed over a portion of a top surface of the protection layer; a silicon nitride (SiN) layer disposed over a portion of the metal RDL, the SiN layer having a first opening leading to a top of the metal RDL, wherein a cross-section of the SiN layer has an inner bottom angle between 75 degrees and 85 degrees at the first opening; and a polyimide layer disposed over the SiN layer, the polyimide layer having a second opening at least partially disposed over the first opening leading to the metal RDL, wherein a cross-section of the polyimide layer at the second opening has a top angle between 160 degrees and 170 degrees, and a bottom angle between 75 degrees and 85 degrees.

[0086] In some embodiments, the width of the second opening is at least 1.2 microns greater than the diameter of the first opening. In some embodiments, the radius of the second opening is at least 0.6 microns greater than the diameter of the first opening. In some embodiments, the semiconductor device further includes a metal bump layer, which is disposed above the metal RDL, the first opening, and the second opening. In some embodiments, the semiconductor device further includes a metal insulator metal (MIM) capacitor layer disposed in the first protective layer. In some embodiments, the semiconductor device further includes a barrier layer disposed above the first protective layer. In some embodiments, the semiconductor device further includes an interlayer dielectric (IDL), a top metal layer, and a first protective layer, the interlayer dielectric being disposed on the top surface of the wafer, and the top metal layer being disposed in a portion of the IDL. The first protective layer is disposed above the top metal layer and the IDL. In some embodiments, the vertical thickness of the polyimide layer above the metal RDL is less than 4 microns.

[0087] The foregoing summarizes the features of several embodiments so that those skilled in the art can better understand the various aspects of the present disclosure. It should be understood by those skilled in the art that they can easily use the present disclosure as a basis to design or modify other processes and structures to perform the same purpose and / or achieve the same advantages of the embodiments described herein. It should also be recognized by those skilled in the art that such equivalent structures do not depart from the spirit and scope of the present disclosure, and various modifications, substitutions and changes may be made herein without departing from the spirit and scope of the present disclosure.

Claims

1. A semiconductor device, characterized in that: Include: a first protective layer disposed above a metal contact; a metal redistribution layer disposed above a portion of the first protection layer; a second protection layer disposed above a portion of the metal redistribution layer, and the second protection layer has a first opening; as well as A polyimide layer is disposed on the second protective layer, and the polyimide layer has a second opening; Among them, a vertical cross-section of the second protective layer at the first opening has an inner bottom angle between 75 degrees and 85 degrees, and a vertical cross-section of the polyimide layer at the second opening has a top angle and a bottom angle, the top angle is between 160 degrees and 170 degrees, and the bottom angle is between 75 and 85 degrees.

2. The semiconductor device according to claim 1, wherein Also includes: A metal-insulator-metal capacitor layer is disposed in the first protection layer.

3. The semiconductor device according to claim 2, wherein: Also includes: A barrier layer is disposed on the first protection layer.

4. The semiconductor device according to claim 1, wherein: Also includes: an interlayer dielectric disposed on a top surface of a wafer; a top metal layer disposed within a portion of the interlayer dielectric; and The first protection layer is disposed above the top metal layer and the interlayer dielectric.

5. A semiconductor device, characterized in that: Include: a protective layer disposed on a metal contact layer of a wafer; a metal redistribution layer disposed over a portion of a top surface of the protection layer; a silicon nitride layer disposed above a portion of the metal redistribution layer, the silicon nitride layer having a first opening leading to a top of the metal redistribution layer, wherein a cross section of the silicon nitride layer has an inner bottom angle between 75 degrees and 85 degrees at the first opening; as well as A polyimide layer is disposed above the silicon nitride layer, the polyimide layer having a second opening at least partially disposed above the first opening leading to the metal redistribution layer, wherein a cross-section of the polyimide layer at the second opening has a top angle between 160 degrees and 170 degrees, and a bottom angle between 75 degrees and 85 degrees.

6. The semiconductor device according to claim 1 or 5, wherein: A width of the second opening is at least 1.2 micrometers greater than a diameter of the first opening.

7. The semiconductor device according to claim 1 or 5, wherein: A radius of the second opening is at least 0.6 micrometers greater than a diameter of the first opening.

8. The semiconductor device according to claim 1 or 5, wherein: Also includes: A metal bump layer is disposed above the metal redistribution layer, the first opening and the second opening.

9. The semiconductor device according to claim 1 or 5, wherein: A vertical thickness of the polyimide layer above the metal redistribution layer is less than 4 micrometers.

10. A semiconductor device, characterized in that: The semiconductor device has an improved layer opening for supporting a metal bump, and the semiconductor device comprises:

1. Metal contact; a protective layer disposed above the metal contact; A metal-insulator-metal capacitor layer is disposed in the protective layer; a redistribution layer extending through the protection layer and a portion of the metal-insulator-metal capacitor layer; a silicon nitride layer disposed over a portion of the redistribution layer; a polyimide layer disposed on the silicon nitride layer; as well as A metal bump layer extends through the silicon nitride layer and the polyimide layer and contacts the redistribution layer, wherein an inner bottom angle of an intersection of the metal bump layer and the polyimide layer is between 60 degrees and 85 degrees.

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