Reset circuit, reset device and microcomputer system
By designing a reset circuit including a power supply interface unit and a reset signal generation unit, the combination of capacitor and diode is used to solve the problem of unstable reset pulse in a strong interference environment, and the anti-interference and stability of the reset circuit are achieved.
Patent Information
- Application Number
- CN202420967926.7
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-05-07
- Publication Date
- 2025-03-28
- Estimated Expiration
- 2034-05-07
AI Technical Summary
The existing reset circuit may have unstable reset pulses in a strong interference environment or when the power supply is temporarily interrupted, which will affect the operation of the microcontroller, resulting in crashes, program runs off or control failure.
A reset circuit is designed, including a power supply interface unit and a reset signal generation unit. Through the combination of the first capacitor, the second capacitor, the first diode, the second diode and the first transistor, a stable low-level reset signal is generated at the moment of power-on, and a voltage is prevented from existing at both ends of the capacitor when the power supply is powered down, ensuring the stability of the reset circuit.
The stability of reset pulses is achieved in a strong interference environment and a short interruption of the power supply, avoiding the problems of microcontroller crash, program runs off or control failure, and improving the anti-interference of the reset circuit.
Smart Images
Figure CN222691715U_ABST
Abstract
Description
Technical Field
[0001] The utility model belongs to the technical field of reset circuits, and more specifically, relates to a reset circuit, a reset device and a microcomputer system. Background Art
[0002] In order to ensure that the circuits of microcomputer system products can work stably and reliably, the microcontroller reset circuit is an indispensable part of the microcomputer system products. The performance of the reset circuit will directly affect the stability of the entire microcomputer system.
[0003] The first function of the microcontroller reset circuit is power-on reset. Since the circuit of the microcomputer system product is a sequential digital circuit, and the sequential digital circuit requires a stable clock signal to work stably and reliably, when the power of the microcomputer system product is powered on, it is necessary to wait until the clock signal is stable before the reset signal of the microcontroller reset circuit is removed and the microcomputer system product starts to work normally. At present, the conventional reset circuit uses the characteristic that the voltage across the capacitor cannot change suddenly, and combines the resistor to form an RC charge and discharge circuit to provide a short low-level reset pulse for the microcontroller.
[0004] However, in actual applications, conventional reset circuits may have unstable reset pulses in strong interference environments or when the power supply is briefly interrupted, which will affect the operation of the microcontroller and cause the microcontroller to freeze, run away, or fail to control. Utility Model Content
[0005] The embodiment of the utility model provides a reset circuit, a reset device and a microcomputer system to solve the problem of unstable reset of the current reset circuit.
[0006] In a first aspect, an embodiment of the present utility model provides a reset circuit for providing a reset signal to a processor, including a power interface unit and a reset signal generating unit;
[0007] The reset signal generating unit includes a first resistor, a second resistor, a third resistor, a first capacitor, a second capacitor, a first diode, a second diode and a first transistor, the cathode of the first diode and the first end of the second resistor are both connected to the power interface unit, the anode of the first diode and the second end of the second resistor are both connected to the collector of the first transistor and the first end of the third resistor, the second end of the third resistor is connected to the first end of the second capacitor and serves as the output end of the reset signal generating unit, the first end of the first capacitor is connected to the power interface unit, the second end of the first capacitor is respectively connected to the first end of the first resistor and the cathode of the second diode, the second end of the first resistor is connected to the base of the first transistor, the emitter of the first transistor is connected to the anode of the second diode and the second end of the second capacitor and then grounded;
[0008] The reset signal generating unit is used to generate a low level output at the moment when the power interface unit is connected to the voltage, and to generate a reset pulse when the voltage fluctuates.
[0009] In a possible implementation, the reset signal generating unit further includes a fourth resistor, a first end of the fourth resistor is respectively connected to the second end of the first resistor and the base of the first transistor, and a second end of the fourth resistor is grounded.
[0010] In a possible implementation, the resistance value of the first resistor and the resistance value of the second resistor are both greater than the resistance value of the third resistor; and the capacitance value of the first capacitor is greater than the capacitance value of the second capacitor.
[0011] In a possible implementation manner, a resistance value of the first resistor is smaller than a resistance value of the fourth resistor.
[0012] In a possible implementation manner, the first transistor is an NPN transistor.
[0013] In a possible implementation, the processor is a system-on-chip.
[0014] In a possible implementation, the processor is a single chip microcomputer.
[0015] In a possible implementation, the voltage input to the power interface unit is in the range of 3.3-5V.
[0016] In a second aspect, an embodiment of the present invention provides a reset device, the reset device comprising the reset circuit of any one of the first aspect.
[0017] In a third aspect, an embodiment of the present utility model provides a microcomputer system, the microcomputer system comprising the reset device of the second aspect.
[0018] The embodiment of the utility model provides a reset circuit, a reset device and a microcomputer system. At the moment when the power interface unit is connected to the voltage, the collector potential of the first transistor is pulled down, so that the output terminal RESET of the reset signal generating unit can be ensured to be at a low level. When the voltage across the first capacitor is saturated, the first transistor is cut off, so as to ensure that RESET always maintains a low level at the moment of power-on, and reset is completed by charging the second capacitor. At the moment when the power interface unit loses power, the second capacitor is discharged by the first diode, and the first capacitor is discharged by the second diode, so as to prevent the failure of the reset circuit caused by the voltage across the first capacitor or the second capacitor when power is on. Furthermore, it can be ensured that a stable low-level output is maintained at the moment of power-on, and a reset pulse can be effectively generated when the voltage fluctuates. The reset circuit provided by the utility model has strong anti-interference performance and a stable reset pulse. BRIEF DESCRIPTION OF THE DRAWINGS
[0019] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative labor.
[0020] Figure 1 This is a structural diagram of a commonly used reset circuit;
[0021] Figure 2 A circuit diagram of a reset circuit provided by an embodiment of the utility model;
[0022] Figure 3 A circuit diagram of another reset circuit provided by an embodiment of the utility model;
[0023] Figure 4 A schematic diagram of the structure of a reset device provided by an embodiment of the utility model;
[0024] Figure 5 A schematic structural diagram of a microcomputer system provided in an embodiment of the utility model. DETAILED DESCRIPTION
[0025] In order to enable people in the technical field to better understand the present solution, the technical solution in the embodiment of the present solution will be clearly described below in conjunction with the drawings in the embodiment of the present solution. Obviously, the described embodiment is an embodiment of a part of the present solution, not all of the embodiments. Based on the embodiments in the present solution, all other embodiments obtained by ordinary technicians in the field without creative work should fall within the scope of protection of the present solution.
[0026] The term "including" and any other variations in the specification and claims of this solution and the above drawings mean "including but not limited to", and is intended to cover non-exclusive inclusions and is not limited to the examples listed in the text. In addition, the terms "first" and "second" are used to distinguish different objects, not to describe a specific order.
[0027] The following is a detailed description of the implementation of the present invention in conjunction with the specific drawings:
[0028] As introduced in the background technology, Figure 1The schematic diagram of the commonly used RC reset circuit is shown in Figure 1. After the reset circuit is turned on, the power supply charges the capacitor C through the resistor R. The reset pin is at a low level when the power supply is connected. After a period of time, when the capacitor is fully charged, the reset pin level is at a high level. It can be seen that the RC reset circuit realizes the process of converting the reset pin from a low level to a high level through the capacitor charging process, that is, it gives a reset signal.
[0029] However, the reset circuit may have unstable reset pulses in a strong interference environment or when the power supply is briefly interrupted. For example, if there is a momentary voltage interruption and the charge on the capacitor cannot be completely discharged through R during the voltage interruption, the voltage across the capacitor cannot "return to zero", and a low-level reset pulse cannot be generated after power is turned on again.
[0030] In order to solve the problems existing in the prior art, the present invention provides a reset circuit, a reset device and a microcomputer system. The reset circuit provided by the embodiment of the present invention is first introduced below.
[0031] like Figure 2 As shown, a reset circuit is used to provide a reset signal to a processor 300, including a power interface unit 100 and a reset signal generating unit 200. The power interface unit 100 is used to access a power supply voltage for operation of the reset circuit or a charging voltage for charging. The reset signal generating unit 200 is used to generate a low-level output at the moment when the power interface unit 100 is connected to a voltage, and to generate a reset pulse when the voltage fluctuates.
[0032] Specifically, the reset signal generating unit 200 includes a first resistor R1, a second resistor R2, a third resistor R3, a first capacitor E1, a second capacitor E2, a first diode D1, a second diode D2 and a first transistor Q1. The cathode of the first diode D1 and the first end of the second resistor R2 are both connected to the power interface unit 100, the anode of the first diode D1 and the second end of the second resistor R2 are both connected to the collector of the first transistor Q1 and the first end of the third resistor R3, respectively, the second end of the third resistor R3 is connected to the first end of the second capacitor E2 and serves as the output end of the reset signal generating unit 200, the first end of the first capacitor E1 is connected to the power interface unit 100, the second end of the first capacitor E1 is respectively connected to the first end of the first resistor R1 and the cathode of the second diode D2, the second end of the first resistor R1 is connected to the base of the first transistor Q1, and the emitter of the first transistor Q1 is connected to the anode of the second diode D2 and the second end of the second capacitor E2 and then grounded.
[0033] In this embodiment, the resistance of the first resistor R1 and the resistance of the second resistor R2 are both greater than the resistance of the third resistor R3 , and the capacitance of the first capacitor E1 is greater than the capacitance of the second capacitor E2 .
[0034] Exemplarily, in order to ensure that RESET maintains a low level during the power stabilization time, the capacitance value of the first capacitor E1 ranges from 1 uF to 10 uF.
[0035] Exemplarily, the resistance of the first resistor R1 may be 8-12KΩ.
[0036] In some embodiments, the second resistor R2, the third resistor R3 and the second capacitor E2 determine the low level time of the reset pulse, which can be matched according to the type of the single chip microcomputer.
[0037] Exemplarily, the resistance of the third resistor R3 is less than 100Ω.
[0038] In addition, the charging time of the second resistor R2 and the second capacitor E2 should be able to meet the time requirement of the low level of the reset pulse.
[0039] Exemplarily, the value range of the second resistor R2 may be between 1KΩ and 10KΩ, and the value range of the capacitance value of the second capacitor E2 may be between 0.1uF and 10uF.
[0040] In some embodiments, the first transistor Q1 is an NPN transistor.
[0041] In some embodiments, the processor may be a system-on-chip or a single-chip microcomputer.
[0042] In this embodiment, when the single processor is a single chip microcomputer, the voltage range of the power interface unit can be 3.3-5V.
[0043] In some embodiments, Figure 3 As shown, in order to prevent the base of the first transistor Q1 from being disturbed and introducing current to cause malfunction, a fourth resistor R4 can be added to the reset signal generating unit 200. The first end of the fourth resistor R4 is respectively connected to the second end of the first resistor R1 and the base of the first transistor Q1, and the second end of the fourth resistor R4 is grounded.
[0044] In this embodiment, the resistance of the first resistor R1 is smaller than the resistance of the fourth resistor R4.
[0045] For example, the resistance of the first resistor R1 may be 8-12KΩ, and the resistance of the fourth resistor R4 may be 18-22KΩ. For example, the resistance of the first resistor R1 may be 10KΩ, and the resistance of the fourth resistor R4 may be 20KΩ.
[0046] The working principle of the reset circuit provided by the present invention at the moment when the power interface unit 100 is powered on is as follows:
[0047] At the moment the power interface unit 100 is powered on, the voltage across the first capacitor E1 cannot change suddenly. The power interface unit 100 provides a base drive current to the first transistor Q1 through the first resistor R1, so that the first transistor Q1 is turned on and the collector potential of the first transistor Q1 is pulled down.
[0048] When the collector of the first transistor Q1 is at a low level, the RESET terminal is grounded through the third resistor R3 and the second capacitor E2, thereby ensuring that the RESET terminal can be accurately pulled to a low level. At the same time, the third resistor R3 forms a discharge loop for the second capacitor E2 to ensure that the voltage across the second capacitor E2 "returns to zero".
[0049] In addition, the power interface unit 100 charges the first capacitor E1 through the first resistor R1 and the base of the first transistor Q1. When the voltage across the first capacitor E1 is saturated, no current flows through the first resistor, and the first transistor Q1 is cut off at this time. During this delay time, RESET always remains at a low level, and the voltage of the power interface unit 100 tends to be stable. The fourth resistor R4 serves as a base bias pull-down resistor of the first transistor Q1 to prevent the base of the first transistor Q1 from being interfered with and introducing current to cause malfunction.
[0050] When the first transistor Q1 is turned off, the voltage across the second capacitor E2 cannot change suddenly, and the power interface unit 100 charges the second capacitor E2 through the second resistor R2, the third resistor R3 and the second capacitor E2. The voltage across the second capacitor E2 gradually increases until it exceeds the reset threshold of the RESET terminal and reset is completed.
[0051] The second working principle at the moment of power failure of the power interface unit 100 is:
[0052] When the voltage of the power interface unit 100 is cut off, since the voltage across the first capacitor E1 cannot change suddenly, the second diode D2 is set to discharge the first capacitor E1. The discharge efficiency through the first capacitor E1 is higher than the discharge efficiency through the first resistor R1, so as to prevent the voltage across the first capacitor E1 from causing circuit failure when the power is turned on next time.
[0053] In addition, when the voltage of the power interface unit 100 is cut off, since the voltage across the second capacitor E2 cannot change suddenly, the first diode D1 is set to discharge the second capacitor E2. Discharging through the second capacitor E2 is more efficient than discharging through the second resistor R2. Since the resistance of the third resistor R3 is small, it can be ignored during discharge to prevent the voltage across the second capacitor E2 from causing circuit failure when the power is turned on next time.
[0054] The reset circuit provided by the present invention can ensure that the output terminal RESET of the reset signal generating unit is at a low level by lowering the collector potential of the first transistor at the moment when the power interface unit is connected to the voltage. When the voltage across the first capacitor is saturated, the first transistor is cut off, thereby ensuring that RESET always maintains a low level at the moment of power-on, and reset is completed by charging the second capacitor. At the moment when the power interface unit loses power, the second capacitor is discharged by the first diode, and the first capacitor is discharged by the second diode, thereby preventing the failure of the reset circuit caused by the voltage across the first capacitor or the second capacitor when power is on. Furthermore, it can ensure that a stable low-level output is maintained at the moment of power-on, and a reset pulse can be effectively generated when the voltage fluctuates. The reset circuit provided by the utility model has strong anti-interference performance and a stable reset pulse.
[0055] Second, Figure 4 It is a structural schematic diagram of a resetting device 4 according to an embodiment of the utility model.
[0056] like Figure 4 As shown, the reset device 4 includes the reset circuit in the first aspect embodiment. Through the above reset circuit, the reset action of the reset device can be made more reliable and stable, and can ensure a stable low-level output at the moment of power-on, and can effectively generate a reset pulse when the voltage fluctuates.
[0057] Figure 5 A schematic structural diagram of a microcomputer system 5 provided in an embodiment of the utility model.
[0058] The microcomputer system 5 includes the reset device 4 provided in the second aspect, which can ensure that the microcomputer system 5 works normally.
[0059] The above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that the technical solutions described in the aforementioned embodiments may still be modified, or some of the technical features may be replaced by equivalents. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present invention.
Claims
1. A reset circuit, characterized in that: Used to provide a reset signal to a processor, including a power interface unit and a reset signal generating unit; The reset signal generating unit comprises a first resistor, a second resistor, a third resistor, a first capacitor, a second capacitor, a first diode, a second diode and a first transistor, the cathode of the first diode and the first end of the second resistor are both connected to the power interface unit, the anode of the first diode and the second end of the second resistor are both connected to the collector of the first transistor and the first end of the third resistor, the second end of the third resistor is connected to the first end of the second capacitor and serves as the output end of the reset signal generating unit, the first end of the first capacitor is connected to the power interface unit, the second end of the first capacitor is respectively connected to the first end of the first resistor and the cathode of the second diode, the second end of the first resistor is connected to the base of the first transistor, the emitter of the first transistor is connected to the anode of the second diode and the second end of the second capacitor and then grounded; The reset signal generating unit is used to generate a low level output at the moment when the power interface unit is connected to a voltage, and to generate a reset pulse when the voltage fluctuates.
2. The reset circuit according to claim 1, characterized in that: The reset signal generating unit further includes a fourth resistor, a first end of the fourth resistor is respectively connected to the second end of the first resistor and the base of the first transistor, and a second end of the fourth resistor is grounded.
3. The reset circuit according to claim 1 or 2, characterized in that: The resistance value of the first resistor and the resistance value of the second resistor are both greater than the resistance value of the third resistor; the capacitance value of the first capacitor is greater than the capacitance value of the second capacitor.
4. The reset circuit according to claim 2, characterized in that: The resistance value of the first resistor is smaller than the resistance value of the fourth resistor.
5. The reset circuit according to claim 1, wherein: The first transistor is an NPN transistor.
6. The reset circuit according to claim 1, wherein: The processor is a system-on-chip.
7. The reset circuit according to claim 1, characterized in that: The processor is a single chip microcomputer.
8. The reset circuit according to claim 7, characterized in that: The voltage range of the power interface unit is 3.3-5V.
9. A resetting device, characterized in that: The reset device comprises the reset circuit according to any one of claims 1-8.
10. A microcomputer system, characterized in that: The microcomputer system includes the reset device according to claim 9.