IGBT (Insulated Gate Bipolar Translator) with optimized gate structure

Abstract

The utility model relates to an IGBT with an optimized gate structure, comprising a plurality of cells, each cell comprises a substrate, the surface of the substrate is provided with a gate trench and a plurality of first emitter trenches, the surface of the substrate is also provided with an emitter metal layer and a gate polysilicon layer, the gate trench is internally provided with a gate, the first emitter trench is internally provided with a first emission gate electrode, and the first emitter trench is internally provided with a second emission gate electrode. The grid electrode is connected with the grid polycrystalline silicon layer, the end portion of the first emitting grid electrode is connected with the emitting electrode metal layer, the surface of the substrate is further provided with a plurality of sets of second emitting electrode grooves and virtual grid electrode grooves which are arranged in a collinear mode, virtual grid electrodes are arranged in the virtual grid electrode grooves, and second emitting grid electrodes are arranged in the second emitting electrode grooves. One end of the second emission gate electrode is connected with the emission electrode metal layer through a contact hole, and one end of the virtual gate electrode is connected with the gate polycrystalline silicon layer. According to the IGBT with the optimized gate structure, the virtual gate can be continuously adjusted during design so as to optimize the device design.

Description

Technical Field

[0001] The utility model relates to the technical field of semiconductor devices, in particular to an IGBT with an optimized gate structure. Background Art

[0002] Trench IGBT still has a large application space in many power electronics fields due to its high current density and excellent compromise characteristics.

[0003] Existing trench IGBTs, such as the IGBT disclosed in the Chinese patent with publication number "CN111211168A" and titled "A RC-IGBT chip and its manufacturing method", include gate trenches, virtual gate trenches and emitter trenches, wherein a gate is provided in the gate trench, which is used to realize the conventional gate function, and an emitter gate is provided in the emitter trench, which is used to improve the reverse recovery, switching speed and other characteristics of the device, thereby improving the overall performance of the device. Usually, IGBTs with gate trenches and emitter trenches often generate high-frequency oscillations during the switching process of the IGBT due to too little gate charge or too small gate capacitance. The virtual gate in the virtual gate trench can be used to increase the gate capacitance and device stability. The trench IGBT has its gate and virtual gate directly connected to the gate bus at both ends, thereby realizing the corresponding functions.

[0004] IGBTs with this structure mainly have the following problems.

[0005] In existing trench IGBTs, the virtual gate and effective trench gate are generally perpendicular to the gate busbar and evenly arranged along the gate busbar direction. During design, designers simply adjust the number of gates to adjust the gate capacitance. This gate adjustment method is relatively simple, and the virtual gate trenches are arranged in an integer ratio with the gate trenches. Correspondingly, the virtual gate and the effective trench gate are related in equal proportions, so the gate charge also increases in integer multiples. This means that when adjusting the gate-related capacitance, designers can only adjust the gate capacitance in integer multiples, but cannot continuously adjust the ratio. When actually adjusting, it is either too large or too small, which brings certain difficulties to device optimization. Utility Model Content

[0006] In order to solve the above technical problems, the utility model provides an IGBT with an optimized gate structure, in which a virtual gate can be continuously adjusted during design to optimize the device design.

[0007] The utility model discloses an IGBT with an optimized gate structure, comprising a plurality of cells, wherein the cells comprise a substrate, a gate groove and a plurality of first emitter grooves are arranged on the surface of the substrate, an emitter metal layer and a gate polysilicon layer are also arranged on the surface of the substrate, a gate is arranged in the gate groove, a first emitter gate electrode is arranged in the first emitter groove, the gate is connected to the gate polysilicon layer, an end of the first emitter gate electrode is connected to the emitter metal layer, a plurality of groups of co-linearly arranged second emitter grooves and virtual gate grooves are also arranged on the surface of the substrate, a virtual gate electrode is arranged in the virtual gate groove, a second emitter gate electrode is arranged in the second emitter groove, the second emitter groove is separated from the virtual gate groove by the substrate, one end of the second emitter gate electrode is connected to the emitter metal layer through a contact hole, and one end of the virtual gate electrode is connected to the gate polysilicon layer.

[0008] The advantage of the IGBT with optimized gate structure is that its cell has a hybrid design of adding virtual gate trenches and second emitter trenches in a direction perpendicular to the gate busbar, thereby realizing two-dimensional adjustment of gate capacitance in directions parallel to and perpendicular to the gate busbar.

[0009] Furthermore, in the IGBT with optimized gate structure of the utility model, each cell includes two first emitter trenches, and the two first emitter trenches are respectively located on the left and right sides of the cell.

[0010] Furthermore, in the IGBT with optimized gate structure of the present invention, each unit cell includes a group of second emitter trenches and virtual gate trenches arranged in a collinear manner.

[0011] The above description is only an overview of the technical solution of the utility model. In order to more clearly understand the technical means of the utility model and implement it in accordance with the contents of the specification, the following embodiments of the utility model are described in detail. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] Figure 1 is a plan view of an IGBT with an optimized gate structure.

[0013] Figure 2 yes Figure 1 A cross-sectional view corresponding to line C1 in FIG.

[0014] Figure 3 yes Figure 1 A cross-sectional view corresponding to line C2 in FIG.

[0015] In the figure, substrate 1, gate trench 2, first emitter trench 3, emitter metal layer 4, gate polysilicon layer 5, gate 6, first emitter gate electrode 7, second emitter trench 8, dummy gate trench 9, dummy gate electrode 10, second emitter gate electrode 11, well region 12, emitter region 13, and insulating dielectric layer 14. DETAILED DESCRIPTION

[0016] The following is a further detailed description of the specific implementation of the present invention in conjunction with the accompanying drawings and examples. The following examples are used to illustrate the present invention, but are not intended to limit the scope of the present invention.

[0017] Example 1: See Figures 1 to 3 The IGBT with optimized gate structure of this embodiment includes several cells, and the cell includes a substrate 1. A gate trench 2 and two first emitter trenches 3 are provided on the surface of the substrate. An emitter metal layer 4 and a gate polysilicon layer 5 are also provided on the surface of the substrate. A gate 6 is provided in the gate trench. A first emitter gate electrode 7 is provided in the first emitter trench. The gate is connected to the gate polysilicon layer, and the end of the first emitter gate electrode is connected to the emitter metal layer. A group of second emitter trenches 8 and virtual gate trenches 9 arranged in a collinear manner are also provided on the substrate surface of each cell. A virtual gate electrode 10 is provided in the virtual gate trench. A second emitter gate electrode 11 is provided in the second emitter trench. The second emitter trench is separated from the virtual gate trench by the substrate. One end of the second emitter gate electrode is connected to the emitter metal layer through a contact hole, and one end of the virtual gate electrode is connected to the gate polysilicon layer.

[0018] The advantage of the IGBT with optimized gate structure is that its cell has a hybrid design of adding virtual gate trenches and second emitter trenches in a direction perpendicular to the gate busbar, thereby realizing two-dimensional adjustment of gate capacitance in directions parallel to and perpendicular to the gate busbar.

[0019] Specifically, the cell includes a plurality of groups of collinearly arranged second emitter trenches and virtual gate trenches, the second emitter gate electrode in the second emitter trench is connected to the emitter metal layer, and one end of the virtual gate in the virtual gate trench is connected to the polysilicon layer. The second emitter trench and the virtual gate trench are separated by a certain distance through the substrate. The total length of the virtual gate trench and the second emitter trench is equivalent to the length of the first emitter trench or the gate trench. Since the virtual gate trench and the second emitter trench are collinearly designed, the designer can not only realize the substantial adjustment of the virtual gate by controlling the number of virtual gate trenches along the direction of the gate busbar, but also realize the fine adjustment of the virtual gate by adjusting the length ratio of the second emitter trench to the virtual gate trench in the direction perpendicular to the gate busbar, thereby realizing the free control of the virtual gate trench and the continuous control of the gate charge, so that the gate capacitance can be adjusted and optimized more accurately, so as to reduce the switching oscillation without introducing too much capacitance and increasing the energy consumption of the chip.

[0020] In addition, since there is a partition between the second emitter trench and the virtual gate trench, the partition distance not only realizes voltage protection, but also, since the length of the virtual gate trench can be adjusted in an infinitely variable manner, this not only realizes smooth adjustment of the gate capacitance to achieve the best performance of the IGBT, but also, several virtual gate trenches of different lengths also improve the problem of IGBT wafer warping.

[0021] In this embodiment, the two sides of the gate groove are well regions 12, the side of the top of the well region close to the gate groove is the emitter region 13, and the two first emitter trenches are respectively located on the side of the two well regions away from the gate. The second emitter trench and the virtual gate trench are both located between the first emitter trenches of adjacent cells. The emitter metal layer is located above the above-mentioned gate trench, the first emitter trench, the second emitter trench and the virtual gate trench, and each trench is isolated from the emitter metal layer by an insulating dielectric layer 14. In addition, the emitter metal layer is connected to the first emitter trench and the second emitter trench through contact holes, and the emitter metal layer is also connected to the above-mentioned emitter region through contact holes.

[0022] The above are only preferred implementations of the utility model, which are used to assist those skilled in the art to implement the corresponding technical solutions, and are not used to limit the scope of protection of the utility model. The scope of protection of the utility model is defined by the attached claims. It should be pointed out that for ordinary technicians in this field, on the basis of the technical solution of the utility model, several equivalent improvements and variations can be made, and these improvements and variations should also be regarded as the scope of protection of the utility model. At the same time, it should be understood that although this specification is described in accordance with the above-mentioned implementation modes, not every implementation mode contains only one independent technical solution. This narrative method of the specification is only for the sake of clarity. Those skilled in the art should regard the specification as a whole. The technical solutions of each embodiment can also be appropriately combined to form other implementation modes that can be understood by those skilled in the art.

Claims

1. An IGBT with an optimized gate structure, comprising a plurality of cells, the cells comprising a substrate, a gate trench and a plurality of first emitter trenches are provided on the surface of the substrate, an emitter metal layer and a gate polysilicon layer are also provided on the surface of the substrate, a gate is provided in the gate trench, a first emitter gate electrode is provided in the first emitter trench, the gate is connected to the gate polysilicon layer, and an end of the first emitter gate electrode is connected to the emitter metal layer, characterized in that: The substrate surface is also provided with a plurality of groups of second emitter grooves and virtual gate grooves arranged in a collinear manner, a virtual gate electrode is provided in the virtual gate groove, a second emitter gate electrode is provided in the second emitter groove, the second emitter groove and the virtual gate groove are separated by the substrate, one end of the second emitter gate electrode is connected to the emitter metal layer through a contact hole, and one end of the virtual gate electrode is connected to the gate polysilicon layer.

2. The IGBT with optimized gate structure according to claim 1, characterized in that: Each cell includes two first emitter trenches, and the two first emitter trenches are respectively located on the left and right sides of the cell.

3. The IGBT with optimized gate structure according to claim 1, characterized in that: Each unit cell includes a group of second emitter trenches and virtual gate trenches arranged in a collinear manner.

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