Chip packaging support and packaging structure using same
By designing the chip packaging bracket, the stable placement and heat dissipation of the main chip and the secondary chip are solved, and the problems of high cost and complex packaging in traditional packaging technology are achieved, and efficient and low-cost chip packaging is achieved.
Patent Information
- Application Number
- CN202420447543.7
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-03-08
- Publication Date
- 2025-03-28
- Estimated Expiration
- 2034-03-08
Smart Images
Figure CN222692247U_ABST
Abstract
Description
Technical Field
[0001] The utility model relates to the technical field of chip packaging, in particular to a chip packaging bracket and a packaging structure using the bracket. Background Art
[0002] LED is a solid-state semiconductor device that can convert electrical energy into light energy. It has the advantages of low power consumption, good luminous effect, strong controllability and long service life. In the manufacturing process of LED, the driver chip needs to be packaged. In the traditional technical solution, due to the limitations of materials and packaging technology, the main chip and the auxiliary chip are usually packaged separately, which will lead to an increase in cost. In order to save costs, it is necessary to package the main chip and the auxiliary chip together, and the current packaging technology is mature. In view of this, a chip packaging bracket and a packaging structure using the bracket are proposed. Utility Model Content
[0003] The utility model aims to provide a chip packaging bracket and a packaging structure using the bracket, which can support the packaging of a main chip and a sub-chip together.
[0004] The above technical objectives of the utility model are achieved through the following technical solutions:
[0005] A chip packaging bracket comprises a carrier, a main base, a first sub-base, a second sub-base, a main chip, a first sub-chip and a second sub-chip, wherein the main base, the first sub-base and the second sub-base are arranged on the carrier, the main chip is arranged on the main base, the first sub-chip is arranged on the first sub-base, and the second sub-chip is arranged on the second sub-base.
[0006] In a preferred embodiment, a main receiving groove is provided on the main base, a first secondary receiving groove is provided on the first secondary base, a second secondary receiving groove is provided on the second secondary base, the main chip is provided in the main receiving groove, the first secondary chip is provided in the first secondary receiving groove, and the second secondary chip is provided in the second secondary receiving groove.
[0007] In a preferred embodiment, a main heat dissipation bracket is provided in the main receiving groove, a first auxiliary heat dissipation bracket is provided in the first auxiliary receiving groove, and a second auxiliary heat dissipation bracket is provided in the second auxiliary receiving groove. The main heat dissipation bracket, the first auxiliary heat dissipation bracket and the second auxiliary heat dissipation bracket are arranged in a grid shape, and the grid is filled with a filling curing agent for bonding.
[0008] In a preferred embodiment, a first overflow space is formed between the outer wall of the main heat dissipation support and the inner wall of the main receiving groove, a second overflow space is formed between the outer wall of the first auxiliary heat dissipation support and the inner wall of the first auxiliary receiving groove, and a third overflow space is formed between the outer wall of the second auxiliary heat dissipation support and the inner wall of the second auxiliary receiving groove.
[0009] In a preferred embodiment, the bottoms of the main heat dissipation support, the first auxiliary heat dissipation support and the second auxiliary heat dissipation support are provided with flow holes.
[0010] In a preferred embodiment, the main heat dissipation support, the first auxiliary heat dissipation support and the second auxiliary heat dissipation support are made of graphite.
[0011] A packaging structure comprises the chip packaging bracket.
[0012] Compared with the prior art, the present invention packages the main chip, the first sub-chip and the second sub-chip together, so that the packaging process can be simplified and the packaging cost can be reduced. BRIEF DESCRIPTION OF THE DRAWINGS
[0013] Figure 1 The utility model is a structural schematic diagram of a chip packaging bracket (with a chip).
[0014] Figure 2 The utility model is a structural schematic diagram of a chip packaging bracket (excluding the chip).
[0015] Figure 3 The utility model is a schematic diagram of a partial longitudinal section structure of a chip packaging bracket.
[0016] In the picture
[0017] Carrier 1; main base 2; main receiving groove 3; main heat dissipation bracket 4; first sub-base 5; first sub-receiving groove 6; first sub-heat dissipation bracket 7; second sub-base 8; second sub-receiving groove 9; second sub-heat dissipation bracket 10; main chip 11; first sub-chip 12; second sub-chip 13; filling curing agent 14; first overflow space 15; second overflow space 16; third overflow space 17; circulation hole 18. DETAILED DESCRIPTION
[0018] The utility model is further described in detail below in conjunction with the accompanying drawings.
[0019] This specific embodiment is merely an explanation of the present invention and is not a limitation of the present invention. After reading this specification, those skilled in the art may make non-creative modifications to the present embodiment as needed, but such modifications are protected by patent law as long as they are within the scope of the claims of the present invention.
[0020] Embodiment 1:
[0021] like Figures 1 to 3 As shown, a chip packaging bracket includes a carrier 1, a main base 2, a first sub-base 5, a second sub-base 8, a main chip 11, a first sub-chip 12 and a second sub-chip 13. The main base 2, the first sub-base 5 and the second sub-base 8 are arranged on the carrier 1, the main chip 11 is arranged on the main base 2, the first sub-chip 12 is arranged on the first sub-base 5, and the second sub-chip 13 is arranged on the second sub-base 8.
[0022] In this embodiment, the main chip 11 , the first sub-chip 12 and the second sub-chip 13 are packaged together, so that the packaging process is simplified and the packaging cost is reduced.
[0023] In order to make the placement of the chip more stable, a main receiving groove 3 is provided on the main base 2, a first secondary receiving groove 6 is provided on the first secondary base 5, and a second secondary receiving groove 9 is provided on the second secondary base 8. The main chip 11 is arranged in the main receiving groove 3, the first secondary chip 12 is arranged in the first secondary receiving groove 6, and the second secondary chip 13 is arranged in the second secondary receiving groove 9, thereby achieving stable placement of each chip.
[0024] In order to improve the heat dissipation capacity so that the heat after concentrated packaging can be quickly discharged, a main heat dissipation bracket 4 is provided in the main receiving groove 3, a first sub-heat dissipation bracket 7 is provided in the first sub-receiving groove 6, and a second sub-heat dissipation bracket 10 is provided in the second sub-receiving groove 9. The main heat dissipation bracket 4, the first sub-heat dissipation bracket 7 and the second sub-heat dissipation bracket 10 are arranged in a grid shape, and the grid is filled with a filling curing agent 14 for pasting, and the filling curing agent 14 is used to paste the chip. Under the above structural setting, the main heat dissipation bracket 4, the first sub-heat dissipation bracket 7 and the second sub-heat dissipation bracket 10 are used to achieve heat conduction on the one hand, and to support the chip on the other hand. The grid-shaped setting is convenient for limiting the flow area of the filling curing agent 14 on the one hand, so as to avoid the filling curing agent 14 from contaminating the front of the chip during the chip placement process. On the other hand, the grid-shaped setting can achieve a good heat dissipation effect.
[0025] Furthermore, a first overflow space 15 is formed between the outer wall of the main heat dissipation bracket 4 and the inner wall of the main receiving groove 3, a second overflow space 16 is formed between the outer wall of the first auxiliary heat dissipation bracket 7 and the inner wall of the first auxiliary receiving groove 6, and a third overflow space 17 is formed between the outer wall of the second auxiliary heat dissipation bracket 10 and the inner wall of the second auxiliary receiving groove 9. In fact, the cross-sectional area of the chip is larger than that of the heat dissipation bracket. When the chip is placed, the filling curing agent 14 is likely to overflow the grid space of the heat dissipation bracket. After the overflow space is set, an overflow space is provided for the excess filling curing agent 14, thereby preventing the excess filling curing agent 14 from contaminating the front side of the chip.
[0026] In order to allow the filling curing agent 14 to fill the lattice space of the heat dissipation bracket, flow holes 18 are set at the bottom of the main heat dissipation bracket 4, the first auxiliary heat dissipation bracket 7 and the second auxiliary heat dissipation bracket 10. The filling curing agent 14 can flow in the flow holes 18 to completely fill the internal lattices of the heat dissipation bracket.
[0027] Furthermore, in order to achieve a better heat dissipation effect, the main heat dissipation bracket 4, the first sub-heat dissipation bracket 7 and the second sub-heat dissipation bracket 10 are made of graphite, and the good thermal conductivity of graphite is used to achieve rapid heat transfer and dissipation.
[0028] Embodiment 2:
[0029] A packaging structure includes the chip packaging bracket described in the first embodiment.
[0030] The above description of the embodiments is to facilitate the understanding and use of the present invention by ordinary technicians in the technical field. It is obvious that those familiar with the technical field can easily make various modifications to the embodiments and apply the general principles described here to other embodiments without creative work. Therefore, the present invention is not limited to the above embodiments. Improvements and modifications made by those skilled in the art based on the disclosure of the present invention without departing from the scope of the present invention should be within the scope of protection of the present invention.
Claims
1. A chip packaging bracket, characterized in that: The invention comprises a carrier, a main base, a first sub-base, a second sub-base, a main chip, a first sub-chip and a second sub-chip. The main base, the first sub-base and the second sub-base are arranged on the carrier, the main chip is arranged on the main base, the first sub-chip is arranged on the first sub-base, and the second sub-chip is arranged on the second sub-base.
2. A chip packaging bracket according to claim 1, characterized in that: The main base is provided with a main receiving groove, the first sub-base is provided with a first sub-receiving groove, the second sub-base is provided with a second sub-receiving groove, the main chip is arranged in the main receiving groove, the first sub-chip is arranged in the first sub-receiving groove, and the second sub-chip is arranged in the second sub-receiving groove.
3. A chip packaging bracket according to claim 2, characterized in that: A main heat dissipation bracket is provided in the main receiving groove, a first auxiliary heat dissipation bracket is provided in the first auxiliary receiving groove, and a second auxiliary heat dissipation bracket is provided in the second auxiliary receiving groove. The main heat dissipation bracket, the first auxiliary heat dissipation bracket and the second auxiliary heat dissipation bracket are arranged in a grid shape, and the grid is filled with a filling curing agent for bonding.
4. A chip packaging bracket according to claim 3, characterized in that: A first overflow space is formed between the outer wall of the main heat dissipation support and the inner wall of the main receiving groove, a second overflow space is formed between the outer wall of the first auxiliary heat dissipation support and the inner wall of the first auxiliary receiving groove, and a third overflow space is formed between the outer wall of the second auxiliary heat dissipation support and the inner wall of the second auxiliary receiving groove.
5. The chip packaging bracket according to claim 3, characterized in that: The bottoms of the main heat dissipation support, the first auxiliary heat dissipation support and the second auxiliary heat dissipation support are provided with flow holes.
6. The chip packaging bracket according to claim 3, characterized in that: The main heat dissipation support, the first auxiliary heat dissipation support and the second auxiliary heat dissipation support are made of graphite.
7. A packaging structure, characterized in that: A chip packaging bracket comprising any one of claims 1-6.