HEMT device

Abstract

The embodiment of the utility model relates to an HEMT device. An HEMT device includes: a semiconductor body forming a heterostructure; a gate region on the semiconductor body and extended along a first axis; a gate metal region including a lower portion on the gate region and recessed relative to the gate region and an upper portion on the lower portion and having a width along the second axis, the width being greater than the width of the lower portion; a source metal region extending on the semiconductor body and partially made of aluminum; a drain metal region on the semiconductor body, the source metal region and the drain metal region on opposite sides of the gate region; and a first conductivity enhancing region of aluminum nitride, the first conductivity enhancing region extending over the semiconductor body and interposed between the source metal region and the gate region, the first conductivity enhancing region being in direct contact with the source metal region and being separated from the gate region.

Description

Technical Field

[0001] The present disclosure relates to high electron mobility transistor (HEMT) devices with improved conductivity. Background Art

[0002] As is known, HEMT devices, also called heterostructure field effect transistors (HFETs), feature wide diffusion, high breakdown voltage and high density and mobility due to the possibility of operating at high voltages.

[0003] In HEMT devices, the semiconductor heterostructure (generally based on AlGaN / GaN layers) allows the so-called 2-dimensional electron gas (2DEG) to be generated spontaneously in the device, thus forming a channel path for the charges. The spontaneous channel can be regulated by applying a suitable voltage to the gate region on the channel path.

[0004] AlGaN / GaN HEMTs are usually depletion mode. However, for practical applications, enhancement mode (normally off) devices are preferred to obtain safe operation and simplify the driving circuit.

[0005] Several schemes have been proposed to realize normally-off HEMT based on AlGaN / GaN layers, including forming the gate region of p-GaN, such as Figure 1 As shown in the example in , it shows an orthogonal reference system XYZ. Specifically, Figure 1 A HEMT device 1 is shown, comprising a semiconductor body 2 including a substrate layer 3, a first layer 4 and a second layer 6 (hereinafter also referred to as a channel layer 4 and a barrier layer 6).

[0006] The substrate layer 3 may include Figure 1 The silicon substrate and the gallium nitride (GaN) buffer layer are not shown separately.

[0007] The channel layer 4 is of a first semiconductor material, such as, for example, a first semiconductor alloy of elements of Group III and Group V of the periodic table; for example, the channel layer 4 may be of gallium nitride (GaN).

[0008] The barrier layer 6 covers the channel layer 4 and is in direct contact with the channel layer 4, and the barrier layer 6 is a second semiconductor material, such as, for example, a second semiconductor alloy of elements of Group III-V of the periodic table of elements, which is different from the first semiconductor alloy. For example, the barrier layer 6 can be aluminum gallium nitride (AlGaN). The channel layer 4 and the barrier layer 6 are, for example, N-type.

[0009] In more detail, the barrier layer 6 is a top portion delimited by a front surface S6 parallel to the plane XY. The channel layer 4 and the barrier layer 6 extend parallel to the plane XY.

[0010] A gate region 7 of conductive material extends on the barrier layer 6. The gate region 7, also referred to as a channel modulation region, is formed, for example, of a third semiconductor material, such as, for example, a third semiconductor alloy of elements of Group III and Group V of the periodic table; specifically, the gate region 7 is here formed of gallium nitride of P conductivity type (pGaN).

[0011] A first insulating region 9 , for example of silicon oxide, extends on the barrier layer 6 , on lateral surfaces of the gate region 7 and on an upper surface of the gate region 7 .

[0012] An opening 11 extends through the first insulating region 9 on top of the gate region 7 , and a gate metal region 10 of, for example, TiN / AlCu / TiN extends in the opening 11 in direct electrical contact with the gate region 7 and partly on the first insulating region 9 .

[0013] A second insulating region 12 , for example silicon oxide, extends on the first insulating region 9 and on the gate metal region 10 .

[0014] A field plate 13 of conductive material may extend on the first insulating region 9 , laterally to the gate metal region 10 , and below the second insulating region 12 .

[0015] The source metal region 15, for example Ti / AlCu / TiN, extends on and laterally to the second insulating region 12 and is in direct electrical contact with the barrier layer 6. Specifically, a portion of the source metal region 15 is in contact with the barrier layer 6; the portion of the source metal region 15 is staggered laterally (i.e., along the X-axis) relative to the gate region 7. In addition, in the HEMT device 1, the source metal region 15 has a portion extending above the gate metal region 10 and above the field plate region 13 and has a masking function.

[0016] A drain metal region 16 of, for example, Ti / AlCu / TiN, extends on and laterally to the second insulating region 12. Specifically, the drain metal region 16 is laterally staggered relative to the gate region 7, extending on the opposite side of the gate region 7 relative to the source metal region 15. Furthermore, a portion of the drain metal region 16 extends in direct contact on the barrier layer 6.

[0017] exist Figure 1 In the figure, the lateral distance between the portion of the source metal region 15 contacting the barrier layer 6 and the gate region 7 is L gs The lateral distance between the portion of the drain metal region 16 contacting the barrier layer 6 and the gate region 7 is given by L gd (the so-called gate-drain distance) is specified.

[0018] Furthermore, the HEMT device 1 is a so-called non-self-aligned device because the manufacturing process for providing the gate metal region 10 is directed to: initially, the gate region 7 is formed; then, the first insulating region 9 is formed; then, the opening 11 is formed; and then the gate metal region 10 is formed. Therefore, instead of forming the gate region 7 and the gate metal region 10 by the same etching, the gate metal region 10 is formed after the formation of the gate region 7 (i.e., after the corresponding etching). In this way, the gate metal region 10 is mushroom-shaped; furthermore, this type of manufacturing process improves the reliability of the HEMT device 1 at high gate biases because it provides better control over the size of the gate metal contact.

[0019] Furthermore, variants are known which include additional insulating regions of silicon nitride (Si3N4) ( Figure 1 The additional insulating region is at least partially arranged on the first insulating region 9, so that the field plate includes a first portion and a second portion that are laterally staggered at different heights and extend on the first insulating region 9 and the additional insulating region, respectively, thereby reducing the capacitance of the HEMT device 1 and improving the breakdown voltage.

[0020] That being said, the gate-drain distance L gs Designed to enable the HEMT device 1 to withstand a high gate-drain voltage V gd ; Therefore, the gate-drain distance L gd It cannot generally be reduced below a certain threshold. Instead, ideally, by reducing the gate-source distance L gs , can reduce the so-called resistance R ON , and increase the saturation current and reduce the gate-source voltage V gs However, in order to form the mushroom-shaped gate metal region 10, the gate-source distance L cannot be excessively reduced. gs In addition, the gate-source distance L gs It must be large enough to allow for separate etching processes for defining the gate metal region 10 and the source metal region 15 . Utility Model Content

[0021] The present disclosure is directed to one or more embodiments to overcome one or more deficiencies existing in existing HEMT devices.

[0022] A HEMT device includes a heterostructure having a first surface, a gate region on the first surface, and the gate region having a second surface opposite to the first surface, a gate conductive region on the second surface, an insulating layer on the first surface and the second surface, a conductivity enhancement region on the first surface and the insulating layer and spaced apart from the gate region, and a source conductive region on the first surface and in contact with the conductivity enhancement region.

[0023] One embodiment of the present disclosure provides a HEMT device, the HEMT device including: a semiconductor body having a semiconductor heterostructure; a gate region, the gate region being on the semiconductor body and being elongated along a first axis; a gate metal region, the gate metal region including a corresponding lower portion and a corresponding upper portion, the corresponding lower portion being on the gate region and being laterally recessed relative to the gate region, the corresponding upper portion being on the lower portion and having a width along a second axis, the width being greater than the width of the lower portion; a source metal region, the source metal region extending on the semiconductor body and including aluminum; a drain metal region of a conductive material, the drain metal region extending on the semiconductor body, the source metal region and the drain metal region extending on opposite sides of the gate region; and a first conductivity enhancing region of aluminum nitride, the first conductivity enhancing region extending on the semiconductor body and being laterally interposed between the source metal region and the gate region, the first conductivity enhancing region being in direct contact with the source metal region and being separated from the gate region.

[0024] According to an embodiment, the HEMT device further comprises: a first dielectric region of a dielectric material, the dielectric material being different from silicon nitride, the first dielectric region extending on top of the semiconductor body, an inner portion of the first dielectric region covering the gate region, a lower portion of the gate metal region extending through the inner portion of the first dielectric region; a second dielectric region of silicon nitride, the second dielectric region being laterally interposed between the gate region and the drain metal region and comprising a respective first portion and a respective second portion, the respective first portion extending on the semiconductor body and laterally contacting a first peripheral portion of the first dielectric region, the respective second portion extending on the first peripheral portion of the first dielectric region; and a field plate of a conductive material, the field plate extending partially in direct contact on the second portion of the second dielectric region and partially in direct contact on the first dielectric region; and wherein the first conductivity enhanced region comprises: a respective first portion extending on the semiconductor body and laterally contacting the source metal region; and a respective second portion, the respective second portion extending on the second peripheral portion of the first dielectric region.

[0025] According to an embodiment, the HEMT device further includes a second conductivity enhanced region of aluminum nitride extending on the semiconductor body and laterally interposed in direct contact between the first portion of the second dielectric region and the drain metal region.

[0026] According to an embodiment, the first dielectric region includes: a sealing region of a non-conductive material; and a silicon oxide region, the silicon oxide region being on the sealing region.

[0027] According to an embodiment, the semiconductor body includes a channel layer of gallium nitride.

[0028] According to an embodiment, the gate region includes a channel modulation region of gallium nitride, the channel modulation region having p-type conductivity.

[0029] Another embodiment of the present disclosure provides a HEMT device, the HEMT device including: a heterostructure, the heterostructure having a first surface; a gate region, the gate region being on the first surface, the gate region having a second surface, the second surface being opposite to the first surface; a gate conductive region, the gate conductive region being on the second surface; an insulating layer, the insulating layer being on the first surface and the second surface; a conductivity enhanced region, the conductivity enhanced region being on the first surface and the insulating layer and being spaced apart from the gate region; and a source conductive region, the source conductive region being on the first surface and being in contact with the conductivity enhanced region.

[0030] According to an embodiment, the conductivity enhanced region includes aluminum nitride.

[0031] According to an embodiment, the insulating layer includes a sealing region on the first surface and a first dielectric region on the sealing region.

[0032] According to an embodiment, the HEMT device further includes: a drain conductive region on the first surface; and a second dielectric region on the first surface and the insulating layer and in contact with the drain conductive region.

[0033] According to an embodiment, the HEMT device further includes: a field plate on the first dielectric region and the second dielectric region, spaced apart from the gate conductive region, and spaced apart from the drain conductive region; and a third dielectric region on the field plate, the second dielectric region, and the first dielectric region.

[0034] According to an embodiment, the source conductive region is partially on the conductivity enhanced region and the drain conductive region is partially on the second dielectric region.

[0035] The above-described embodiments of the present disclosure can realize a HEMT device having improved conductivity. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] For the purpose of understanding the present disclosure, embodiments of the present disclosure will now be described purely as non-limiting examples with reference to the accompanying drawings, in which:

[0037] Figure 1 exemplarily shows a cross section of a known HEMT device;

[0038] Figure 2 exemplarily shows a cross section of a HEMT device according to an embodiment;

[0039] Figure 3, Figure 4 , Figure 5 , Figure 6 , Figure 7 , Figure 8 , Fig. 9 , Fig.10 , Fig.11 , Fig.12 , Fig.13 , Fig.14 , Fig.15 and Fig.16 It is shown as an example Figure 2 A cross section of a semiconductor wafer in a subsequent manufacturing step of a HEMT device;

[0040] Fig.17 exemplarily shows a cross section of a HEMT device according to another embodiment; and

[0041] Fig.18 , Fig.19 , Fig. 20 and Fig.21 It is shown as an example Fig.17 Cross section of a semiconductor wafer during the subsequent fabrication steps of a HEMT device. DETAILED DESCRIPTION

[0042] Figure 2 An orthogonal reference frame XYZ and a HEMT device 20 are shown, which comprises a semiconductor body 22 , here formed by a substrate 23 , a channel layer 24 and a barrier layer 26 .

[0043] The substrate 23 may include Figure 2 The silicon substrate and the gallium nitride (GaN) buffer layer are not shown separately.

[0044] The channel layer 24 is of a first semiconductor material, such as a first semiconductor alloy of elements of Group III and Group V of the periodic table; for example, the channel layer 24 may be of gallium nitride (GaN).

[0045] Barrier layer 26 directly covers channel layer 24 and is a second semiconductor material, such as a second semiconductor alloy of elements from Group III to Group V of the periodic table, different from the first semiconductor alloy. For example, barrier layer 26 may be aluminum gallium nitride (AlGaN).

[0046] The channel layer 24 and the barrier layer 26 are, for example, of N-type.

[0047] In more detail, the barrier layer 26 is composed of a front surface S parallel to the plane XY. t The channel layer 24 and the barrier layer 26 extend parallel to the plane XY.

[0048] The gate region 27 of the conductive material is on the front surface S t The gate region 27 extends in direct contact with the barrier layer 26. In a manner not shown, the gate region 27 is strip-shaped and extends parallel to the Y axis; in other words, the gate region 27 is elongated along the Y axis.

[0049] exist Figure 2 In the example of , the gate region 27 includes a channel modulation region 28 of pGaN (P conductivity type gallium nitride). The channel modulation region 28 operates to modulate the thickness of the conduction channel (i.e., 2-dimensional electron gas - 2DEG) formed at the interface between the channel layer 24 and the barrier layer 26 based on a voltage applied to the conduction channel.

[0050] according to Figure 2 In the example shown in , the gate region 27 further includes an interlayer region 29 (optional) extending in direct contact on the channel modulation region 28 .

[0051] The interlayer region 29 may be a material such as TiN. Figure 2 In the embodiment of FIG. 5 , the interlayer region 29 has a width (parallel to the X-axis) smaller than the channel modulation region 28 .

[0052] The HEMT device 20 further includes a sealing region 31, which is composed of a non-conductive material (e.g., an oxide such as Al2O3) and covers the lateral sides and a portion of the upper side of the channel modulation region 28; specifically, the sealing region 31 directly contacts and covers the portion of the channel modulation region 28 exposed by the interlayer region 29. In addition, the sealing region 31 directly contacts and covers the lateral sides and a portion of the upper side of the interlayer region 29, thereby laterally delimiting a lower portion of a gate opening 33, which extends through the sealing region 31 and is delimited at the bottom by a portion of the interlayer region 29.

[0053] Furthermore, the sealing region 31 extends in direct contact over a portion of the barrier layer 26 which is laterally staggered relative to the overlying channel modulation region 28 .

[0054] The HEMT device 20 further includes a first dielectric region 32 , a second dielectric region 34 , a transition region 35 , a source metal region 45 , a drain metal region 46 , and a gate metal region 50 .

[0055] In detail, the first dielectric region 32 is composed of silicon oxide (eg, TEOS oxide) and extends in direct contact on the sealing region 31. An inner portion of the first dielectric region 32 is penetrated by the gate opening 33.

[0056] As an example, the second dielectric region 34 is composed of silicon nitride (Si3N4) and includes a first portion 36' and a second portion 36". The first portion 36' is laterally staggered relative to the sealing region 31 and the first dielectric region 32, thereby extending in direct contact on corresponding portions of the barrier layer 26. The first portion 36' is in laterally contact with the sealing region 31 and the first dielectric region 32. The second portion 36" extends over a first peripheral portion of the first dielectric region 32, so that the first portion 36' and the second portion 36" define a step profile.

[0057] The transition region 35 is composed of aluminum nitride (AlN) and includes a respective first portion 38 ′ and a respective second portion 38 ″.

[0058] The first portion 38' is laterally staggered relative to the sealing region 31 and the first dielectric region 32 so as to extend in direct contact over corresponding portions of the barrier layer 26. Specifically, the first portion 38' of the transition region 35 and the first portion 36' of the second dielectric region 34 are arranged at a distance on opposite sides of the channel modulation region 28. In addition, the first portion 38' of the transition region 35 laterally contacts the sealing region 31 and the first dielectric region 32.

[0059] The second portion 38″ of the transition region 35 extends over the second peripheral portion of the first dielectric region 32 such that the first portion 38′ and the second portion 38″ define a step profile. Specifically, the above-mentioned first peripheral portion of the first dielectric region 32 and the second peripheral portion of the first dielectric region 32 are arranged at a certain distance on opposite sides of the gate region 27.

[0060] The source metal region 45 is formed of aluminum or an aluminum alloy (e.g., AlCu) and extends in direct contact on the corresponding portion of the barrier layer 26 exposed by the first portion 38' of the transition region 35. Specifically, the lower portion of the source metal region 45 contacts the corresponding portion of the barrier layer 26 and laterally contacts the first portion 38' of the transition region 35.

[0061] The drain metal region 46 is formed of aluminum or an aluminum alloy (e.g., AlCu) and extends in direct contact on a corresponding portion of the barrier layer 26 exposed by the first portion 36' of the second dielectric region 34. Specifically, a lower portion of the drain metal region 46 contacts the corresponding portion of the barrier layer 26 and laterally contacts the first portion 36' of the second dielectric region 34.

[0062] As an example, the gate metal region 50 is formed of multiple layers of TiN / AlCu / TiN and extends in the gate opening 33 in direct contact with the underlying interlayer region 29 so that the interlayer region 29 improves the Schottky contact between the gate metal region 50 and the channel modulation region 28 .

[0063] Source metal region 45 and drain metal region 46 extend on different sides of gate region 27 .

[0064] The HEMT device 20 further includes a field plate 51 and a third dielectric region 53 , which serves as a passivation region.

[0065] The field plate 51 is composed of a conductive material and includes an upper portion and a lower portion, wherein the upper portion extends in direct contact on the second portion 36″ of the second dielectric region 34 and the lower portion extends in direct contact on the corresponding portion of the first dielectric region 32, so that the field plate 51 defines a step profile. In addition, the field plate 51 is arranged between the gate metal region 50 and the drain metal region 46; in addition, the field plate 51 can be formed of the same material as the gate metal region 50 and can be electrically connected to the source metal region 45.

[0066] The third dielectric region 53 is composed of silicon oxide (e.g., TEOS oxide) and extends in direct contact on the field plate 51, on the portion of the second dielectric region 34 exposed by the field plate 51, on the transition region 35, and on the portion of the first dielectric region 32 exposed by the transition region 35, the field plate 51, and the second dielectric region 34. In addition, the third dielectric region 53 laterally coats the source metal region 45 and the drain metal region 46. In addition, as shown in FIG. Figure 2 As shown in FIG. 1 , the third dielectric region 53 may also extend on top of the source metal region 45 and the drain metal region 46; however, although Figure 2 Not shown in FIG. 5 , but openings are present in third dielectric region 53 that allow corresponding top portions of source metal region 45 and drain metal region 46 to be exposed to allow formation of corresponding electrical contacts.

[0067] Furthermore, gate opening 33, in addition to extending through first dielectric region 32 and sealing region 31, also extends through third dielectric region 53. Thus, gate metal region 50 extends through third dielectric region 53; moreover, portions of gate metal region 50 extend directly in contact with third dielectric region 53.

[0068] In more detail, the gate metal region 50 includes a corresponding lower portion 50', which extends in the gate opening 33 and has a width (parallel to the X-axis) that is smaller than the width of the channel modulation region 28 and the width of the interlayer region 29; in addition, the lower portion 50' is laterally recessed relative to the underlying gate region 27 (i.e., along the X-axis, the channel modulation region 28 and the interlayer region 29 protrude on both sides relative to the lower portion 50'). In addition, the gate metal region 50 includes a corresponding upper portion 50", which extends on the lower portion 50' and on top of the third dielectric region 53; the upper portion 50" has a width greater than the width of the lower portion 50'.

[0069] In practice, the gate metal region 50 has a mushroom shape, which together with the fact that the lower portion 50' is laterally recessed relative to the underlying gate region 27, confers electrical stability to the HEMT device 20. Furthermore, the Applicant has noticed that the presence of the transition region 35 causes an increase in the conductivity of the portion of the conductive channel arranged below the transition region 35, thus improving the performance of the HEMT device 20. In practice, the transition region 35 acts as a conductivity enhancement region.

[0070] Furthermore, the field plate 51 allows modulation of the electric field between the drain metal region 46 and the gate metal region 50, thereby reducing the peak value of the electric field close to the channel modulation region 28 and the electric field in the portion of the second dielectric region 34 adjacent to the drain metal region 46. Furthermore, due to the presence of two different dielectric materials that form the first dielectric region 32 and the second dielectric region 34, respectively, the field plate 51 can be formed by selectively etching and patterning the second dielectric region 34 as opposed to time etching, thereby achieving precise control of the shape of the field plate 51, as explained in more detail below.

[0071] The HEMT device 20 may be manufactured as shown in the following figure, which shows a wafer 100 before dicing, the wafer 100 including a semiconductor body 22 , ie including a substrate 23 , a channel layer 24 and a barrier layer 26 .

[0072] like Figure 3As shown in , initially the wafer 100 is operated in a manner known per se, so that the channel modulation region 28 and the interlayer region 29 are formed. By way of example, although not shown in detail, the channel modulation region 28 and the interlayer region 29 can be formed by sputtering a TiN layer on a pGaN layer (not shown, epitaxially grown on the barrier layer 26), and defining the TiN layer and the pGaN layer by lateral etching using a single mask (also not shown) to obtain an interlayer region 29 of smaller width; however, any other manufacturing steps are possible, for example by using two different masks. In addition, a sealing layer 131 is formed on the exposed gate region 27 and the barrier layer 26; by way of example, the sealing layer 131 is thermally deposited or plasma deposited at 300° C. in an environment based on H2O or O3 using an ALD (atomic layer deposition) technique to a thickness in the range [2nm-10nm] (e.g., 2.5nm).

[0073] Then, if Figure 4 As shown in FIG. 1 , the first dielectric layer 132 is formed on the sealing layer 131; as an example, the first dielectric layer 132 is formed by depositing silicon oxide in a SiH4-based environment by PECVD (plasma enhanced chemical vapor deposition). As an example, the first dielectric layer 132 can have a thickness (e.g., 200 nm) included in the range [20 nm-300 nm].

[0074] Then, if Figure 5 As shown in FIG, portions of the sealing layer 131 and the first dielectric layer 132 are removed by an etching process, thereby defining a first window W1 facing a corresponding exposed portion of the barrier layer 26 , which is intended to contact the source metal region 45 and the first portion 38 ′ of the transition region 35 .

[0075] Then, if Figure 6 As shown in FIG. 1 , a second dielectric layer 135 of silicon nitride is formed on the first dielectric layer 132 and on the exposed portion of the barrier layer 26, i.e., the inner side of the first window W1. As an example, the second dielectric layer 135 is formed by depositing silicon nitride using PECVD. As an example, the second dielectric layer 135 may have a thickness (e.g., 100 nm) included in the range [50 nm-300 nm]. Hereinafter, reference is made to the first type of silicon nitride to refer to the silicon nitride forming the second dielectric layer 135.

[0076] In more detail, the first type of silicon nitride is silicon-rich silicon nitride having a percentage of silicon such that its reflectivity is greater than or equal to 1.95; as an example, the reflectivity of the first type of silicon nitride is greater than or equal to 2.

[0077] Then, if Figure 7, a portion of the second dielectric layer 135 is selectively removed, thereby exposing a portion of the first dielectric layer 132 covering the gate region 27. The remaining portion of the second dielectric layer 135 forms a residual dielectric region 135', which is composed of the first type of silicon nitride described above. As explained below, the residual dielectric region 135' serves as a preliminary region.

[0078] Then, if Figure 8 As shown in FIG. 1 , a portion of the sealing layer 131 and a portion of the first dielectric layer 132 are removed by an etching process, thereby defining a second window W2, which faces a corresponding exposed portion of the barrier layer 26, which is intended to contact the drain metal region 46 and the first portion 36' of the second dielectric region 34. The remaining portion of the sealing layer 131 and the remaining portion of the first dielectric layer 132 form the sealing region 31 and the first dielectric region 32, respectively.

[0079] The residual dielectric region 135' laterally delimits a recess 139 which is also laterally delimited by a corresponding portion of the first dielectric region 32 extending over the gate region 27. The recess 139 is delimited at the bottom by a portion of the first dielectric region 32 which is laterally staggered relative to the gate region 27.

[0080] Then, if Fig. 9 , a third dielectric layer 134 of silicon nitride is formed on the residual dielectric region 135', on the first dielectric region 32 and on the exposed portion of the barrier layer 26, i.e., inside the second window W2, and inside the recess 139. As an example, the third dielectric layer 134 is formed by depositing silicon nitride by PECVD. As an example, the third dielectric layer 134 may have a thickness (e.g., 80 nm) included in the range [50 nm-300 nm]. Hereinafter, reference is made to the second type of silicon nitride to refer to the silicon nitride forming the third dielectric layer 134.

[0081] The second type of silicon nitride is nitrogen-rich silicon nitride having a percentage of silicon such that its reflectivity is lower than 1.95; as an example, the reflectivity of the second type of silicon nitride is lower than 1.9.

[0082] Then, if Fig.10 As shown in FIG. 1 , portions of the third dielectric layer 134 are selectively removed by an etching process. This etching process has an end point represented by silicon oxide of the first dielectric region 32.

[0083] The remaining portion of the third dielectric layer 134 forms a first portion 36' and a second portion 36". of the second dielectric region 34. In this manner, the residual dielectric region 135' and a portion of the first dielectric region 32 become exposed; moreover, the first portion 36' of the second dielectric region 34 also temporarily covers a portion of the barrier layer 26 that will contact the drain metal region 46 at the end of the manufacturing process. Furthermore, although not shown, during this etching process, negligible overetching of the residual dielectric region 135' may occur.

[0084] Then, if Fig.11 As shown in FIG. 5 , as an example, the field plate 51 is formed by a sputtering process and a subsequent selective removal process.

[0085] Then, if Fig.12 , the drain opening WD and the source opening WS are formed through the first portion 36' and the residual dielectric region 135' of the second dielectric region 34, respectively. In practice, the drain opening WD is formed by selectively removing a portion of the first portion 36' of the second dielectric region 34, thereby exposing a corresponding portion of the barrier layer 26; the source opening WS is formed by selectively removing a portion of the residual dielectric region 135', thereby exposing a corresponding portion of the barrier layer 26. Since both the residual dielectric region 135' and the second dielectric region 34 are silicon nitride (although of different types), a single etching process is performed to form the drain opening WD and the source opening WS.

[0086] Then, if Fig.13 As shown in FIG. 4 , source metal region 45 and drain metal region 46 are formed so as to extend through source opening WS and drain opening WD, respectively. As an example, source metal region 45 and drain metal region 46 may be formed by sputtering an aluminum layer and by performing a subsequent lift-off process.

[0087] Then, if Fig.14 As shown in FIG. 3 , a thermal treatment is performed to transform the remaining portion of the residual dielectric region 135 ′ into the transformed region 35 .

[0088] Specifically, as an example, the thermal treatment occurs at a temperature in the range of [500-600]° C. (as an example, 560° C.) and has a duration in the range of [2-5] minutes, thereby transforming the first type of silicon nitride of the residual dielectric region 135 ′ into aluminum nitride (AlN). In this regard, the applicant has noted that during the above-mentioned thermal treatment, the second type of silicon nitride forming the second dielectric region 34 is not transformed into aluminum nitride, in contrast to the first type of silicon nitride.

[0089] In more detail, a transformation of the first type of silicon nitride of the residual dielectric region 135' to aluminum nitride (AlN) occurs due to the presence of aluminum atoms in the source metal region 45. Specifically, such a transformation continues over time, starting from the portion of the residual dielectric region 135' that contacts the source metal region 45, which is transformed into a first portion 38' of the transformed region 35, toward the portion of the residual dielectric region 135' that is separated from the source metal region 45, which is transformed into a second portion 38" of the transformed region 35.

[0090] Then, if Fig.15 , the fourth dielectric layer 153 is formed on the transition region 35, the field plate 51, and the exposed portions of the first dielectric region 32 and the second dielectric region 34, as well as on the source metal region 45 and the drain metal region 46. As an example, the fourth dielectric layer 153 is formed by depositing silicon oxide by PECVD. Although not shown, openings in the fourth dielectric layer 153 that expose corresponding top portions of the source metal region 45 and the drain metal region 46 are then formed in a manner known per se.

[0091] Then, if Fig.16 As shown in FIG. 1 , the gate opening 33 is formed by selectively removing a portion of the fourth dielectric layer 153 and a lower portion of the sealing layer 31; the remaining portion of the fourth dielectric layer 153 forms the third dielectric region 53. Then, although not shown, the gate metal region 50 is formed in a manner known per se.

[0092] Then, a final manufacturing step follows, which consists in dicing the wafer 100, thus obtaining Figure 2 HEMT device 20.

[0093] Fig.17 Another embodiment is shown, which is described herein below with reference to Figure 2 Unless otherwise specified, the Figure 2 The elements in the embodiments are indicated in the same way.

[0094] The HEMT device (designated herein by 200) includes an additional transition region 235 of aluminum nitride (AlN). Furthermore, a second dielectric region (designated herein by 234, with first and second portions designated by 236' and 236" for each) is composed of a first type of silicon nitride.

[0095] The additional transition region 235 is laterally staggered relative to the first portion 236 ′ of the second dielectric region 234 and extends in direct contact over a corresponding portion of the barrier layer 26 ; moreover, the additional transition region 235 laterally contacts the first portion 236 ′ of the second dielectric region 234 .

[0096] The drain metal region 46 laterally contacts the additional transition region 235, so the drain metal region 46 is separated from the second dielectric region 234. In addition, the third dielectric region 53 covers the additional transition region 235.

[0097] From a practical point of view, the presence of the additional transition region 235 allows increasing the conductivity of the portion of the conducting channel arranged below the additional transition region 235 without reducing the gate-drain distance.

[0098] Can be used with Figure 2 The HEMT device 200 is manufactured in the same manner as the HEMT device 20 , but has the following differences.

[0099] In detail, Fig.18 As shown in FIG. 1 , the manufacturing process provides for forming an additional first window W1′ together with the above-mentioned first window W1 after forming the sealing layer 131 and the first dielectric layer 132. The additional first window W1′ extends to the corresponding exposed portion of the barrier layer 26. The remaining portion of the sealing layer 131 and the remaining portion of the first dielectric layer 132 form the sealing region 31 and the first dielectric region 32, respectively.

[0100] Then, if Fig.19 As shown in FIG. 1 , a second dielectric layer 135 of the first type silicon nitride is formed on the first dielectric region 32 and the exposed portion of the barrier layer 26 , ie, inside the first window W1 and the additional first window W1 ′.

[0101] Then, if Fig. 20 As shown in FIG. 1 , a portion of the second dielectric layer 135 is selectively removed, thereby exposing the first dielectric region 32. The remaining portion of the second dielectric layer 135 forms the above-mentioned residual dielectric region 135' and the additional residual dielectric region 235'. The additional residual dielectric region 235' forms the second portion 236" of the second dielectric region 234 and the preliminary region 240.

[0102] Then, the manufacturing process is similar to the reference Figures 11 to 16 The description continues in the same manner, but in fact the drain opening WD is formed through the preliminary region 240 (ie, by removing a portion of the preliminary region 240), as shown in FIG. Fig.21 As shown in .

[0103] In addition, although not shown in detail, the heat treatment causes a portion of the remaining portion of the preliminary region 240 to transform into the additional transformation region 235. In addition, the width of the preliminary region 240 along the X-axis and the parameters of the heat treatment (i.e., temperature and duration) can be compared with the reference Figure 2The parameters mentioned in the embodiment are the same, so that part of the preliminary region 240 is not converted into aluminum nitride, ie, it remains silicon nitride, and forms the first portion 236 ′ of the second dielectric region 234 , thereby maintaining the high breakdown voltage of the HEMT device 200 .

[0104] Finally, it is clear that various modifications and variations may be made to the HEMT devices and processes described and illustrated herein, all falling within the scope of the present disclosure as defined in the appended claims.

[0105] As an example, the field plate 51 may not be present or may have a different shape.

[0106] The HEMT device may be of the normally-on type. As an example, the channel modulation region may be made of a metallic material as opposed to a semiconductor material.

[0107] The structure of the semiconductor body may be different. As an example, different materials may be used and / or other layers may be present, such as a spacer layer (eg, of AlN) interposed between the channel layer 24 and the barrier layer 26 .

[0108] A HEMT device (20; 200) can be summarized as comprising: a semiconductor body (22), the semiconductor body forming a semiconductor heterostructure (24, 26); a gate region (27), the gate region (27) being arranged on the semiconductor body (22) and being elongated along a first axis (Y); a gate metal region (50), the gate metal region comprising a respective lower portion (50') and a respective upper portion (50"), the respective lower portion (50') being arranged on the gate region (27) and being laterally recessed relative to the gate region (27), the respective upper portion (50") being arranged on the lower portion (50') and having a width along a second axis (X) that is greater than the width of the lower portion (50'). ') has a large width; a source metal region (45), the source metal region extends on the semiconductor body (22) and is at least partially made of aluminum; a drain metal region (46) of conductive material, the drain metal region extends on the semiconductor body (22), the source metal region (45) and the drain metal region (46) extend on opposite sides of the gate region (27); a first conductivity enhancement region (35) of aluminum nitride, the first conductivity enhancement region extends on the semiconductor body (22) and is laterally interposed between the source metal region (45) and the gate region (27), the first conductivity enhancement region (35) is in direct contact with the source metal region (45) and is separated from the gate region (27).

[0109] The HEMT device may also include: a first dielectric region (31, 32) of dielectric material, the dielectric material being different from silicon nitride, the first dielectric region (31, 32) extending on top of the semiconductor body (22), an inner portion of the first dielectric region (31, 32) covering the gate region (27), a lower portion (50") of the gate metal region (50) extending through the inner portion of the first dielectric region (31, 32); and a second dielectric region (34, 234) of silicon nitride, the second dielectric region (34, 234) being laterally interposed between the gate region (27) and the drain metal region (46) and including a respective first portion (36'; 236') and a respective second portion (36"; 236"), the respective first portion (36'; 236') extending on the semiconductor body (22) and laterally The invention relates to a first dielectric region (31, 32) and a first peripheral portion (36"; 236") of the first dielectric region (31, 32) in direct contact with the first dielectric region (31, 32), and a corresponding second portion (36"; 236") extending on the first peripheral portion (31, 32); and a field plate (51) of conductive material, the field plate partially extending in direct contact with the second portion (36"; 236") of the second dielectric region (34; 234) and partially extending in direct contact with the first dielectric region (31, 32); and the first conductivity enhancement region (35) may include: a corresponding first portion (38'), the corresponding first portion (38') extending on the semiconductor body (22) and laterally contacting the source metal region (45); and a corresponding second portion (38"), the corresponding second portion (38") extending on the second peripheral portion (31, 32) of the first dielectric region (31, 32).

[0110] The HEMT device may further include: a second conductivity enhancing region (235) of aluminum nitride extending on the semiconductor body (22) and being interposed in direct contact and laterally between the first portion (236') of the second dielectric region (234) and the drain metal region (46).

[0111] The first dielectric region (31, 32) may include: a sealing region (31) of a non-conductive material; and a silicon oxide region (32), the silicon oxide region being arranged on the sealing region (31).

[0112] The semiconductor body (22) may include a channel layer (24) of gallium nitride.

[0113] The gate region (27) may include a channel modulation region (28) of gallium nitride, the channel modulation region (28) having p-type conductivity.

[0114] A method for manufacturing a HEMT device (20; 200) can be summarized as comprising: forming a gate region (27) on a semiconductor body (22), the semiconductor body (22) forming a semiconductor heterostructure (24, 26), the gate region (27) being elongated along a first axis (Y); forming a gate metal region (50), the gate metal region (50) comprising a respective lower portion (50') on the gate region (27) and laterally recessed relative to the gate region (27), and a respective upper portion (50") on the lower portion (50') and having a width along a second axis (X) that is greater than a width of the lower portion (50'); forming a source A gate region (27) is formed by forming a first conductivity enhancement region (35) of aluminum nitride, the first conductivity enhancement region (35) extending on the semiconductor body (22) and being laterally interposed between the source metal region (45) and the gate region (27), the first conductivity enhancement region (35) being in direct contact with the source metal region (45) and being separated from the gate region (27).

[0115] Forming the first conductivity enhancing region (35) may include: forming a preliminary dielectric region (135') of silicon nitride, the preliminary dielectric region (135') laterally contacting the source metal region (45); and performing a thermal treatment to transform the preliminary dielectric region (135') into the first conductivity enhancing region (35).

[0116] The method may also include: forming a first dielectric region (31, 32) of dielectric material, the dielectric material being different from silicon nitride, the first dielectric region (31, 32) extending on top of the semiconductor body (22), an inner portion of the first dielectric region (31, 32) covering the gate region (27), a lower portion (50") of the gate metal region (50) extending through the inner portion of the first dielectric region (31, 32); forming a second dielectric region (34, 234) of silicon nitride, the second dielectric region (34, 234) being laterally interposed between the gate region (27) and the drain metal region (46), and including a respective first portion (36'; 236') and a respective second portion (36"; 236"), the respective first portion (36'; 236') extending on the semiconductor body (22) and laterally contacting a first peripheral portion of the first dielectric region (31, 32), the respective second portion (36"; 236") extending on a first peripheral portion of the first dielectric region (31, 32); and forming a field plate (51) of conductive material, the field plate (51) partially extending in direct contact with a second portion (36"; 236") of the second dielectric region (34; 234), and the field plate (51) partially extending in direct contact with the first dielectric region (31, 32); and forming a first conductivity enhancement region (35) may include: forming a first portion (38') of the first conductivity enhancement region (35), the first portion (38') of the first conductivity enhancement region (35) extending on the semiconductor body (22) and laterally contacting the source metal region (45); and forming a second portion (38") of the first conductivity enhancement region (35), the second portion (38") of the first conductivity enhancement region (35) extending on a second peripheral portion of the first dielectric region (31, 32).

[0117] Forming the second dielectric region (34) may include: forming a dielectric layer (134) of silicon nitride after forming the preliminary dielectric region (135'); and selectively removing a portion of the dielectric layer (134), the remaining portion of the dielectric layer (134) forming the second dielectric region (34).

[0118] Forming the source metal region (45) and the drain metal region (46) may include: forming a source opening (WS) and a drain opening (46), the source opening (WS) and the drain opening (46) respectively passing through the preliminary dielectric region (135') and the first portion (36') of the second dielectric region (34); and forming the source metal region (45) and the drain metal region (46) so that the source metal region (45) and the drain metal region (46) extend in the source opening (WS) and the drain opening (46), respectively.

[0119] The preliminary dielectric region (135') may be made of silicon nitride with a percentage of silicon such that the corresponding refractive index is greater than or equal to 1.95; and the second dielectric region (34) may be made of silicon nitride with a percentage of silicon such that the corresponding refractive index is lower than 1.95.

[0120] The method may also include forming a second conductivity enhancing region (235) of aluminum nitride extending over the semiconductor body (22) and interposed in direct contact and laterally between the first portion (236') of the second dielectric region (234) and the drain metal region (46).

[0121] The drain metal region (46) may be at least partially made of aluminum, and the method may further include: forming an additional preliminary dielectric region (235'), the preliminary dielectric region (135') and the additional preliminary dielectric region (235') being made of silicon nitride having a certain percentage of silicon such that the corresponding refractive index is greater than or equal to 1.95; and forming the source metal region (45) and the drain metal region (46) may include: forming a source opening (WS) and a drain opening (46), the source opening (WS) and the drain opening (46) respectively passing through A preliminary dielectric region (135') and an additional preliminary dielectric region (235'); and forming a source metal region (45) and a drain metal region (46) so that the source metal region (45) and the drain metal region (46) extend in the source opening (WS) and the drain opening (46), respectively; and thermal treatment causes a portion (240) of the additional preliminary dielectric region (235') to transform into a second conductivity enhanced region (235), and a portion of the additional preliminary dielectric region (235') forms a second dielectric region (234).

[0122] The various embodiments described above can be combined to provide further embodiments. Aspects of the embodiments can be modified, if necessary to employ concepts of the various patents, applications and publications to provide further embodiments.

[0123] These and other changes can be made to the embodiments in light of the above detailed description. In general, in the appended claims, the terms used should not be interpreted as limiting the claims to the specific embodiments disclosed in the specification and claims, but should be interpreted to include all possible embodiments and the full scope of equivalents to which these claims are entitled. Therefore, the claims are not limited by the present disclosure.

Claims

1. A HEMT device, characterized in that: include: a semiconductor body having a semiconductor heterostructure; a gate region on the semiconductor body and elongated along a first axis; a gate metal region, the gate metal region comprising a respective lower portion and a respective upper portion, the respective lower portion being on the gate region and being laterally recessed relative to the gate region, the respective upper portion being on the lower portion and having a width along a second axis that is greater than a width of the lower portion; a source metal region extending over the semiconductor body and comprising aluminum; a drain metal region of conductive material, the drain metal region extending over the semiconductor body, the source metal region and the drain metal region extending on opposite sides of the gate region; as well as A first conductivity enhancing region of aluminum nitride extends over the semiconductor body and is laterally interposed between the source metal region and the gate region, the first conductivity enhancing region being in direct contact with the source metal region and separated from the gate region.

2. The HEMT device according to claim 1, characterized in that: Also includes: a first dielectric region of a dielectric material other than silicon nitride, the first dielectric region extending over a top portion of the semiconductor body, an inner portion of the first dielectric region covering the gate region, the lower portion of the gate metal region extending through the inner portion of the first dielectric region; a second dielectric region of silicon nitride, the second dielectric region being laterally interposed between the gate region and the drain metal region and comprising a respective first portion and a respective second portion, the respective first portion extending over the semiconductor body and laterally contacting a first peripheral portion of the first dielectric region, the respective second portion extending over the first peripheral portion of the first dielectric region; as well as a field plate of conductive material extending partially in direct contact over the second portion of the second dielectric region and partially in direct contact over the first dielectric region; And wherein the first conductivity enhanced region comprises: a respective first portion extending over the semiconductor body and laterally contacting the source metal region; as well as A corresponding second portion extends over a second peripheral portion of the first dielectric region.

3. The HEMT device according to claim 2, characterized in that: Also includes: A second conductivity enhancing region of aluminum nitride extends over the semiconductor body and is interposed laterally in direct contact between the first portion of the second dielectric region and the drain metal region.

4. The HEMT device according to claim 2, characterized in that: The first dielectric region comprises: Sealing areas of non-conductive material; and A silicon oxide region is provided on the sealing region.

5. The HEMT device according to claim 1, characterized in that: The semiconductor body includes a channel layer of gallium nitride.

6. The HEMT device according to claim 1, characterized in that: The gate region includes a channel modulation region of gallium nitride, and the channel modulation region has p-type conductivity.

7. A HEMT device, characterized in that: include: a heterostructure having a first surface; a gate region, the gate region being on the first surface, the gate region having a second surface, the second surface being opposite to the first surface; a gate conductive region, the gate conductive region being on the second surface; an insulating layer, the insulating layer being on the first surface and the second surface; a conductivity enhancement region on the first surface and the insulating layer and spaced apart from the gate region; as well as A source conductive region is on the first surface and in contact with the conductivity enhanced region.

8. The HEMT device according to claim 7, characterized in that: The conductivity enhanced region includes aluminum nitride.

9. The HEMT device according to claim 8, characterized in that: The insulating layer comprises: a sealing area on the first surface; and A first dielectric region is disposed on the sealing region.

10. The HEMT device according to claim 9, characterized in that: Also includes: a drain conductive region, the drain conductive region being on the first surface; as well as A second dielectric region is on the first surface and the insulating layer and is in contact with the drain conductive region.

11. The HEMT device according to claim 10, characterized in that: Also includes: a field plate, the field plate being on the first dielectric region and the second dielectric region, spaced apart from the gate conductive region, and spaced apart from the drain conductive region; as well as A third dielectric region is formed on the field plate, the second dielectric region, and the first dielectric region.

12. The HEMT device according to claim 11, characterized in that: The source conductive region is partially on the conductivity enhanced region, and the drain conductive region is partially on the second dielectric region.

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