A circuit for outputting positive and negative analog voltage amplitudes based on PWM control

Abstract

The utility model discloses a circuit for outputting positive and negative analog voltage amplitudes based on PWM control, including an integral sampling circuit, an integral sampling circuit electrically connected to a first reverse amplifier circuit, the first reverse amplifier circuit electrically connected to a follower circuit, and the follower circuit electrically connected to a second reverse amplifier circuit. The utility model can only use the timer function of a processor to realize the output of positive and negative analog voltages through an operational amplifier, and can control the output voltage amplitude through PWM, so that the voltage can realize stepless voltage regulation, simple control, and low cost.

Description

Technical Field

[0001] The utility model relates to the field of electricity, and in particular to a circuit for outputting positive and negative analog voltage amplitudes based on PWM control. Background Art

[0002] The switch angle of the intelligent air vent requires motor control. The positive signal represents that the air vent needs to be opened, and the opening angle is determined by the analog value; the negative signal represents that the air vent needs to be closed, and the closing angle is also determined by the analog value.

[0003] Common analog output uses DA chips, and the processor controls the output of positive and negative voltage values ​​through SPI or data bus. This method requires complex hardware and software and is costly. Utility Model Content

[0004] In order to solve the above technical problems, the utility model discloses a circuit for outputting positive and negative analog voltage amplitudes based on PWM control.

[0005] A circuit for outputting positive and negative analog voltage amplitudes based on PWM control includes an integral sampling circuit, the integral sampling circuit is electrically connected to a first reverse amplifier circuit, the first reverse amplifier circuit is electrically connected to a follower circuit, and the follower circuit is electrically connected to a second reverse amplifier circuit.

[0006] As a further improvement, the integral sampling circuit includes a first amplifier U1, a positive electrode of the first amplifier U1 electrically connected to one end of the second capacitor C2 and one end of the sixth resistor R6, the other end of the second capacitor C2 is grounded, the other end of the sixth resistor R6 is electrically connected to one end of the first capacitor C1 and one end of the fifth resistor R5, the other end of the first capacitor C1 is grounded, the other end of the fifth resistor R5 is electrically connected to one end of the first resistor R1, one end of the eighth resistor R8 and the PWM input signal; the other end of the first resistor R1 is electrically connected to the positive electrode of the V3P3 power supply, and the other end of the eighth resistor R8 is grounded; the negative electrode of the first amplifier U1 is electrically connected to the output end of the first amplifier U1.

[0007] A further improvement is that the first reverse amplifier circuit includes a second amplifier U2, the negative electrode of the second amplifier U2 is electrically connected to one end of the seventh resistor R7 and one end of the second resistor R2, and the other end of the seventh resistor R7 is electrically connected to the output end of the first amplifier U1; the other end of the second resistor R2 is electrically connected to the output end of the second amplifier U2, the positive electrode of the second amplifier U2 is electrically connected to one end of the eleventh resistor R11, and the other end of the eleventh resistor R11 is grounded.

[0008] As a further improvement, the follower circuit includes a third amplifier U3, the positive electrode of the third amplifier U3 is electrically connected to one end of the ninth resistor R9 and one end of the third resistor R3, the other end of the ninth resistor R9 is electrically connected to the output end of the second amplifier U2, the other end of the third resistor R3 is electrically connected to the V3P3 power supply, and the negative electrode of the third amplifier U3 is electrically connected to the output end of the third amplifier U3.

[0009] As a further improvement, the second reverse amplifier circuit includes a fourth amplifier U4, a negative electrode of the fourth amplifier U4 being electrically connected to one end of the tenth resistor R10 and one end of the fourth resistor R4; the other end of the tenth resistor R10 being electrically connected to the output end of the third amplifier U3, and the other end of the fourth resistor R4 being electrically connected to the output end of the fourth amplifier U4; the positive electrode of the fourth amplifier U4 being electrically connected to one end of the twelfth resistor R12, and the other end of the twelfth resistor R12 being grounded.

[0010] As a further improvement, the output signal of the second amplifier U2 is denoted as Um, the voltage of the V3P3 power supply is 3.3V, when |Um|>3.3V, the output voltage Uo of the fourth amplifier U4 is positive, and when |Um|<3.3V, the output voltage Uo of the fourth amplifier U4 is negative.

[0011] Further improvement, Uo = -1 / 2*(R4' / R10'+1)(3.3+Um)

[0012] Um=-Upwm*(R2' / R7'+1)

[0013] 0<Upwm<3.3, Upwm is the average voltage of the PWM signal;

[0014] Wherein, R2' is the resistance value of the second resistor, R7' is the resistance value of the seventh resistor, R4' is the resistance value of the fourth resistor, and R10' is the resistance value of the tenth resistor.

[0015] For further improvement, R2' is 20k, R7' is 10k, R4' is 13.3k, and R10' is 2k.

[0016] As a further improvement, the first amplifier U1, the second amplifier U2, the third amplifier U3 and the fourth amplifier U4 are all of model TP2274.

[0017] As a further improvement, the amplification factor of the first reverse amplifier circuit is -3 times, and the amplification factor of the second reverse amplifier circuit is -7.65 times.

[0018] The beneficial effects of the utility model are:

[0019] The utility model can only use the timer function of the processor to realize the output of positive and negative analog voltages through the operational amplifier, and can control the output voltage amplitude through PWM, the voltage can realize stepless voltage regulation, the control is simple and the cost is low. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] Figure 1 This is the circuit diagram of the utility model. DETAILED DESCRIPTION

[0021] The following is a further description of the implementation of the utility model in conjunction with the accompanying drawings and examples. It should be noted that the examples do not limit the scope of protection claimed by the utility model.

[0022] Example 1

[0023] like Figure 1 As shown, when PWM_IN is at a high level, it is pulled up to the V3P3 power supply through a 22k resistor R1, and when it is at a low level, it is pulled down to the power ground through a 22k resistor R8. Resistors R1 and R8 are used to ensure that the level signal of PWM_IN is of standard amplitude to reduce the difference in analog quantity after integration; resistor R5 of 22k and capacitor C1 of 1nF are used to integrate the PWM signal, resistor R6 of 22k and capacitor C2 of 1nF are used to perform secondary integration on the first-stage integrated signal, and the signal is sampled and output by a follower made of TP2274 operational amplifier U1.

[0024] The follower output voltage is reversely amplified by the 10k resistor R7, the 20k resistor R2, the 10k resistor R11 and the TP2274 operational amplifier U2, with an amplification factor of -3 times. The output signal at this time is recorded as Um. After the above two steps, the positive voltage of PWM_IN is converted into the corresponding negative voltage Um output.

[0025] The V3P3 power supply and Um (always negative) are divided by 2k resistors R3 and R9 and then input to the follower made of TP2274 op amp U3. Since Um is a negative voltage, when |Um|>V3P3, the voltage divider resistors R3 and R9 output a negative voltage; when |Um|<V3P3, the voltage divider resistor outputs a positive voltage.

[0026] The signal is reversely amplified by 2k resistor R10, 2k resistor R12, 13.3k resistor R4 and TP2274 operational amplifier U4, with an amplification factor of -7.65. The output voltage is Uo. When |Um|>V3P3, the output is positive; when |Um|<V3P3, the output voltage is negative.

[0027] Uo=-1 / 2*(R4 / R10+1)(3.3+Um)

[0028] Um=-Upwm*(R2 / R7+1)

[0029] Uo=11.475Upwm-12.6225(0<Upwm(average voltage)<3.3)

[0030] The PWM signal of the processor is converted into a DC signal after two-stage RC filtering, and the impedance is transformed through the follower. After reverse amplification, the DC signal is amplified and converted into a negative voltage marked as Um; the positive and negative voltages of V3P3 are divided by resistors and enter the follower, and then the Uo analog voltage is output through the reverse amplifier.

[0031] Since Um is a negative voltage value, when |Um|>V3P3, the voltage divider resistor output is a negative voltage and Uo output is a positive voltage value; when |Um|<V3P3, the voltage divider resistor output is a positive voltage and Uo output is a negative voltage value.

[0032] And Uo changes linearly with the linear change of PWM. The circuit user can change the output range by changing the supply voltage and amplification factor of the op amp.

[0033] Finally, it should be noted that the above embodiments are only used to illustrate the technical solution of the utility model rather than to limit it. Although the utility model has been described in detail with reference to the preferred embodiments, ordinary technicians in the field should understand that the technical solution of the utility model can be modified or replaced by equivalents without departing from the purpose and scope of the technical solution of the utility model, which should be included in the scope of the claims of the utility model.

Claims

1. A circuit for outputting positive and negative analog voltage amplitudes based on PWM control, characterized in that: It includes an integral sampling circuit, the integral sampling circuit is electrically connected to a first reverse amplifier circuit, the first reverse amplifier circuit is electrically connected to a follower circuit, and the follower circuit is electrically connected to a second reverse amplifier circuit.

2. The circuit for outputting positive and negative analog voltage amplitudes based on PWM control as claimed in claim 1, characterized in that: The integral sampling circuit comprises a first amplifier (U1), a positive electrode of the first amplifier (U1) being electrically connected to one end of a second capacitor (C2) and one end of a sixth resistor (R6), the other end of the second capacitor (C2) being grounded, the other end of the sixth resistor (R6) being electrically connected to one end of the first capacitor (C1) and one end of a fifth resistor (R5), the other end of the first capacitor (C1) being grounded, the other end of the fifth resistor (R5) being electrically connected to one end of the first resistor (R1), one end of an eighth resistor (R8) and a PWM input signal; the other end of the first resistor (R1) being electrically connected to the positive electrode of a V3P3 power supply, the other end of the eighth resistor (R8) being grounded; and the negative electrode of the first amplifier (U1) being electrically connected to the output end of the first amplifier (U1).

3. The circuit for outputting positive and negative analog voltage amplitudes based on PWM control as claimed in claim 2, characterized in that: The first reverse amplifier circuit comprises a second amplifier (U2), a negative electrode of the second amplifier (U2) being electrically connected to one end of a seventh resistor (R7) and one end of a second resistor (R2), and the other end of the seventh resistor (R7) being electrically connected to the output end of the first amplifier (U1); the other end of the second resistor (R2) being electrically connected to the output end of the second amplifier (U2), a positive electrode of the second amplifier (U2) being electrically connected to one end of an eleventh resistor (R11), and the other end of the eleventh resistor (R11) being grounded.

4. The circuit for outputting positive and negative analog voltage amplitudes based on PWM control as claimed in claim 3, characterized in that: The follower circuit comprises a third amplifier (U3), a positive electrode of the third amplifier (U3) being electrically connected to one end of a ninth resistor (R9) and one end of a third resistor (R3), the other end of the ninth resistor (R9) being electrically connected to the output end of the second amplifier (U2), the other end of the third resistor (R3) being electrically connected to a V3P3 power supply, and a negative electrode of the third amplifier (U3) being electrically connected to the output end of the third amplifier (U3).

5. The circuit for outputting positive and negative analog voltage amplitudes based on PWM control as claimed in claim 4, characterized in that: The second reverse amplifier circuit comprises a fourth amplifier (U4), a negative electrode of the fourth amplifier (U4) being electrically connected to one end of a tenth resistor (R10) and one end of a fourth resistor (R4); the other end of the tenth resistor (R10) being electrically connected to the output end of the third amplifier (U3), and the other end of the fourth resistor (R4) being electrically connected to the output end of the fourth amplifier (U4); a positive electrode of the fourth amplifier (U4) being electrically connected to one end of a twelfth resistor (R12), and the other end of the twelfth resistor (R12) being grounded.

6. The circuit for outputting positive and negative analog voltage amplitudes based on PWM control as claimed in claim 5, characterized in that: The output signal of the second amplifier (U2) is denoted as Um, the voltage of the V3P3 power supply is 3.3V, when |Um|>3.3V, the output voltage Uo of the fourth amplifier (U4) is positive, and when |Um|<3.3V, the output voltage Uo of the fourth amplifier (U4) is negative.

7. The circuit for outputting positive and negative analog voltage amplitudes based on PWM control as claimed in claim 6, characterized in that: Uo=-1 / 2*(R4' / R10'+1)(3.3+Um) Um=-Upwm*(R2' / R7'+1) 0<Upwm<3.3, Upwm is the average voltage of the PWM signal; Wherein, R2' is the resistance value of the second resistor, R7' is the resistance value of the seventh resistor, R4' is the resistance value of the fourth resistor, and R10' is the resistance value of the tenth resistor.

8. The circuit for outputting positive and negative analog voltage amplitudes based on PWM control as claimed in claim 7, characterized in that: R2' is 20k, R7' is 10k, R4' is 13.3k, and R10' is 2k.

9. The circuit for outputting positive and negative analog voltage amplitudes based on PWM control as claimed in claim 5, characterized in that: The first amplifier (U1), the second amplifier (U2), the third amplifier (U3) and the fourth amplifier (U4) are all TP2274.

10. The circuit for outputting positive and negative analog voltage amplitudes based on PWM control as claimed in claim 1, characterized in that: The amplification factor of the first reverse amplifier circuit is -3 times, and the amplification factor of the second reverse amplifier circuit is -7.65 times.

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