Circuit structure

Abstract

A circuit structure is mainly characterized in that a seed crystal layer formed by a plurality of discontinuous metal blocks is formed on a dielectric layer, and a circuit layer is formed on the seed crystal layer through electroplating, so that the combination effect of the seed crystal layer and the circuit layer arranged on the seed crystal layer is enhanced through overall surface roughening and relative concave-convex structures of the plurality of discontinuous metal blocks. Therefore, the problem of delamination is avoided, and the process yield is improved.

Description

Technical Field

[0001] The present application relates to a semiconductor manufacturing process, and more particularly to a circuit structure and a manufacturing method thereof. Background Art

[0002] With the rapid development of the electronics industry, electronic products tend to be thinner, lighter, shorter and smaller in shape, and their functions are developing in the direction of high performance, high functionality and high speed. Therefore, in order to meet the needs of high integration and miniaturization of semiconductor devices, semiconductor chips and substrates need to have high-density and fine-pitch circuit layers.

[0003] Furthermore, fan-out packaging technology has become an important trend in the future development of 5G and advanced packaging. The redistribution layer (RDL) can achieve more I / O and thinner semiconductor devices, so it has become a development focus of the semiconductor industry.

[0004] The aforementioned RDL process mainly involves first laying a whole seed layer on the dielectric layer, and then using the seed layer as a current conduction path to electroplate a circuit layer thereon. Subsequently, another dielectric layer and a circuit layer may be stacked on this circuit layer in sequence to form a multi-layer RDL structure to meet the high integration and miniaturization requirements of semiconductor devices.

[0005] However, as the number of RDL layers increases, the problem of delamination due to stress between layers in the manufacturing process arises.

[0006] Therefore, how to overcome the above-mentioned problems of the prior art has become a topic that needs to be solved urgently. Utility Model Content

[0007] In view of the above-mentioned deficiencies of the prior art, the present application provides a circuit structure, including: a dielectric layer; a seed layer disposed on the dielectric layer, wherein the seed layer is composed of a plurality of discontinuous metal blocks; and a circuit layer disposed on the seed layer.

[0008] The present application also provides a method for manufacturing a circuit structure, comprising: providing a dielectric layer; forming a seed layer on the dielectric layer, wherein the seed layer is composed of a plurality of discontinuous metal blocks; and forming a circuit layer on the seed layer.

[0009] In the aforementioned circuit structure and its manufacturing method, the spacing between each of the multiple non-continuous metal blocks is the same; the size of each of the multiple non-continuous metal blocks is the same; the spacing between each of the multiple non-continuous metal blocks is different; or the size of each of the multiple non-continuous metal blocks is different.

[0010] In the aforementioned circuit structure and its manufacturing method, the circuit layer includes a plurality of conductive circuits, and each of the conductive circuits covers a portion of the plurality of non-continuous metal blocks.

[0011] In the aforementioned circuit structure and its manufacturing method, the method of manufacturing the seed layer first forms a whole metal layer on the dielectric layer, and then performs an etching process on the metal layer to form a plurality of discontinuous metal blocks.

[0012] In the aforementioned circuit structure and its manufacturing method, the method of manufacturing the seed layer directly forms a plurality of non-continuous metal blocks on the dielectric layer.

[0013] The aforementioned circuit structure and its manufacturing method also include forming a patterned resist layer on the dielectric layer and the plurality of discontinuous metal blocks, wherein the resist layer has a plurality of openings.

[0014] The aforementioned circuit structure and its manufacturing method also include electroplating to form the circuit layer on the plurality of discontinuous metal blocks that expose the resistance layer opening.

[0015] The aforementioned circuit structure and its manufacturing method also include removing the resistance layer and the portions of the plurality of non-continuous metal blocks covered by the resistance layer.

[0016] The aforementioned circuit structure and its manufacturing method also include: stacking another dielectric layer on the circuit layer; forming another seed layer composed of multiple non-continuous metal blocks on the other dielectric layer; and forming another circuit layer on the other seed layer.

[0017] In the aforementioned circuit structure and its manufacturing method, the other circuit layer includes a plurality of other conductive circuits, and the line width / line spacing of each of the other conductive circuits is smaller than the line width / line spacing of each of the conductive circuits in the circuit layer.

[0018] In the aforementioned circuit structure and manufacturing method thereof, the size and spacing of the plurality of discontinuous metal blocks under each of the other conductive circuits are smaller than the size and spacing of the plurality of discontinuous metal blocks under each of the conductive circuits.

[0019] As can be seen from the above, the circuit structure of the present application mainly forms a seed layer composed of multiple non-continuous metal blocks on the dielectric layer, and electroplates the circuit layer on the seed layer, so as to strengthen the bonding effect between the seed layer and the circuit layer arranged thereon through the overall surface roughening and relative concave-convex structure of multiple non-continuous metal blocks (seed layer), thereby improving the existing problem of delamination caused by stress between layers and improving the process yield. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] Figures 1A to 1E It is a cross-sectional schematic diagram of the manufacturing method of the circuit structure of the present application.

[0021] Figure 1B-1 and Figure 1B-2 for Figure 1B Schematic cross-sectional view of other embodiments.

[0022] Figure 2 It is a cross-sectional schematic diagram of another embodiment of the circuit structure of the present application.

[0023] Main component symbols

[0024] 1,2 Line structure

[0025] 10 Dielectric layer

[0026] 11 Metal Layer

[0027] 11a Seed layer

[0028] 110,210 Metal Blocks

[0029] 12. Barrier layer

[0030] 120 Opening

[0031] 13 Circuit layer

[0032] 130 Conductive circuit

[0033] 20 Another dielectric layer

[0034] 21a Another seed layer

[0035] 23 Another circuit layer

[0036] 230 Another conductive line

[0037] d spacing. DETAILED DESCRIPTION

[0038] The following describes the implementation methods of the present application through specific embodiments. Those skilled in the art can easily understand other advantages and effects of the present application from the contents disclosed in this specification.

[0039] It should be noted that the structures, proportions, sizes, etc. illustrated in the drawings attached to this specification are only used to match the contents disclosed in the specification for the understanding and reading of those skilled in the art, and are not used to limit the limiting conditions for the implementation of this application, so they have no substantial technical significance. Any modification of the structure, change in the proportional relationship, or adjustment of the size, without affecting the effects and purposes that can be achieved by this application, should still fall within the scope of the technical content disclosed in this application. At the same time, the terms such as "on", "first", "second", "one", etc. cited in this specification are only for the convenience of narration, and are not used to limit the scope of the implementation of this application. The change or adjustment of their relative relationship should also be regarded as the scope of the implementation of this application without substantially changing the technical content.

[0040] Figures 1A to 1E It is a cross-sectional schematic diagram of a first embodiment of a method for manufacturing a circuit structure 1 of the present application.

[0041] like Figure 1A As shown, a dielectric layer 10 is provided, and a whole metal layer 11 is deposited on the dielectric layer 10 .

[0042] The dielectric layer 10 is formed of a material such as Ajinomoto build-up film (ABF), polybenzoxazole (PBO), polyimide (PI), glass fiber prepreg (PP) or other dielectric materials. The metal layer 11 is formed of a material such as copper metal (the metal layer 11 is the seed layer in the prior art).

[0043] The metal layer 11 may be formed by a sputtering process, a physical vapor deposition (PVD) process, or other suitable processes.

[0044] like Figure 1B As shown, the metal layer 11 is subjected to an etching process (dry etching or wet etching) to form a plurality of discontinuous metal blocks 110. The plurality of discontinuous metal blocks 110 constitute the seed layer 11a of the present application.

[0045] In this embodiment, the spacing d between each of the plurality of non-continuous metal blocks 110 may be the same, and the size of each of the plurality of non-continuous metal blocks 110 may also be the same. In another embodiment, the spacing d between each of the plurality of non-continuous metal blocks 110 may be different from each other (e.g. Figure 1B-1 In another embodiment, the sizes of the plurality of non-continuous metal blocks 110 may be different (eg Figure 1B-2 shown).

[0046] In addition, in other embodiments, it is also possible to omit Figure 1A In the step of forming a plurality of discontinuous metal blocks 110 directly on the dielectric layer 10 as a seed layer 11a (such as Figure 1B as shown), for example, by doping methods such as ion implantation.

[0047] like Figure 1C As shown, a patterned resist layer 12 is formed on the dielectric layer 10 and the plurality of discontinuous metal blocks 110 (seed layer 11 a ). The resist layer 12 has a plurality of openings 120 to expose portions of the plurality of discontinuous metal blocks 110 (seed layer 11 a ).

[0048] like Figure 1D As shown, the plurality of discontinuous metal blocks 110 (seed layer 11 a ) are used as current conduction paths to form a circuit layer 13 by electroplating on the plurality of discontinuous metal blocks 110 (seed layer 11 a ) that expose the resist opening 120 .

[0049] The circuit layer 13 includes a plurality of conductive circuits 130 , wherein each of the conductive circuits 130 covers a portion of the plurality of non-continuous metal blocks 110 .

[0050] like Figure 1E As shown, the resist layer 12 and the portions of the plurality of discontinuous metal blocks 110 covered by the resist layer 12 are removed to obtain the circuit structure 1 of the present application, wherein the circuit structure 1 can be applied to circuits of semiconductor devices related to semiconductor chips, substrates or interposers.

[0051] See also Figure 2 , is a cross-sectional schematic diagram of another embodiment of the circuit structure 2 of the present application, which mainly continues to stack another dielectric layer 20 on the circuit layer 13 using the circuit redistribution layer (RDL) specification, and refers to the aforementioned manufacturing method to form another seed layer 21a composed of multiple non-continuous metal blocks 210 on the other dielectric layer 20, and then form another circuit layer 23 on the other seed layer 21a.

[0052] In addition, more dielectric layers and circuit layers may be stacked on the other circuit layer 23 , and the seed layers between the stacked dielectric layers and circuit layers are composed of a plurality of discontinuous metal blocks.

[0053] Furthermore, the other circuit layer 23 can be electrically connected to the circuit layer 13 through a plurality of conductive blind vias (not shown) disposed in the other dielectric layer 20 .

[0054] In this embodiment, the other circuit layer 23 includes multiple other conductive circuits 230, wherein the line width / line spacing of each other conductive circuit 230 is smaller than the line width / line spacing of each conductive circuit 130, and the size and spacing of the multiple non-continuous metal blocks 210 covering each other conductive circuit 230 are smaller than the size and spacing of the multiple non-continuous metal blocks 110 covering each conductive circuit 130.

[0055] Through the above-mentioned manufacturing method, the present application also provides a circuit structure 1, 2, including: a dielectric layer 10; a seed layer 11a, disposed on the dielectric layer 10, wherein the seed layer 11a is composed of a plurality of non-continuous metal blocks 110; and a circuit layer 13, disposed on the seed layer 11a.

[0056] The circuit layer 13 includes a plurality of conductive circuits 130 , wherein each of the conductive circuits 130 covers a portion of the plurality of non-continuous metal blocks 110 .

[0057] The circuit structure 2 further includes another dielectric layer 20 ; another seed layer 21 a formed on the other dielectric layer 20 and composed of a plurality of discontinuous metal blocks 210 ; and another circuit layer 23 formed on the other seed layer 21 a .

[0058] In summary, the circuit structure and manufacturing method of the present application mainly form a seed layer composed of multiple non-continuous metal blocks on the dielectric layer, and electroplate the circuit layer on the seed layer, so as to strengthen the bonding effect between the seed layer and the circuit layer arranged thereon through the overall surface roughening and relative concave-convex structure of the multiple non-continuous metal blocks (seed layer), thereby improving the existing problem of delamination caused by stress between layers and improving the process yield.

[0059] The above embodiments are used to illustrate the principles and effects of the present application, but are not used to limit the present application. Any person skilled in the art may modify the above embodiments without violating the spirit and scope of the present application. Therefore, the scope of protection of the present application should be as listed in the claims.

Claims

1. A circuit structure, characterized in that: include: Dielectric layer; A seed layer is disposed on the dielectric layer, wherein the seed layer is composed of a plurality of discontinuous metal blocks; as well as The circuit layer is disposed on the seed layer.

2. The circuit structure according to claim 1, characterized in that: The intervals between each of the plurality of non-continuous metal blocks are the same.

3. The circuit structure according to claim 1, characterized in that: The sizes of each of the plurality of non-continuous metal blocks are the same.

4. The circuit structure according to claim 1, characterized in that: The intervals between each of the plurality of non-continuous metal blocks are different.

5. The circuit structure according to claim 1, characterized in that: The sizes of each of the plurality of non-continuous metal blocks are different.

6. The circuit structure according to claim 1, characterized in that: The circuit layer includes a plurality of conductive circuits, and each of the conductive circuits covers a portion of the plurality of discontinuous metal blocks.

7. The circuit structure according to claim 1, characterized in that: The line structure also includes: another dielectric layer; another seed layer formed on the another dielectric layer and composed of a plurality of discontinuous metal blocks; and Another circuit layer is formed on the another seed layer.

8. The circuit structure according to claim 7, characterized in that: The other circuit layer includes a plurality of other conductive circuits, and the line width / line spacing of each of the other conductive circuits is smaller than the line width / line spacing of each of the conductive circuits in the circuit layer.

9. The circuit structure according to claim 8, characterized in that: The size and spacing of some of the multiple non-continuous metal blocks under each of the other conductive circuits are smaller than the size and spacing of some of the multiple non-continuous metal blocks under each of the conductive circuits.

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