High reliability external watchdog circuit with controllable reset duration for data collector

Abstract

The utility model relates to a high-reliability external watchdog circuit with controllable reset time for a collector, comprising a PWM transmission pin WDI, a reset pin RST, a logic counter D1, MOS tubes Q1, Q2, capacitors C1, C3, C4, C5, resistors R1, R5, R6, R7, power supplies VCC, VDD, GND; wherein the PWM transmission pin WDI is connected to the resistor R1 and the capacitor C1; the other end of the resistor R1 is connected to the power supply VCC; the capacitor C1 is connected to the logic counter D1-RST; the utility model has reasonable design, compact structure and convenient use.

Description

Technical Field

[0001] The utility model relates to a high-reliability external watchdog circuit with controllable reset time for a collector. Background Art

[0002] The survey found that in most external watchdog circuit designs, external watchdog chips are used. The watchdog chip feeding signal WDI is usually directly connected to the signal source of the embedded system, and the reset output pin RST of the watchdog chip is connected to the reset pin of the main control chip. When the main control chip cannot feed the dog in time within the built-in overflow time range, it will trigger the logic of the reset pin of the watchdog chip to flip, thereby resetting the main control chip. However, most external watchdog circuits cannot flexibly adjust the reset pulse width, especially when the power-on starts, the watchdog timing cannot be disabled, resulting in power-on timing overflow, and abnormalities such as repeated power-on of the system will occur. In addition, the external watchdog circuit built with the watchdog chip often cannot filter the frequency range of the PWM feeding signal input by the main control chip, and mostly adopts a direct connection method with poor anti-interference ability. Some methods using tri-state buffers greatly increase the cost of peripheral circuits. If the watchdog chip is fed when the timing does not overflow, the logic of the watchdog output signal can be kept unchanged. If the timer overflows and the dog is not fed, the output signal will flip to achieve the reset function.

[0003] The biggest disadvantage of the above circuit application is that some large operating systems, such as some acquisition terminals, have signal lag when they are just powered on, which causes reset phenomenon. In addition, because the working environment of the collector is mostly a complex outdoor environment, it is common for electromagnetic interference to cause abnormal output of the dog feeding signal. At this time, once the environment interferes, the mechanical reset of the field operation terminal may have a huge impact on the normal operation of the product. At this time, it is necessary to design an external watchdog circuit that can flexibly configure the reset time or power supply time of the embedded operating system. Utility Model Content

[0004] The technical problem to be solved by the utility model is generally to provide a high-reliability external watchdog circuit with controllable reset time for a collector.

[0005] In order to solve the above problems, the technical solution adopted by the utility model is:

[0006] A high-reliability external watchdog circuit with controllable reset time for a collector, comprising a PWM transmission pin WDI, a reset pin RST, a logic counter D1, MOS tubes Q1, Q2, capacitors C1, C3, C4, C5, resistors R1, R5, R6, R7, and power supplies VCC, VDD, and GND;

[0007] Among them, the PWM sending pin WDI is connected to the resistor R1 and the capacitor C1; the other end of the resistor R1 is connected to the power supply VCC;

[0008] Capacitor C1 is connected to the RST terminal of logic counter D1;

[0009] The VCC end of the logic counter D1 is connected to the power supply VCC and the capacitor C3, and the other end of the capacitor C3 is connected to GND. The Q13 end of the logic counter D1 is connected to the reset pin RST, the reset pin RST is connected to the resistor R5 and the gate of the MOS tube Q2, the source of the MOS tube is connected to GND, the drain of the MOS tube Q1 is connected to the resistor R7, and the other end of the resistor R7 is connected to the power supply VDD, the other end of the resistor R5 is connected to the resistor R6 and the gate of the MOS tube Q1, the drain of the MOS tube Q1 is connected to the capacitor C4 and the power supply VDD, the other end of the capacitor C4 is connected to GND, the source of the MOS tube Q1 is connected to the other end of the resistor R6, the capacitor C5, and the power supply VCC, and the other end of the capacitor C5 is connected to GND.

[0010] The capacitor C1 is also connected to a resistor R4 and a diode VD1 respectively. The other end of the resistor R4 is connected to GND. The other end of the diode VD1 is connected to GND. The GND end of the logic counter D1 is connected to GND.

[0011] The dog circuit also includes resistors R2, R3 and capacitor C2; resistor R2 is electrically connected to resistor R3 and capacitor C2 respectively; the other end of resistor R2 is connected to the CIN end of logic counter D1, the other end of resistor R3 is connected to the COUT end of logic counter D1, and the other end of capacitor C2 is connected to the COUT end of logic counter D1.

[0012] The utility model designs a high-reliability external watchdog circuit with controllable reset time for a collector. The circuit can flexibly configure the reset time or power supply time of the embedded system at the output end, and connects a first-order CR passive high-pass filter circuit at the input end to ensure the high reliability of the reset system, and can avoid abnormal reset of the watchdog circuit caused by external environmental interference or when the embedded system program itself runs away. The circuit design is novel and reasonable. It uses a low-cost logic counter and adds a peripheral RC circuit to replace the expensive external watchdog device. At the same time, it has the advantage of flexible timing of logic devices, which greatly improves the effectiveness and reliability of the reset and restart operations of the embedded system. This solution is suitable for the promotion and use of various types of collection terminals and a wider range of embedded operating platforms.

[0013] The high-reliability external watchdog circuit with controllable reset time for the collector comprises a first-order CR passive high-pass filter circuit, a timing reset circuit and a reset output control power-off circuit.

[0014] In view of the technical problems of the background technology, the collector of the present application has a high-reliability external watchdog circuit with controllable reset time, and its reset time is controllable, which avoids the reset phenomenon caused by the delay of the dog feeding signal when the system is just powered on, thereby ensuring the normal operation of the on-site operation terminal. At the same time, it abandons the more expensive method of using a three-state gate buffer on the market to maintain the normal operation of the watchdog circuit. The design cleverly uses lower-cost discrete devices to build a first-order CR high-pass filter circuit to achieve three-state buffering and has strong anti-interference ability, and greatly reduces the cost of the external watchdog circuit.

[0015] The utility model has the advantages of reasonable design, low cost, firmness and durability, safety and reliability, simple operation, time-saving, labor-saving, money-saving, compact structure and convenient use. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figure 1 The utility model is a schematic diagram of a high-reliability external watchdog circuit with controllable reset time. DETAILED DESCRIPTION

[0017] like Figure 1 As shown, the high-reliability external watchdog circuit with controllable reset time for the collector in this embodiment includes a PWM sending pin WDI, a reset pin RST, a logic counter D1, MOS tubes Q1, Q2, capacitors C1, C2, C3, C4, C5, resistors R1, R2, R3, R4, R5, R6, R7, a diode VD1, and power supplies VCC, VDD, and GND. The connection relationship is as follows: the PWM sending pin WDI is connected to the resistor R1 and the capacitor C1, the other end of the resistor R1 is connected to the power supply VCC, the capacitor C1 is connected to the resistor R4, the diode VD1, and the RST end of the logic counter D1, the other end of the resistor R4 is connected to GND, the other end of VD1 is connected to GND, the GND end of the logic counter D1 is connected to GND, the resistor R2 is connected to the resistor R3 and the capacitor C2, the other end of the resistor R2 is connected to the CIN end of the logic counter D1, the other end of R3 is connected to the COUT end of the logic counter D1, the other end of C2 is connected to the COUT end of the logic counter D1, and the VCC end of the logic counter D1 is connected The power supply VCC and capacitor C3, the other end of C3 is connected to GND, the Q13 end of the logic counter D1 is connected to the reset pin RST, the reset pin RST is connected to the resistor R5 and the gate of the MOS tube Q2, the source of the MOS tube is connected to GND, the drain of the MOS tube is connected to the resistor R7, the other end of the resistor R7 is connected to the power supply VDD, the other end of the resistor R5 is connected to the resistor R6 and the gate of the MOS tube Q1, the drain of the MOS tube Q1 is connected to the capacitor C4 and the power supply VDD, the other end of the capacitor C4 is connected to GND, the source of the MOS tube Q1 is connected to the other end of the resistor R6, the capacitor C5, and the power supply VCC, and the other end of the capacitor C5 is connected to GND.

[0018] For example, the values ​​of the resistor R3 and capacitor C2 can be adjusted according to the differences in signal lag time when different types of operating systems are just powered on, so as to achieve flexible and controllable reset output time. After the PWM sending pin WDI is input, it passes through the first-order CR passive high-pass filter circuit. By adjusting the parameters of capacitor C1 and resistor R4, different high-pass filter cutoff frequencies can be set to ensure that the PWM signal output by the system can only pass without distortion when it is higher than the set cutoff frequency, ensuring that the logic counter count is reset. When the input PWM signal frequency is lower than the high-pass cutoff frequency, for example, when the system is interfered by the external environment and the program runs away, the PWM signal output is continuously high or low. After the set delay, the logic counter timeout overflow will be triggered to achieve system reset. The above design method has strong anti-interference ability and extremely low cost of peripheral circuit design.

[0019] Beneficial effects of the utility model: The utility model provides a high-reliability external watchdog circuit with controllable reset time for a collector, wherein the PWM pulse signal input end is connected to a first-order CR passive high-pass filter circuit constructed with discrete devices, and the cutoff frequency of the high-pass filter circuit can be adjusted by adjusting the parameters of the resistor and the capacitor, so that the input PWM signal frequency can be controlled, which greatly improves the anti-interference performance of the embedded operating system working in a complex environment. In addition, due to its simple structure and low implementation cost, it is suitable for promotion and use in various types of acquisition terminals and a wider range of embedded operating platforms. At the reset output end, the resistor and capacitor parameters can be adjusted according to the differences in signal lag time when different types of operating systems are just powered on, so as to achieve flexible and controllable reset output time and avoid timeout reset when the system is powered on.

[0020] The present invention is fully described for a clearer disclosure, and the prior art will not be listed one by one.

[0021] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the utility model, rather than to limit it; although the utility model is described in detail with reference to the above embodiments, ordinary technicians in this field should understand that they can still modify the technical solutions recorded in the above embodiments, or replace some of the technical features therein with equivalents; it is obvious for those skilled in the art to combine multiple technical solutions of the utility model. However, these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the spirit and scope of the technical solutions of the embodiments of the utility model.

Claims

1. A high-reliability external watchdog circuit with controllable reset time for a collector, characterized by: Including PWM transmission pin WDI, reset pin RST, logic counter D1, MOS tubes Q1, Q2, capacitors C1, C3, C4, C5, resistors R1, R5, R6, R7, power supplies VCC, VDD, GND; Among them, the PWM sending pin WDI is connected to the resistor R1 and the capacitor C1; the other end of the resistor R1 is connected to the power supply VCC; Capacitor C1 is connected to the RST terminal of logic counter D1; The VCC end of the logic counter D1 is connected to the power supply VCC and the capacitor C3, and the other end of the capacitor C3 is connected to GND. The Q13 end of the logic counter D1 is connected to the reset pin RST, the reset pin RST is connected to the resistor R5 and the gate of the MOS tube Q2, the source of the MOS tube is connected to GND, the drain of the MOS tube Q1 is connected to the resistor R7, and the other end of the resistor R7 is connected to the power supply VDD, the other end of the resistor R5 is connected to the resistor R6 and the gate of the MOS tube Q1, the drain of the MOS tube Q1 is connected to the capacitor C4 and the power supply VDD, the other end of the capacitor C4 is connected to GND, the source of the MOS tube Q1 is connected to the other end of the resistor R6, the capacitor C5, and the power supply VCC, and the other end of the capacitor C5 is connected to GND.

2. The high-reliability external watchdog circuit with controllable reset time for a collector according to claim 1, characterized in that: The capacitor C1 is also connected to a resistor R4 and a diode VD1 respectively. The other end of the resistor R4 is connected to GND. The other end of the diode VD1 is connected to GND. The GND end of the logic counter D1 is connected to GND.

3. The high-reliability external watchdog circuit with controllable reset time for a collector according to claim 2, characterized in that: The dog circuit also includes resistors R2, R3 and capacitor C2; resistor R2 is electrically connected to resistor R3 and capacitor C2 respectively; the other end of resistor R2 is connected to the CIN end of logic counter D1, the other end of resistor R3 is connected to the COUT end of logic counter D1, and the other end of capacitor C2 is connected to the COUT end of logic counter D1.

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