Metal oxide semiconductor field effect transistor structure

Abstract

The utility model provides a metal oxide semiconductor field effect transistor structure. The field effect transistor structure comprises a substrate, an epitaxial layer, a first well region, a second well region, a current expansion layer, an equipotential ring region, a first source region, a second source region, a first channel region, a second channel region, a buffer layer, a first grid electrode and a second grid electrode. The epitaxial layer is formed on the substrate; the first well region, the second well region and the current expansion layer are formed at the upper part in the epitaxial layer; the current expansion layer is located between the first well region and the second well region; the equipotential ring region is formed at the upper part in the epitaxial layer and is at least partially positioned at the same side of the first well region, the second well region and the current expansion layer; the first source region and the second source region are respectively formed at the upper parts in the first well region and the second well region and are spaced from the current expansion layer; the first channel region and the second channel region are respectively formed by upper regions, close to the current expansion layer, in the first well region and the second well region; the first grid electrode and the second grid electrode are respectively positioned above the first channel region and the second channel region; the buffer layer is formed at the upper part of the middle area in the current expansion layer; the buffer layer and the equipotential ring region are connected or arranged at intervals.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to a metal oxide semiconductor field effect transistor structure. Background Art

[0002] In the field of power electronics, SiC MOSFET has developed rapidly in the past decade. Due to its high temperature, high frequency, high efficiency and other performance advantages, it has been widely used in motor drive, new energy power generation, smart grid and other scenarios. In these application contexts, the reliability of SiC MOSFET is a key issue and the most core factor affecting the safe and reliable operation of power electronic equipment. In order to further increase the switching frequency and reduce switching losses, dual-gate SiC MOSFET has been proposed in recent years. Compared with traditional planar devices, it has the same on-resistance and lower gate-drain charge. However, a key challenge facing dual-gate SiC MOSFET is the electric field concentration phenomenon caused by the gate corner exposed in the blocking state. The peak electric field of its oxide layer can reach more than 7MV, which reduces the reliability of the device gate oxide and leads to premature breakdown. In addition, both traditional planar and dual-gate SiC MOSFET have poor short-circuit reliability, and their short-circuit tolerance time is much lower than that of silicon devices. In practical applications, once a device short circuit is detected, the external circuit will trigger a protection mechanism to shut down the device, but during the time of triggering the protection, the device still needs to withstand a certain period of short-circuit current. Therefore, improving the short-circuit tolerance of SiC MOSFET from the perspective of device structure has also become a research focus. Utility Model Content

[0003] The embodiment of the present application provides a metal oxide semiconductor field effect transistor structure, which includes:

[0004] N-type substrate;

[0005] An N-type epitaxial layer formed on one side of the N-type substrate;

[0006] A P-type first well region and a P-type second well region are formed in an upper portion of the N-type epitaxial layer and are spaced apart from each other in a first direction;

[0007] An N-type current spreading layer, formed in an upper portion of the N-type epitaxial layer and located between the P-type first well region and the P-type second well region;

[0008] A P-type equipotential ring region is formed in the upper part of the N-type epitaxial layer and is at least partially located on the same side of the P-type first well region, the P-type second well region, and the N-type current spreading layer in the second direction; there is a non-zero angle between the first direction and the second direction, and the up-down direction is perpendicular to the plane determined by the first direction and the second direction;

[0009] An N-type first source region and an N-type second source region, wherein the N-type first source region is formed at an upper portion of the P-type first well region, the N-type second source region is formed at an upper portion of the P-type second well region, and both the N-type first source region and the N-type second source region are spaced apart from the N-type current spreading layer;

[0010] A first channel region and a second channel region, wherein the first channel region is formed by an upper region of the P-type first well region close to the N-type current spreading layer, and the second channel region is formed by an upper region of the P-type second well region close to the N-type current spreading layer;

[0011] a first gate and a second gate, the first gate being located above the first channel region, and the second gate being located above the second channel region;

[0012] A P-type buffer layer is formed on the upper part of the middle region in the N-type current spreading layer; wherein the P-type buffer layer is connected to or spaced from the P-type equipotential ring region.

[0013] In some embodiments, the ion doping concentration of the N-type current spreading layer is greater than or equal to the ion doping concentration of the N-type epitaxial layer; and the ratio between the ion doping concentration of the N-type current spreading layer and the ion doping concentration of the N-type epitaxial layer is 1-20.

[0014] In some embodiments, a ratio of a width of the P-type buffer layer in the first direction to a width of the N-type current spreading layer in the first direction is 0.2-0.5.

[0015] In some embodiments, a P-type first contact region is formed in the P-type first well region and is located on a side of the N-type first source region away from the N-type current spreading layer;

[0016] The P-type second well region is formed with a P-type second contact region located on a side of the N-type second source region away from the N-type current spreading layer.

[0017] In some embodiments, the P-type buffer layer, the P-type first contact region, and the P-type second contact region have the same ion doping concentration.

[0018] In some embodiments, the junction depths of the P-type buffer layer, the P-type first contact region, and the P-type second contact region are the same.

[0019] In some embodiments, the metal oxide semiconductor field effect transistor structure includes:

[0020] A first gate oxide layer and a second gate oxide layer, wherein the first gate oxide layer is located between the first channel region and the first gate, and the second gate oxide layer is located between the second channel region and the second gate.

[0021] In some embodiments, the metal oxide semiconductor field effect transistor structure includes: an interlayer dielectric layer covering the exposed portions of the first gate and the second gate and filling the gap between the first gate and the second gate;

[0022] In some embodiments, the metal oxide semiconductor field effect transistor structure includes:

[0023] A first source and a second source, wherein the first source is located in the N-type first source region, and the second source is located above the N-type second source region.

[0024] In some embodiments, the metal oxide semiconductor field effect transistor structure includes: a drain; located on a side of the N-type substrate away from the N-type epitaxial layer.

[0025] The main technical effects achieved by the embodiments of the present application are:

[0026] The metal oxide semiconductor field effect transistor structure provided by the embodiment of the present application improves the electric field distribution on the PN junction formed by the P-type first well region and the P-type second well region and the N-type current expansion layer, and the P-type first well region and the P-type second well region and the N-type epitaxial layer in the blocking state by forming a P-type buffer layer in the upper part of the middle region in the N-type current expansion layer, thereby improving the voltage resistance of the metal oxide semiconductor field effect transistor structure. If the P-type buffer layer is connected to the P-type equipotential ring region, the flow width of the third quadrant body diode can be increased, the conduction voltage drop of the body diode can be reduced, and the dead zone loss can be reduced when applied to power electronic converters. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] Figure 1 is a cross-sectional view of a metal oxide semiconductor field effect transistor structure provided by an exemplary embodiment of the present application;

[0028] Figure 2 is a top view of a partial structure of a metal oxide semiconductor field effect transistor structure provided by an exemplary embodiment of the present application;

[0029] Figure 3 is a top view of a partial structure of another metal oxide semiconductor field effect transistor structure provided by an exemplary embodiment of the present application;

[0030] Figure 4 It is a cross-sectional view of a metal oxide semiconductor field effect tube structure in the related art;

[0031] Figure 5 is a cross-sectional view of another metal oxide semiconductor field effect transistor structure in the related art;

[0032] Figure 6A metal oxide semiconductor field effect transistor structure and a Figure 4 and Figure 5 A schematic diagram showing a comparison of output characteristic curves of two metal oxide semiconductor field effect transistor structures;

[0033] Figure 7 A metal oxide semiconductor field effect transistor structure and a Figure 4 and Figure 5 A schematic diagram showing a comparison of short-circuit characteristic curves of two metal oxide semiconductor field effect transistor structures;

[0034] Figure 8 A metal oxide semiconductor field effect transistor structure and a Figure 4 and Figure 5 A schematic diagram showing a comparison of gate charge characteristic curves of two metal oxide semiconductor field effect transistor structures;

[0035] Fig. 9 is a method flow chart of a method for preparing a metal oxide semiconductor field effect transistor structure provided by an exemplary embodiment of the present application;

[0036] Figures 10 to 17 is based on Fig. 9 The structure schematic diagram of different stages of preparing a metal oxide semiconductor field effect transistor structure in a method for preparing a metal oxide semiconductor field effect transistor structure is shown. DETAILED DESCRIPTION

[0037] Here, the technical solutions in the embodiments (or "implementations") of the present application will be described clearly and completely in conjunction with the accompanying drawings. When the following description refers to the drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements.

[0038] If there are terms involving directional indications or positional relationships in the embodiments of the present application (such as up, down, left, right, front, back, inside, outside, top, bottom, center, vertical, horizontal, longitudinal, transverse, length, width, counterclockwise, clockwise, axial, radial, circumferential, etc.), such terms are only used to explain the relative positional relationship, movement, etc. between the components in a certain specific posture; if the specific posture changes, the directional indication or positional relationship will also change accordingly. In addition, the terms "first", "second", etc. involved in the embodiments of the present application are only used for the purpose of convenience of description and cannot be understood as indicating or implying relative importance.

[0039] The following is combined with Figures 1 to 17 , some embodiments of the present application are described in detail. In the absence of conflict, the following embodiments and features in the embodiments can be combined with each other.

[0040] Please refer to Figure 1 and, if necessary, combined Figure 2 and Figure 3 As shown, the metal oxide semiconductor field effect transistor structure 100 includes an N-type substrate 1, an N-type epitaxial layer 2, a P-type first well region 31, a P-type second well region 32, an N-type current spreading layer 4, an N-type first source region 51, an N-type second source region 52, a first channel region 61, a second channel region 62, a P-type buffer layer 8, a first gate 101, a second gate 102 and a P-type equipotential ring region 14. Among them, the N-type epitaxial layer 2 is formed on one side of the N-type substrate 1. The P-type first well region 31 and the P-type second well region 32 are formed in the upper part of the N-type epitaxial layer 2 and are spaced apart from each other in the first direction x. The N-type current spreading layer 4 is formed in the upper part of the N-type epitaxial layer 2 and is located between the P-type first well region 31 and the P-type second well region 32. The P-type equipotential ring region 14 is formed in the upper part of the N-type epitaxial layer 2 and is at least partially located on the same side of the P-type first well region 31, the P-type second well region 32, and the N-type current spreading layer 4 in the second direction y; there is a non-zero angle between the first direction x and the second direction y, and the up-down direction is perpendicular to the plane defined by the first direction x and the second direction y. The N-type first source region 51 is formed in the upper part of the P-type first well region 31, the N-type second source region 52 is formed in the upper part of the P-type second well region 32, and the N-type first source region 51 and the N-type second source region 52 are both spaced apart from the N-type current spreading layer 4. The first channel region 61 is formed by the upper region of the P-type first well region 31 close to the N-type current spreading layer 4, and the second channel region 62 is formed by the upper region of the P-type second well region 32 close to the N-type current spreading layer 4. The first gate 101 is located above the first channel region 61, and the second gate 102 is located above the second channel region 62. The P-type buffer layer 8 is formed on the upper part of the middle region of the N-type current spreading layer 4; wherein the P-type buffer layer 8 is connected to or spaced from the P-type equipotential ring region 14. Figure 2 As shown, the P-type buffer layer 8 is connected to the P-type equipotential ring region 14. Figure 3 As shown, the P-type buffer layer 8 and the P-type equipotential ring region 14 are spaced apart from each other.

[0041] The above-mentioned metal oxide semiconductor field effect transistor structure 100 improves the electric field distribution on the PN junction formed by the P-type first well region 31 and the P-type second well region 32 and the N-type current spreading layer 4, and the P-type first well region 31 and the P-type second well region 32 and the N-type epitaxial layer 28 in the blocking state by forming the P-type buffer layer 8 on the upper part of the middle region in the N-type current spreading layer 4, thereby improving the withstand voltage capability of the metal oxide semiconductor field effect transistor structure 100. For the connection between the P-type buffer layer 8 and the P-type equipotential ring region 14, the flow width of the third quadrant body diode can be increased, the conduction voltage drop of the body diode can be reduced, and the dead zone loss can be reduced when applied to power electronic converters.

[0042] The metal oxide semiconductor field effect transistor structure 100 is a silicon carbide metal oxide semiconductor field effect transistor, namely, SiC MOSFET.

[0043] In some embodiments, the N-type substrate 1 is a silicon carbide (SiC) substrate. The N-type substrate 1 is a heavily doped silicon carbide substrate.

[0044] In some embodiments, the N-type epitaxial layer 2 is a lightly doped epitaxial layer. The doping concentration of the N-type epitaxial layer 2 may be 2e14-1e16 cm -3 The preferred doping concentration of the N-type epitaxial layer 2 may be 9e15cm -3 .

[0045] The thickness of the N epitaxial layer 2 may be greater than or equal to the thickness of the N-type substrate 1 .

[0046] In some embodiments, the thickness of the N epitaxial layer 2 may be 5-50 μm, such as 5 μm, 10 μm, 15 μm, 20 μm, 25 μm, 30 μm, 35 μm, 40 μm, 45 μm, 50 μm, etc. In some embodiments, the preferred thickness of the N epitaxial layer 2 is 10 μm.

[0047] In some embodiments, the junction depths of the P-type first well region 31 and the P-type second well region 32 may be equal. The junction depths of the P-type first well region 31 and the P-type second well region 32 may be 0.7 μm-1.2 μm. For example, 0.7 μm, 0.8 μm, 0.9 μm, 1.0 μm, 1.1 μm, 1.2 μm. In some embodiments, the junction depth of the P-type first well region 31 and the P-type second well region 32 is preferably 0.9 μm.

[0048] In some embodiments, the P-type first well region 31 and the P-type second well region 32 are made of the same material. The doping concentration of the P-type first well region 31 and the P-type second well region 32 may be 1e18-3e18 cm -3 In some embodiments, the preferred doping concentration of the P-type first well region 31 and the P-type second well region 32 is 1.5e18 cm-3 .

[0049] In some embodiments, the ion doping concentration of the N-type current spreading layer 4 is greater than or equal to the ion doping concentration of the N-type epitaxial layer 2 , so that the N-type epitaxial layer 2 can play a better isolation and protection role and avoid current leakage in the N-type current spreading layer 4 .

[0050] In some embodiments, the ratio between the ion doping concentration of the N-type current spreading layer 4 and the ion doping concentration of the N-type epitaxial layer 2 is 1-20.

[0051] In some embodiments, the doping concentration of the N-type current spreading layer 4 is preferably 8e16 cm -3 .

[0052] In some embodiments, the junction depth of the N-type current spreading layer is 0.7 μm-1.2 μm. For example, the junction depth of the N-type current spreading layer 4 can be 0.7 μm, 0.8 μm, 0.9 μm, 1.0 μm, 1.1 μm, 1.2 μm. In some embodiments, the preferred junction depth of the N-type current spreading layer 4 can be 0.8 μm.

[0053] In some embodiments, the N-type first source region 51 and the N-type second source region 52 have the same material and junction depth.

[0054] In some embodiments, the junction depth between the N-type first source region 51 and the N-type second source region 52 may be 0.2-0.3 μm, for example, 0.2 μm, 0.25 μm, 0.3 μm, etc. The preferred junction depth between the N-type first source region 51 and the N-type second source region 52 is 0.3 μm.

[0055] In some embodiments, the P-type buffer layer 8 is a P-type heavily doped region.

[0056] The doping concentration of the P-type buffer layer 8 can be 1e19-5e19 cm -3 For example, 1e19 cm -3 , 2e19 cm -3 、3e19cm -3 , 4e19 cm -3 , 5e19 cm -3 In some embodiments, the doping concentration of the P-type buffer layer 8 is preferably 1e19 cm -3 .

[0057] In some embodiments, the junction depth d of the P-type buffer layer 8 is 0.2 μm-0.4 μm, for example, 0.2 μm, 0.25 μm, 0.3 μm, 0.35 μm, 0.4 μm, etc. In some embodiments, the preferred junction depth of the P-type buffer layer 8 is 0.4 micrometers μm.

[0058] In some embodiments, the ratio of the width W1 of the P-type buffer layer 8 in the first direction x to the width W2 of the N-type current spreading layer 4 in the first direction x is 0.2-0.5, so as to improve the buffering effect of the P-type buffer layer 8 while ensuring the performance of the N-type current spreading layer 4.

[0059] In some embodiments, the width W2 of the N-type current spreading layer 4 is 2.5 μm, and the width W1 of the P-type buffer layer 8 is 0.8 μm.

[0060] In some embodiments, a P-type first contact region 71 is formed in the P-type first well region 31 and is located on a side of the N-type first source region 51 away from the N-type current spreading layer 4. A P-type second contact region 72 is formed in the P-type second well region 32 and is located on a side of the N-type second source region 52 away from the N-type current spreading layer 4.

[0061] The P-type first contact region 71 and the P-type second contact region 72 may be P-type heavily doped regions. The doping concentration of the P-type first contact region 71 and the P-type second contact region 72 may be 1e19-5e19 cm -3 For example, 1e19 cm -3 、2e19cm -3 、3e19 cm -3 , 4e19 cm -3 , 5e19 cm -3 In some embodiments, the doping concentration of the P-type first contact region 71 and the P-type second contact region 72 is preferably 1e19 cm -3 .

[0062] In some embodiments, the junction depths of the P-type first contact region 71 and the P-type second contact region 72 are the same.

[0063] The junction depth d of the P-type buffer layer 8 is 0.2 μm-0.4 μm, for example, 0.2 μm, 0.25 μm, 0.3 μm, 0.35 μm, 0.4 μm, etc. In some embodiments, the preferred junction depth of the P-type buffer layer 8 is 0.4 micrometers μm.

[0064] In some embodiments, the P-type buffer layer 8 , the P-type first contact region 71 , and the P-type second contact region 72 have the same ion doping concentration.

[0065] In some embodiments, the junction depth d of the P-type buffer layer 8 , the junction depth D of the P-type first contact region 71 , and the junction depth D of the P-type second contact region 72 are the same.

[0066] The P-type equipotential ring region 14 may be a zero potential point region.

[0067] In some embodiments, the P-type equipotential ring region 14 may be a P-type heavily doped region. The doping concentration of the P-type first contact region 71 and the P-type second contact region 72 may be 1e19-5e19 cm -3 For example, 1e19 cm -3 , 2e19 cm -3 、3e19cm -3 , 4e19 cm -3 , 5e19 cm -3 In some embodiments, the doping concentration of the P-type equipotential ring region 14 is preferably 1e19 cm -3 .

[0068] In some embodiments, the depth of the P-type equipotential ring region 14 is 0.2 μm-0.4 μm, for example, 0.2 μm, 0.25 μm, 0.3 μm, 0.35 μm, 0.4 μm, etc. In some embodiments, the preferred depth of the P-type equipotential ring region 14 is 0.4 micrometers μm.

[0069] In some embodiments, the P-type equipotential ring region 14 has the same ion doping concentration as the P-type buffer layer 8 , the P-type first contact region 71 , and the P-type second contact region 72 .

[0070] In some embodiments, the depth of the P-type equipotential ring region 14 is the same as the junction depth d of the P-type buffer layer 8 , the junction depth D of the P-type first contact region 71 , and the junction depth of the P-type second contact region 72 .

[0071] In some embodiments, the P-type buffer layer 8 , the P-type first contact region 71 , the P-type second contact region 72 , and the P-type equipotential ring region are formed in the same process, and the P-type buffer layer 8 is formed without adding any preparation process.

[0072] In some embodiments, the MOSFET structure 100 may further include a first gate oxide layer 91 and a second gate oxide layer 92. The first gate oxide layer 91 is located between the first channel region 61 and the first gate 101, and the second gate oxide layer 92 is located between the second channel region 62 and the second gate 102.

[0073] The first gate oxide layer 91 and the second gate oxide layer 92 may be spaced apart from each other.

[0074] In some embodiments, the MOSFET structure 100 may further include an interlayer dielectric layer 12 covering exposed portions of the first gate 101 and the second gate 102 and filling a gap between the first gate 101 and the second gate 102 .

[0075] In some embodiments, the MOSFET structure 100 may further include a first source 111 and a second source 112 . The first source 111 is located at the N-type first source region 51 , and the second source 112 is located above the N-type second source region 52 .

[0076] The first source 111 and the second source 112 can be connected to a zero potential point.

[0077] In some embodiments, the MOSFET structure 100 may further include a drain 13. The drain 13 is located on a side of the N-type substrate 1 away from the N-type epitaxial layer 2.

[0078] In the metal oxide semiconductor field effect transistor structure 100, the provision of the P-type buffer layer 8 also has the following beneficial effects: 1. The presence of the P-type buffer layer 8 strengthens the shielding of the drain voltage in the blocking state, which is beneficial to reducing the peak value of the electric field strength of the gate oxide layer, greatly improving the gate oxide reliability of the device, and preventing the gate oxide layer of the device from breaking down prematurely. 2. Due to the presence of the P-type buffer layer 8, in the saturation state of high drain voltage, the PN junction formed by the P-type buffer layer 8 and the N-type current expansion layer 4 is reverse-biased and depleted, reducing the current width of the N-type current expansion layer 4 in the saturation state, limiting the current of the device under short-circuit conditions, and greatly improving the short-circuit tolerance of the device. 3. The presence of the P-type buffer layer 8 reduces the gate-drain capacitance in the switching state, greatly improving the switching rate of the device, so that the device can operate at an extremely high switching frequency.

[0079] It should be noted that compared with Figure 3 In the embodiment shown in the figure, between the P-type buffer layer 8 and the P-type equipotential ring area 14, in the metal oxide semiconductor field effect transistor structure, between the P-type buffer layer 8 and the P-type equipotential ring area 14 is as shown in the figure. Figure 2 With the connection method shown, the P-type equipotential ring area 14 achieves improved electric field distribution, improved voltage resistance of the metal oxide semiconductor field effect tube structure, reduced dead zone loss, improved gate oxide reliability of the device, prevented premature breakdown of the gate oxide layer of the device, improved short-circuit tolerance of the device, and increased the switching rate of the device.

[0080] It should be noted that, in the present application, each N-type structural region or structural layer of the metal oxide semiconductor field effect transistor structure 100 can be formed by doping with a pentavalent element, such as one or two elements of nitrogen (N) element or phosphorus (P) element. Each P-type structural region or structural layer of the metal oxide semiconductor field effect transistor structure 100 can be formed by doping with a trivalent element, such as one or two elements of aluminum (Al) element or boron (B) element.

[0081] Based on the above description, combined with Figures 4 to 8As shown, an exemplary analysis is performed on the beneficial effects of the metal oxide semiconductor field effect transistor structure 100 described in the present application. Figure 4 It is a cross-sectional view of a metal oxide semiconductor field effect transistor structure 200 in the related art. The metal oxide semiconductor field effect transistor structure 200 is a dual-gate SiC MOSFET structure, which may be referred to as a dual-gate SiC MOSFET structure hereinafter. Figure 5 1 is a cross-sectional view of another metal oxide semiconductor field effect transistor structure 300 in the related art. The metal oxide semiconductor field effect transistor structure 300 is a planar SiC MOSFET structure, which may be referred to as a planar SiC MOSFET structure hereinafter. Similar or identical structures or regions in the metal oxide semiconductor field effect transistor structures 100, 200 and 300 are labeled with the same reference numerals.

[0082] In the MOSFET structure 100, the ion doping concentration of the N-type epitaxial layer 2 is 9e15cm -3 The junction depth of the N-type current spreading layer 4 is 0.8 μm, and the doping concentration of the N-type current spreading layer 4 is 8e16 cm -3 The junction depths of the P-type first contact region 71 and the P-type second contact region 72 are both 0.4 μm, and the doping concentrations are both 5e18 cm -3 The P-type buffer layer 8 is connected to the P-type equipotential ring area, the junction depth of the P-type buffer layer is 0.4 μm, and the doping concentration is 5e18 cm -3 ; two gate oxide layers 9; two gate electrodes 10; the width W2 of the N-type current spreading layer 4 is 2.5 μm, the width W1 of the P-type buffer layer 8 is 0.8 μm, and the length of the first gate electrode 101 and the second gate electrode 102 exposed in the second direction y at the upper end of the N-type current spreading layer 4 is 0.4 μm. The dimensions of each structural layer or region of the MOSFET structures 200 and 300 are the same as the dimensions of the corresponding structural layers or regions of the MOSFET structure 100.

[0083] exist Figure 4 In the dual-gate SiC MOSFET structure shown, there is an N-type current spreading layer 4 with a doping concentration of 4e16cm-3, a gate oxide layer 9 covering the entire N-type current spreading layer 4, and an interlayer dielectric layer 12, and no P-type buffer layer is used. In addition, other structural parameters, process parameters, process flow, and verification conditions are exactly the same as those of the embodiment of the utility model.

[0084] exist Figure 5In the planar SiC MOSFET structure shown, there is an N-type current spreading layer 4 with a doping concentration of 4e16 cm-3, a gate oxide layer 9 covering the entire N-type current spreading layer 4, a gate 10, and an interlayer dielectric layer 12, and no P-type buffer layer is used. In addition, other structural parameters, process parameters, process flow, and test conditions are exactly the same as those of the embodiment of the utility model.

[0085] In the blocking state, the metal oxide semiconductor field effect transistor structure 100 provided by the present application is compared with Figure 4 The dual-gate SiC MOSFET structure shown in the figure greatly reduces the electric field at the gate corner, even lower than Figure 5 The gate oxide layer electric field of the planar SiC MOSFET shown is lower. This weakens the contradiction between gate oxide reliability and device effectiveness and reduces the demand for process accuracy. Under the same parameter conditions, the embodiment of the present application adopts a P-type buffer layer 8 grounding connection method, which is similar to Figure 4 The dual-gate SiC MOSFET structure shown in the figure, Figure 5 The planar SiC MOSFET structure shown in the figure is simulated and analyzed. The simulation results are shown in Figures 6 to 8 shown.

[0086] Figure 6 A metal oxide semiconductor field effect transistor structure and a Figure 4 and Figure 5 The figure is a schematic diagram comparing the output characteristic curves of the two metal oxide semiconductor field effect transistor structures. Figure 6 In the simulation analysis of the metal oxide semiconductor field effect tube structures shown in the figure, the gate-source voltage used is 20V. Figure 6 It can be seen that the utility model is compared with Figure 5 The planar SiC MOSFET structure shown in the figure, Figure 4 The output characteristics of the dual-gate SiC MOSFET structure shown in FIG. 1 are almost unchanged, indicating that the introduction of the P-type buffer layer 8 has no effect on the on-resistance of the device.

[0087] Figure 7 A metal oxide semiconductor field effect transistor structure and a Figure 4 and Figure 5 The figure is a schematic diagram comparing the short-circuit characteristic curves of the two metal oxide semiconductor field effect transistor structures. Figure 7 In the simulation analysis of the metal oxide semiconductor field effect tube structures shown in the figure, the drain-source voltage used is 600V and the gate-source voltage is 20V. Figure 7 It can be seen that the utility model is compared with Figure 5 The planar SiC MOSFET structure shown in the figure, Figure 4The dual-gate SiC MOSFET structure shown in the figure has a greatly reduced short-circuit current and significantly enhanced short-circuit withstand capability.

[0088] Figure 8 A metal oxide semiconductor field effect transistor structure and a Figure 4 and Figure 5 The schematic diagram of the comparison of gate charge characteristic curves of the two metal oxide semiconductor field effect transistor structures shown in FIG. Figure 8 It can be seen that the Miller platform in the gate charging curve of the utility model is significantly shortened, indicating that the gate-drain charge during the charging process is reduced, which means a smaller gate-drain capacitance and can work at a higher switching speed and operating frequency. Through the above comparison, it is confirmed that the dual-gate SiC MOSFET structure of the embodiment of the utility model has a more excellent performance.

[0089] like Fig. 9 As shown, the present application further provides a method for preparing a metal oxide semiconductor field effect transistor structure, comprising the following steps S101 to S105:

[0090] In step S101 , an N-type substrate is provided, and an N-type epitaxial layer is formed on one side of the N-type substrate.

[0091] In step S102, a P-type first well region, a P-type second well region and an N-type current spreading layer are formed in the upper portion of the N-type epitaxial layer; wherein the P-type first well region and the P-type second well region are spaced apart in a first direction, and the N-type current spreading layer is located between the P-type first well region and the P-type second well region.

[0092] In step S103, an N-type first source region is formed in the upper portion of the P-type first well region, and an N-type second source region is formed in the upper portion of the P-type second well region; the N-type first source region and the N-type second source region are both spaced apart from the N-type current spreading layer; a first channel region is formed in an upper region of the P-type first well region close to the N-type current spreading layer, and a second channel region is formed in an upper region of the P-type second well region close to the N-type current spreading layer.

[0093] In step S104, a P-type buffer layer is formed in the upper part of the middle region of the N-type current spreading layer, and a P-type equipotential ring region is formed in the upper part of the N-type epitaxial layer; wherein the P-type buffer layer and the P-type equipotential ring region are connected or spaced apart, and at least part of the P-type equipotential ring region is located on the same side of the P-type first well region, the P-type second well region and the N-type current spreading layer in the second direction; a non-zero angle is formed between the first direction and the second direction, and the up and down directions are perpendicular to the plane determined by the first direction and the second direction.

[0094] In step S105 , a first gate is formed above the first channel region, and a second gate is formed above the second channel region.

[0095] The following combination Figures 10 to 17 The preparation method of the metal oxide semiconductor field effect transistor structure is described in detail.

[0096] like Fig.10 As shown, in step S101 , an N-type substrate 1 is provided, and an N-type epitaxial layer 2 is formed on one side of the N-type substrate 1 .

[0097] The N-type substrate 1 is a silicon carbide (SiC) substrate.

[0098] The N-type epitaxial layer 2 can be formed by using a semiconductor growth process.

[0099] like Fig.11 As shown, in step S102, a P-type first well region 31, a P-type second well region 32 and an N-type current spreading layer 4 are formed in the upper part of the N-type epitaxial layer 2. The P-type first well region 31 and the P-type second well region 32 are arranged at intervals in the first direction x, and the N-type current spreading layer 4 is located between the P-type first well region 31 and the P-type second well region 32.

[0100] like Fig.12 As shown, in step S103, an N-type first source region 51 is formed in the upper part of the P-type first well region 31, and an N-type second source region 52 is formed in the upper part of the P-type second well region 32. The N-type first source region 51 and the N-type second source region 52 are both spaced apart from the N-type current spreading layer 4; a first channel region 61 is formed in the upper region of the P-type first well region 31 close to the N-type current spreading layer 4, and a second channel region 62 is formed in the upper region of the P-type second well region 32 close to the N-type current spreading layer 4.

[0101] like Fig.13 As shown, in step S104, a P-type buffer layer 8 is formed in the upper part of the middle region of the N-type current spreading layer 4, and a P-type equipotential ring region 14 is formed in the upper part of the N-type epitaxial layer 2. The P-type buffer layer 8 is connected to or spaced from the P-type equipotential ring region 14, and at least part of the P-type equipotential ring region 14 is located on the same side of the P-type first well region 31 and the P-type second well region 32 and the N-type current spreading layer 4 in the second direction y; there is a non-zero angle between the first direction x and the second direction y, and the up-down direction is perpendicular to the plane defined by the first direction x and the second direction y.

[0102] like Fig.13As shown, in some embodiments, the method further includes: forming a P-type first contact region 71 in the P-type first well region 31, which is located at the N-type first source region 51 and away from the N-type current spreading layer 4; and forming a P-type second contact region 72 in the P-type second well region 32, which is located at the N-type second source region 52 and away from the N-type current spreading layer 4.

[0103] In some embodiments, the P-type buffer layer 8 , the P-type first contact region 71 , and the P-type second contact region 72 are formed in the same process, and the P-type buffer layer 8 is formed without adding any additional preparation processes.

[0104] In some other embodiments, the P-type buffer layer 8 , the P-type first contact region 71 , the P-type second contact region 72 , and the P-type equipotential ring region 14 are formed in the same process.

[0105] At this point, after forming the P-type buffer layer 8, the P-type first contact region 71, the P-type second contact region 72, and the P-type equipotential ring region 14, the following can be formed: Fig.13 The upper surface shown is a flat plate-like intermediate structure.

[0106] After forming a P-type buffer layer 8 in the upper part of the middle region of the N-type current spreading layer 4 and forming a P-type equipotential ring region 14 in the upper part of the N-type epitaxial layer 2 in step S104, the method includes the following step S106:

[0107] In step 106 , a first gate oxide layer 91 is formed on the first channel region 61 , and a second gate oxide layer 92 is formed on the second channel region 62 .

[0108] like Fig.14 As shown, step S106 can be implemented by the following steps S1061 and S1062:

[0109] In step S1061, Fig.13 A gate oxide material layer 90 is formed on the upper surface of the intermediate structure.

[0110] In step S1062 , the gate oxide material layer 90 is etched to form a first gate oxide layer 91 and a second gate oxide layer 92 .

[0111] The gate oxide material layer 90 can be formed by chemical vapor deposition. The material of the gate oxide material layer 90 can be silicon dioxide.

[0112] A photolithography and etching process may be used to form the first gate oxide layer 91 and the second gate oxide layer 92 by etching.

[0113] like Fig.15As shown, in step S105 , a first gate 101 is formed above the first channel region 61 , and a second gate 102 is formed above the second channel region 62 .

[0114] Polysilicon deposition process can be used in Fig.14 A polysilicon layer is deposited on the entire upper surface of the structure, and the polysilicon at both ends and in the middle area is etched by photolithography and etching to form a first gate 101 and a second gate 102 .

[0115] The above-mentioned etching process for etching to form the first gate oxide layer 91 and the second gate oxide layer 92 can be performed after forming the first gate 101 and the second gate 102, so as to etch away the portions of the gate oxide material layer 90 located at the two ends of the first gate 101 and the second gate 102 in the first direction x and between the first gate 101 and the second gate 102, so as to form the first gate oxide layer 91 and the second gate oxide layer 92.

[0116] like Fig.16 and Fig.17 As shown, after forming a first gate 101 on the first channel region 61 and forming a second gate 102 on the second channel region 62 in step 105, the method includes the following step S107:

[0117] In step S107 , an interlayer dielectric layer 12 is formed. The interlayer dielectric layer 12 covers the exposed portions of the first gate 101 and the second gate 102 and fills the space between the first gate 101 and the second gate 102 .

[0118] The interlayer dielectric layer 12 can be formed by chemical vapor deposition combined with photolithography and etching processes. The material of the interlayer dielectric layer 12 can be silicon dioxide.

[0119] In step S107, chemical vapor deposition may be used to form Fig.16 After the interlayer dielectric material layer 120 with a larger coverage area is formed, the interlayer dielectric material layer 120 can be etched at both ends in the first direction x by a photolithography process to expose the P-type first contact region 71, the P-type second contact region 72, at least a portion of the N-type first source region 51 and the N-type second source region 52, forming a structure as shown in FIG. Fig.17 An interlayer dielectric layer 12 is shown.

[0120] like Fig.17 As shown, after step S107, the method includes the following step S108:

[0121] In step S108 , a first source 111 , a second source 112 and a drain 13 are formed. The first source 111 is located above the N-type first source region 51 , and the second source 112 is located above the N-type second source region 52 . The drain 13 is located on a side of the N-type substrate 1 away from the N-type epitaxial layer 2 .

[0122] In step S108 , a first source electrode 111 and a second source electrode 112 may be formed in the region of the interlayer dielectric material layer etched away in step S107 .

[0123] The first source electrode 111 and the second source electrode 112 may be formed by a metal deposition process. The material of the first source electrode 111 and the second source electrode 112 may be aluminum.

[0124] It should be noted that the P-type first well region 31, the P-type second well region 32, the P-type buffer layer 8, the P-type first contact region 71 and the P-type second contact region 72, the P-type equipotential ring region 14, the N-type current spreading layer, the N-type first source region 51 and the N-type second source region 52 are all formed by ion implantation process.

[0125] In the present application, each N-type structural region or structural layer of the metal oxide semiconductor field effect transistor structure 100 can be formed by doping pentavalent elements, such as one or two elements of nitrogen (N) element or phosphorus (P) element. Each P-type structural region or structural layer of the metal oxide semiconductor field effect transistor structure 100 can be formed by doping trivalent elements, such as one or two elements of aluminum (Al) element or boron (B) element.

[0126] For example, in some embodiments, in step S102, when forming the P-type first well region 31 and the P-type second well region 32 and the N-type current spreading layer 4 in the upper portion of the N-type epitaxial layer 2, aluminum atoms may be implanted multiple times in the upper portion of the N-type epitaxial layer 2 to form the P-type first well region 31 and the P-type second well region 32. Nitrogen atoms may be implanted multiple times in the region between the P-type first well region 31 and the P-type second well region 32 to form the N-type current spreading layer 4.

[0127] In step S103, when an N-type first source region 51 is formed in the upper portion of the P-type first well region 31 and an N-type second source region 52 is formed in the upper portion of the P-type second well region 32, nitrogen atoms may be injected multiple times into the upper portion of the P-type first well region 31 to form the N-type first source region 51 and nitrogen atoms may be injected multiple times into the upper portion of the P-type second well region 32 to form the N-type second source region 52.

[0128] In step S104, when a P-type buffer layer is formed in the upper part of the middle region within the N-type current spreading layer and a P-type equipotential ring region is formed in the upper part of the N-type epitaxial layer, aluminum atoms may be injected multiple times into the upper part of the N-type epitaxial layer to form a P-type equipotential ring region, and aluminum atoms may be injected multiple times into the upper part of the middle region within the N-type current spreading layer to form a P-type buffer layer.

[0129] Accordingly, when forming the first contact region 71 and the second contact region 72, aluminum atoms can be injected multiple times in the P-type first well region 31 on the side of the N-type first source region 51 away from the N-type current spreading layer 4 to form the P-type first contact region 71, and aluminum atoms can be injected multiple times in the P-type second well region 32 on the side of the N-type second source region 52 away from the N-type current spreading layer 4 to form the P-type second contact region 72.

[0130] It should be noted that the technical solutions or technical features described in the above embodiments can be combined or supplemented with each other without causing conflicts. The scope of protection of this application is not limited to the precise structures described in the above embodiments and shown in the drawings; all modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of this application should be included in the scope of protection of this application.

Claims

1. A metal oxide semiconductor field effect transistor structure, characterized in that: include: N-type substrate; N-type epitaxial layer; formed on one side of the N-type substrate; A P-type first well region and a P-type second well region are formed in an upper portion of the N-type epitaxial layer and are spaced apart from each other in a first direction; An N-type current spreading layer, formed in an upper portion of the N-type epitaxial layer and located between the P-type first well region and the P-type second well region; A P-type equipotential ring region is formed in the upper part of the N-type epitaxial layer and is at least partially located on the same side of the P-type first well region, the P-type second well region, and the N-type current spreading layer in the second direction; there is a non-zero angle between the first direction and the second direction, and the up-down direction is perpendicular to the plane determined by the first direction and the second direction; An N-type first source region and an N-type second source region, wherein the N-type first source region is formed at an upper portion of the P-type first well region, the N-type second source region is formed at an upper portion of the P-type second well region, and both the N-type first source region and the N-type second source region are spaced apart from the N-type current spreading layer; A first channel region and a second channel region, wherein the first channel region is formed by an upper region of the P-type first well region close to the N-type current spreading layer, and the second channel region is formed by an upper region of the P-type second well region close to the N-type current spreading layer; a first gate and a second gate, the first gate being located above the first channel region, and the second gate being located above the second channel region; A P-type buffer layer is formed on the upper part of the middle region in the N-type current spreading layer; wherein the P-type buffer layer is connected to or spaced from the P-type equipotential ring region.

2. The metal oxide semiconductor field effect transistor structure according to claim 1, characterized in that: The ion doping concentration of the N-type current spreading layer is greater than or equal to the ion doping concentration of the N-type epitaxial layer; and the ratio between the ion doping concentration of the N-type current spreading layer and the ion doping concentration of the N-type epitaxial layer is 1-20.

3. The metal oxide semiconductor field effect transistor structure according to claim 1, characterized in that: The ratio of the width of the P-type buffer layer in the first direction to the width of the N-type current spreading layer in the first direction is 0.2-0.

5.

4. The metal oxide semiconductor field effect transistor structure according to claim 1, characterized in that: A P-type first contact region is formed in the P-type first well region and is located on a side of the N-type first source region away from the N-type current spreading layer; The P-type second well region is formed with a P-type second contact region located on a side of the N-type second source region away from the N-type current spreading layer.

5. The metal oxide semiconductor field effect transistor structure according to claim 4, characterized in that: The P-type buffer layer, the P-type first contact region, and the P-type second contact region have the same ion doping concentration.

6. The metal oxide semiconductor field effect transistor structure according to claim 4, characterized in that: The junction depths of the P-type buffer layer, the P-type first contact region, and the P-type second contact region are the same.

7. The metal oxide semiconductor field effect transistor structure according to claim 1, characterized in that: The metal oxide semiconductor field effect transistor structure comprises: A first gate oxide layer and a second gate oxide layer, wherein the first gate oxide layer is located between the first channel region and the first gate, and the second gate oxide layer is located between the second channel region and the second gate.

8. The metal oxide semiconductor field effect transistor structure according to claim 1, characterized in that: The metal oxide semiconductor field effect transistor structure comprises: The interlayer dielectric layer covers the exposed portions of the first gate and the second gate and fills the space between the first gate and the second gate.

9. The metal oxide semiconductor field effect transistor structure according to claim 1, characterized in that: The metal oxide semiconductor field effect transistor structure comprises: A first source and a second source, wherein the first source is located in the N-type first source region, and the second source is located above the N-type second source region.

10. The metal oxide semiconductor field effect transistor structure according to claim 1, characterized in that: The metal oxide semiconductor field effect transistor structure comprises: The drain is located on a side of the N-type substrate away from the N-type epitaxial layer.

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