SiC UMOSFET integrated with Schottky diode

Abstract

The utility model discloses a SiC UMOSFET integrated with a Schottky diode, and relates to the technical field of semiconductors. A heavily doped P + region of a first trench region is utilized to protect a gate oxide layer of a second trench region, electric field concentration at corners at the bottom of trench gate oxide is reduced through a space depletion layer between the P + region and an N-type drift layer, and early breakdown failure of the gate oxide layer is avoided, so that the use reliability of the gate oxide layer is improved, and the service life of the gate oxide layer is prolonged. A Schottky diode (SBD) structure is integrated on the side wall of the first groove region, so that in the follow current process of the device, original PN junction body diode follow current is changed into SBD follow current, a P region hole is prevented from entering an N-type drift layer, the bipolar degradation effect of the device is avoided, and the long-term use reliability of the device is improved.

Description

Technical Field

[0001] The utility model relates to the technical field of semiconductors, in particular to a SiC UMOSFET with an integrated Schottky diode. Background Art

[0002] The third generation wide bandgap semiconductor materials represented by silicon carbide (SiC) have excellent physical properties such as strong critical breakdown field, low intrinsic carrier concentration, fast saturated electron drift rate, and high thermal conductivity. Therefore, metal-oxide-semiconductor field effect transistors (MOSFETs) prepared with SiC as semiconductor materials can achieve superior device performance in high voltage, high temperature, high frequency, high radiation and other fields. Especially with the rapid development of new energy vehicles, photovoltaics and other fields, traditional silicon-based power devices have approached the performance limit of the material itself and cannot meet the more stringent use requirements put forward by these application fields. As a result, SiC power devices have begun to gradually replace silicon-based power devices, and the future will no longer be the only market structure for silicon-based power devices.

[0003] SiC MOSFET devices have two obvious disadvantages during long-term use:

[0004] (1) The probability of early breakdown failure of the gate oxide layer of SiC MOSFET devices is high, especially for trench SiC MOSFET devices. Due to the high interface state density of SiC / SiO2 and the large number of defects, the gate oxide layer quality is poor. In addition, the curvature effect of the trench gate oxide is more likely to cause electric field concentration at the bottom corner, which further aggravates the breakdown failure rate.

[0005] (2) Conventional SiC MOSFET devices integrate an anti-parallel PN junction body diode to achieve freewheeling protection for the device. However, during the freewheeling process, the holes in the P region will enter the N-type drift layer, causing the recombination of holes and electrons, leading to the spread of lattice defects in the drift layer, and ultimately causing bipolar degradation of the device, resulting in performance deterioration.

[0006] In summary, during the long-term use of trench SiC MOSFET, the early breakdown failure of the gate oxide layer and the bipolar degradation effect caused by the PN junction diode pose challenges to the reliability of the device and greatly affect the large-scale stable use of the device. Therefore, how to improve the gate oxide layer reliability and bipolar degradation effect of trench Si MOSFET devices is crucial to the long-term use of the device.

[0007] In the existing patent documents, for example, a utility model patent for "Preparation method and application of trench MOS field effect transistor" was applied for and published on June 23, 2023, with the authorization announcement number CN 116313809 B. Its preparation method is as follows: an N-type semiconductor epitaxial layer, a well region and a doping region are sequentially formed on the semiconductor substrate layer; a virtual trench is etched on both sides of the middle region of the doping region, and P-type impurities are injected into the bottom of the virtual trench to form a P+ layer; a gate trench is etched in the middle region of the doping region; oxide is filled into the inside of the virtual trench; a metal layer is formed on the side of the doping region away from the N-type semiconductor epitaxial layer. In this patent document, although the electric field concentration at the bottom corner of the trench gate oxide is improved by the P+ layer at the bottom of the trench, the parasitic body diode in the MOS is still a PN junction diode, and there are problems such as large follow-through loss and bipolar degradation effect during the device follow-through process. Utility Model Content

[0008] In view of the above problems, the utility model provides a trench SiC field effect transistor which avoids early breakdown failure of the gate oxide layer, improves the reliability of the gate oxide layer, and during the device freewheeling process, changes the original PN junction body diode freewheeling to SBD freewheeling, thereby avoiding the holes in the P region from entering the N-type drift layer, thereby improving the long-term reliability of the device.

[0009] The technical solution of the utility model is:

[0010] A SiC UMOSFET with integrated Schottky diode, characterized in that it comprises a back electrode metal, a back ohmic alloy layer, an Epi layer and a front electrode metal arranged in sequence from bottom to top;

[0011] The Epi layer is provided with:

[0012] A P-body region extending downward from the top surface of the Epi layer;

[0013] An N+ region extending downward from a top surface of the P-body region;

[0014] A first trench region extends downward from the top surface of the N+ region to below the P-body region and is located in the Drift layer; the cross section of the first trench region is a V-shaped structure;

[0015] A P+ region extending downward from the bottom of the first trench region and connected to a corner of the bottom of the first trench region; the P+ region is located in the Drift layer;

[0016] A second trench region extends downward from the top surface of the N+ region to below the P-body region; a bottom of the second trench region is located above a bottom of the first trench region;

[0017] A gate oxide layer is arranged on the groove wall and the groove bottom of the second groove region;

[0018] A Poly layer, filled in the second trench region and connected to the gate oxide layer;

[0019] An isolation dielectric layer, located on the top of the first trench region, and connected to the N+ region, the second trench region and the Poly layer respectively;

[0020] The front ohmic alloy layer extends from the top surface of the N+ region to the bottom of the first trench region, the bottom is connected to the P+ region, and the side edge of the top is connected to the isolation dielectric layer.

[0021] Specifically, the bottom of the front electrode metal extends into the first groove region and is connected to the front ohmic alloy layer.

[0022] Specifically, the cross section of the second groove region is a U-shaped structure.

[0023] Specifically, the Epi layer includes a Sub layer and a Drift layer which are sequentially connected from bottom to top.

[0024] Specifically, the metal thickness of the front electrode is 5000 nm.

[0025] Specifically, a layer of back electrode metal is formed on the bottom surface of the back ohmic alloy layer by evaporating Ti / Ni / Ag or Ni / Pd / Au metal;

[0026] The thickness of Ti / Ni / Ag or Ni / Pd / Au metals are 30nm / 300nm / 1200nm respectively.

[0027] The utility model has two trench regions in a trench SiC MOSFET device, wherein the heavily doped P+ region of the first trench region is used to protect the gate oxide layer of the second trench region, and the electric field concentration at the bottom corner of the trench gate oxide is reduced by the space depletion layer between the P+ region and the N-type drift layer, thereby avoiding the early breakdown failure of the gate oxide layer, thereby improving the reliability of the gate oxide layer. At the same time, the utility model integrates an SBD structure on the side wall of the first trench region, and in the device freewheeling process, the original PN junction body diode freewheeling is changed to freewheeling from the SBD, thereby avoiding the P region holes from entering the N-type drift layer, thereby avoiding the occurrence of the bipolar degradation effect of the device, and improving the long-term reliability of the device. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] Figure 1 It is a structural schematic diagram of step S100 of the utility model;

[0029] Figure 2 It is a structural schematic diagram of step S200 of the utility model;

[0030] Figure 3 It is a structural schematic diagram of step S300 of the utility model;

[0031] Figure 4 It is a structural schematic diagram of step S400 of the utility model;

[0032] Figure 5 It is a structural schematic diagram of step S600 of the utility model;

[0033] Figure 6 It is a structural schematic diagram of step S700 of the utility model;

[0034] Figure 7 It is a structural schematic diagram of step S800 of the utility model;

[0035] Figure 8 It is a structural schematic diagram of step S900 of the utility model;

[0036] Fig. 9 It is a structural schematic diagram of step S1000 of the utility model;

[0037] Fig.10 It is a structural schematic diagram of step S1100 of the utility model;

[0038] Fig.11 It is a structural schematic diagram of step S1200 of the utility model;

[0039] Fig.12 It is a structural schematic diagram of step S1300 of the utility model;

[0040] In the figure, 1 is the Sub layer, 2 is the Drift layer, 3 is the Epi layer, 4 is the P-body region, 5 is the N+ region, 6 is the first trench region, 7 is the P+ region, 8 is the second trench region, 9 is the gate oxide layer, 10 is the Poly layer, 11 is the isolation dielectric layer, 12 is the front ohmic alloy layer, 13 is the front electrode metal, 14 is the back ohmic alloy layer, and 15 is the back electrode metal. DETAILED DESCRIPTION

[0041] The present invention is described in detail below in conjunction with specific practical cases. Examples of the embodiments are shown in the accompanying drawings, and the schematic implementation methods and descriptions of the present invention are only used to explain the present invention and are not intended to limit the present invention.

[0042] In the description of the present invention, it should be understood that the terms "upper", "lower", "left", "right", "vertical", "horizontal", etc., indicating the orientation or position relationship, are based on the orientation or position relationship shown in the drawings, and are only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the present invention. In the description of the present invention, unless otherwise specified, "multiple" means two or more.

[0043] In the description of the present invention, it should be noted that, unless otherwise clearly specified and limited, the terms "installation", "connection" and "connection" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection, or it can be indirectly connected through an intermediate medium, or it can be the internal communication of two components. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0044] A method for preparing a SiC UMOSFET with an integrated Schottky diode comprises the following steps:

[0045] S100, refer to Figure 1 As shown, a shallowly doped P-body region 4 is initially formed on the silicon carbide Epi layer 3 by ion implantation;

[0046] The Epi layer 3 in step S100 is composed of a silicon carbide Sub layer 1 and a silicon carbide Drift layer 2, both of which are N-type conductive types. The ions implanted into the shallowly doped P-body region 4 are Al ions with a doping concentration of 1E17 cm -2 -1E18cm -2 .

[0047] S200, refer to Figure 2 As shown, a heavily doped N+ region 5 is initially formed on the upper surface of the P-body region 4 by ion implantation;

[0048] The heavily doped N+ region 5 in step S200 is implanted with N ions at a doping concentration of 1E18 cm -2 -1E19cm -2 .

[0049] S300, refer to Figure 3 As shown, a first trench region 6 is formed downwardly on the top surface of the N+ region 5 by etching;

[0050] In step S300 , the inner wall of the first trench region 6 is an inclined surface, which is convenient for the subsequent preparation of the ohmic alloy layer.

[0051] S400, refer to Figure 4 As shown, a heavily doped P+ region 7 is initially formed on the bottom surface of the first trench region 6 by ion implantation;

[0052] The heavily doped P+ region 7 in step S400 is implanted with Al ions at a doping concentration of 1E17 cm -2 -1E18cm -2 .

[0053] S500, the P-body region 4, the N+ region 5 and the P+ region 7 are completely formed by high temperature activation annealing;

[0054] The high temperature activation annealing temperature in step S500 is between 1600°C and 1900°C.

[0055] S600, refer to Figure 5 As shown, a second trench region 8 is formed on the Epi layer 3 by etching;

[0056] S700, reference Figure 6 As shown, O2 is introduced into the inner wall of the second trench region 8, and a gate oxide layer 9 is grown by dry oxygen oxidation;

[0057] S800, reference Figure 7 As shown, a Poly layer 10 is formed inside the second trench region 8 by polysilicon deposition, and is used as a gate electrode of the device;

[0058] S900, refer to Figure 8 As shown, an isolation dielectric layer 11 is formed on the top surface of the N+ region 5 and the second trench region 8 by oxide deposition, and is used as an insulating layer for isolating the gate electrode and the source electrode of the device;

[0059] S1000, refer to Fig. 9 As shown, a Ni metal layer is formed on the top surface of the N+ region 5 and in the first trench region 6 by Ni metal sputtering, and then a front ohmic alloy layer 12 is formed by alloying annealing;

[0060] The thickness of the Ni metal in step S1000 is 100 nm.

[0061] S1100, reference Fig.10 As shown, a layer of front electrode metal 13 is formed on the device by Al metal sputtering, which is used as the source electrode of the device;

[0062] The thickness of the front electrode metal 13 in step S1100 is 5000 nm.

[0063] S1200, refer to Fig.11 As shown, a Ni metal layer is formed on the bottom surface of the Epi layer 3 by Ni metal sputtering, and then a back ohmic alloy layer 14 is formed by laser annealing;

[0064] The thickness of the Ni metal in step S1200 is 100 nm.

[0065] S1300, refer to Fig.12 As shown, a layer of back electrode metal 15 is formed on the bottom surface of the back ohmic alloy layer 14 by Ti / Ni / Ag or Ni / Pd / Au metal evaporation method, and is used as a drain electrode of the device;

[0066] The thickness of the Ti / Ni / Ag or Ni / Pd / Au metal in step S1300 is 30nm / 300nm / 1200nm.

[0067] A SiC UMOSFET with an integrated Schottky diode, comprising a back electrode metal 15, a back ohmic alloy layer 14, an Epi layer 3 and a front electrode metal 13 arranged in sequence from bottom to top;

[0068] The Epi layer 3 is provided with:

[0069] A P-body region 4 extending downward from the top surface of the Epi layer 3;

[0070] An N+ region 5 extending downward from a top surface of the P-body region 4;

[0071] A first trench region 6 extends downward from the top surface of the N+ region 5 to below the P-body region 4, that is, is located in the Drift layer 2;

[0072] A P+ region 7 extends downward from the bottom of the first trench region 6 and is connected to a corner of the bottom of the first trench region 6; the P+ region 7 is located in the Drift layer 2;

[0073] A second trench region 8 extends downward from the top surface of the N+ region 5 to below the P-body region 4; the bottom of the second trench region 8 is located above the bottom of the first trench region 6;

[0074] A gate oxide layer 9 is arranged on the groove wall and the groove bottom of the second groove region 8;

[0075] A Poly layer 10, filled in the second trench region 8 and connected to the gate oxide layer 9;

[0076] An isolation dielectric layer 11, located on the top of the first trench region 6, and connected to the N+ region 5, the second trench region 8 and the Poly layer 10 respectively;

[0077] The front ohmic alloy layer 12 extends from the top surface of the N+ region 5 to the bottom of the first trench region 6 , is connected to the P+ region 7 at the bottom, and is connected to the isolation dielectric layer 11 at the side of the top.

[0078] The bottom of the front electrode metal 13 extends into the first trench region 6 and is connected to the front ohmic alloy layer 12 .

[0079] The cross section of the first groove region 6 is in a V-shaped structure; the V-shape allows the sputtered Ni metal to better cover the surface of the front ohmic alloy layer when the front ohmic alloy layer is subsequently formed, thereby better forming the ohmic alloy layer 12 .

[0080] The cross section of the second trench region 8 is a U-shaped structure.

[0081] The Epi layer 3 includes a Sub layer 1 and a Drift layer 2 which are sequentially connected from bottom to top.

[0082] Beneficial effects of the utility model:

[0083] 1. Improve the reliability of the gate oxide layer of the device:

[0084] Since SiC MOSFET contains C element in its SiC material, many defects such as C clusters, dangling bonds, oxygen vacancies, etc. will be generated during the thermal oxidation growth of the gate oxide layer, resulting in a large interface state density and many defects at the SiC / SiO2 interface, which deteriorates the quality of the gate oxide layer. In the trench-type SiC MOSFET, the trench gate oxide layer will easily cause electric field concentration at the bottom corner due to the curvature effect, further aggravating the probability of premature breakdown failure of the gate oxide layer. The utility model is provided with two trench regions in the trench-type SiCMOSFET device, and the space depletion layer between the heavily doped P+ region and the N-type drift layer of the first trench region is used to protect the gate oxide layer of the second trench region, thereby avoiding premature breakdown failure of the gate oxide layer and improving the reliability of use.

[0085] 2. Reduce the bipolar degradation effect of the device: Conventional SiC MOSFETs integrate an anti-parallel PN junction body diode to achieve freewheeling protection for the device. However, in this process, the holes in the P region will enter the N-type drift layer, causing the holes and electrons to recombine, which can easily cause the lattice defects in the drift layer to spread, causing the bipolar degradation effect, and ultimately deteriorating the performance of the device. The utility model integrates an SBD structure on the sidewall of the first trench area, converting the PN junction body diode originally used as the freewheeling path into an SBD, thereby preventing the holes in the P region from entering the drift layer and reducing the occurrence of the bipolar degradation effect of the device.

Claims

1. SiC UMOSFET with integrated Schottky diode, characterized in that: It comprises a back electrode metal (15), a back ohmic alloy layer (14), an Epi layer (3) and a front electrode metal (13) which are arranged in sequence from bottom to top; The Epi layer (3) is provided with: A P-body region (4) extending downward from the top surface of the Epi layer (3); An N+ region (5) extending downward from a top surface of the P-body region (4); A first trench region (6) extends downward from the top surface of the N+ region (5) to below the P-body region (4), and is located in the Drift layer (2); the cross section of the first trench region (6) is a V-shaped structure; A P+ region (7) extending downward from the bottom of the first trench region (6) and connected to a corner of the bottom of the first trench region (6); the P+ region (7) is located in the Drift layer (2); A second trench region (8) extending downward from the top surface of the N+ region (5) to below the P-body region (4); the bottom of the second trench region (8) is located above the bottom of the first trench region (6); A gate oxide layer (9) is arranged on the groove wall and groove bottom of the second groove region (8); A Poly layer (10) filled in the second trench region (8) and connected to the gate oxide layer (9); An isolation dielectric layer (11), located on the top of the first trench region (6), and connected to the N+ region (5), the second trench region (8) and the Poly layer (10) respectively; The front ohmic alloy layer (12) extends from the top surface of the N+ region (5) to the bottom of the first trench region (6), the bottom is connected to the P+ region (7), and the side edge of the top is connected to the isolation dielectric layer (11).

2. The SiC UMOSFET with integrated Schottky diode according to claim 1, characterized in that: The bottom of the front electrode metal (13) extends into the first groove area (6) and is connected to the front ohmic alloy layer (12).

3. The SiC UMOSFET with integrated Schottky diode according to claim 1, characterized in that: The cross section of the second groove region (8) is a U-shaped structure.

4. The SiC UMOSFET with integrated Schottky diode according to claim 1, characterized in that: The Epi layer (3) includes a Sub layer (1) and a Drift layer (2) which are sequentially connected from bottom to top.

5. The SiC UMOSFET with integrated Schottky diode according to claim 1, characterized in that: The thickness of the front electrode metal (13) is 5000nm.

6. The SiC UMOSFET with integrated Schottky diode according to claim 1, characterized in that: A layer of back electrode metal (15) is formed on the bottom surface of the back ohmic alloy layer (14) by evaporating Ti / Ni / Ag or Ni / Pd / Au metal; The thickness of Ti / Ni / Ag or Ni / Pd / Au metals are 30nm / 300nm / 1200nm respectively.

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