Semiconductor structure

Abstract

The utility model provides a semiconductor structure. In one embodiment, an exemplary semiconductor structure includes a source / drain feature over a substrate; a metal gate structure extending longitudinally in a first direction and adjacent to the source / drain feature; a gate isolation structure longitudinally extending in a second direction substantially perpendicular to the first direction; and a source / drain contact electrically coupled to the source / drain feature and including a first portion directly above the source / drain feature and a second portion extending from the first portion along the first direction. In an embodiment, a gate isolation structure divides a metal gate structure into two isolated portions. In an embodiment, the first portion has a first width in the second direction and the second portion has a second width in the second direction, the first width being greater than the second width.

Description

Technical Field

[0001] An embodiment of the utility model relates to a semiconductor structure, and in particular to a semiconductor structure with a gate isolation structure. Background Art

[0002] The semiconductor integrated circuit (IC) industry has experienced exponential growth. Technological advances in IC materials and design have produced several generations of ICs, each with smaller and more complex circuits than the previous generation. In the evolution of ICs, functional density (i.e., the number of interconnected devices per unit chip area) has generally increased, while geometry size (i.e., the smallest component (or line segment) that can be created using a manufacturing process) has decreased. This scaling down generally provides benefits by increasing production efficiency and reducing associated costs.

[0003] As integrated circuits (ICs) move toward smaller technology nodes, electrical shorts may exist between adjacent metal gates and source / drain contacts disposed over source / drain features. This may affect the overall performance of the IC device. Although existing source / drain contacts are generally adequate for their intended purpose, they are not satisfactory in all respects. Utility Model Content

[0004] The purpose of the present disclosure is to provide a semiconductor structure to solve at least one of the above problems.

[0005] The present disclosure provides a semiconductor structure. The semiconductor structure includes a source / drain feature located above a substrate, a metal gate structure extending longitudinally along a first direction and adjacent to the source / drain feature, and a gate isolation structure extending longitudinally along a second direction substantially perpendicular to the first direction. The gate isolation structure divides the metal gate structure into two isolated parts. The semiconductor structure also includes a source / drain contact, which is electrically coupled to the source / drain feature and includes a first portion located directly above the source / drain feature, and a second portion extending from the first portion along the first direction. The first portion has a first width along the second direction, and the second portion has a second width along the second direction. The first width is greater than the second width.

[0006] According to one embodiment of the present disclosure, the second portion of the source / drain contact includes two edges that are bent inwardly in a top view.

[0007] According to one embodiment of the present disclosure, in a cross-sectional view, a boundary of the gate isolation structure is located directly below the second portion of the source / drain contact.

[0008] According to one embodiment of the present disclosure, it also includes: an isolation feature located above the above-mentioned substrate and below the above-mentioned gate isolation structure; and a plurality of gate spacers extending longitudinally along the above-mentioned first direction and including a first portion located on a plurality of side walls of the above-mentioned metal gate structure, and a second portion arranged directly above the above-mentioned isolation feature, wherein the above-mentioned second portion of the above-mentioned gate spacer is located directly below a first portion of the above-mentioned gate isolation structure.

[0009] According to one embodiment of the present disclosure, the source / drain feature is a first source / drain feature and the source / drain contact is a first source / drain contact, wherein the semiconductor structure further includes: a second source / drain feature, so that the metal gate structure is arranged between the first source / drain feature and the second source / drain feature; and a second source / drain contact, electrically coupled to the second source / drain feature, and having a third portion located directly above the second source / drain feature, and a fourth portion extending from the third portion along the first direction; wherein the third portion has a third width, and the fourth portion has a fourth width smaller than the third width.

[0010] The present disclosure provides a semiconductor structure. The semiconductor structure includes a first source / drain feature and a second source / drain feature located above a substrate, a first metal gate structure and a second metal gate structure extending longitudinally along a first direction above the substrate and adjacent to the first source / drain feature and the second source / drain feature, respectively, and a gate isolation structure extending longitudinally along a second direction substantially perpendicular to the first direction. The first metal gate structure and the second metal gate structure are isolated by the gate isolation structure. The semiconductor structure also includes a source / drain contact, the source / drain contact includes two first portions located directly above the first source / drain feature and the second source / drain feature, and a second portion connecting the two first portions. The second portion is adjacent to the gate isolation structure, and the two first portions and the second portion have different widths.

[0011] According to one embodiment of the present disclosure, the second portion of the source / drain contact is located directly above a portion of the gate isolation structure and is in direct contact with a side wall of the gate isolation structure.

[0012] According to one embodiment of the present disclosure, it also includes: an isolation feature, arranged between the above-mentioned first source / drain feature and the above-mentioned second source / drain feature; and a plurality of gate spacers, having a first portion located on a plurality of side walls of the above-mentioned first metal gate structure and the above-mentioned second metal gate structure, and a second portion arranged directly above the above-mentioned isolation feature, wherein the above-mentioned second portion of the above-mentioned source / drain contact is separated from the above-mentioned gate isolation structure by the above-mentioned second portion of the above-mentioned gate spacer.

[0013] The present disclosure provides a semiconductor structure in an embodiment. The semiconductor structure includes a substrate, and a first active region and a second active region located above the substrate and parallel to each other. The first active region includes a first source / drain feature, and the second active region includes a second source / drain feature. The semiconductor structure also includes a metal gate structure, which extends longitudinally along a first direction, is located above the first active region and the second active region, and is adjacent to the first source / drain feature and the second source / drain feature. The semiconductor structure also includes a source / drain contact, and the source / drain contact includes two first portions located directly above the first source / drain feature and the second source / drain feature, respectively, and a second portion extending between the two first portions. The two first portions have a first width along a second direction substantially perpendicular to the first direction, and the second portion has a second width along the second direction. The first width is greater than the second width.

[0014] According to one embodiment of the present disclosure, it also includes a first gate isolation structure and a second gate isolation structure, wherein the first gate isolation structure and the second gate isolation structure extend longitudinally along the second direction and are located between the first active area and the second active area, wherein the first gate isolation structure divides the metal gate structure into two isolated parts, and wherein the second part of the source / drain contact is located between the first gate isolation structure and the second gate isolation structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] The disclosed method can be better understood from the following embodiments and the accompanying drawings. It should be emphasized that, in accordance with standard industry practice, various features are not drawn to scale and are only used for illustrative purposes. In fact, the size of various features may be arbitrarily increased or decreased to make the discussion clear and understandable.

[0016] Figure 1 The present invention is a flowchart of a method for forming a semiconductor structure according to one or more embodiments of the present invention.

[0017] Figure 2A , Figure 3A , Figure 4A , Figure 5A and Fig. 6A As shown in various ways according to the present disclosure, Figure 1 A partial top view of an exemplary workpiece during various manufacturing stages of a method of.

[0018] Figure 2B , Figure 3B , Figure 4B , Figure 5B and Figure 6B As shown in various ways according to the present disclosure, Figure 1 During the various manufacturing stages of the method, the workpiece is separately Figure 2A , Figure 3A , Figure 4A , Figure 5A and Fig. 6A Partial cross-sectional view of line segment BB'.

[0019] Figure 2C , Figure 3C , Figure 4C , Figure 5C and Figure 6C As shown in various ways according to the present disclosure, Figure 1 During the various manufacturing stages of the method, the workpiece is separately Figure 2A , Figure 3A , Figure 4A , Figure 5A and Fig. 6A Partial cross-sectional view of line segment CC'.

[0020] Figure 5D and Fig.6D As shown in various ways according to the present disclosure, Figure 1 An enlarged partial top view of a portion of a workpiece during various manufacturing stages of a method.

[0021] Fig. 7A FIG. 1 is a partial top view of a first alternative working piece shown in various embodiments according to the present disclosure.

[0022] Figure 7B and Figure 7C As shown in various ways according to the present disclosure, respectively along Fig. 7A A partial cross-sectional view of a first alternative working piece taken along line segments BB' and CC'.

[0023] Fig. 8A FIG. 1 is a partial top view of a second alternative working piece shown in various embodiments according to the present disclosure.

[0024] Figure 8B and Figure 8C As shown in various ways according to the present disclosure, respectively along Fig. 8A A partial cross-sectional view of a second alternative working piece taken along line segments BB' and CC'.

[0025] Fig.9A FIG. 1 is a partial top view of a third alternative working piece according to various embodiments of the present disclosure.

[0026] Fig. 9B As shown in various ways according to the present disclosure, along Fig.9A A partial cross-sectional view of a third alternative working piece taken along line segment BB'.

[0027] Fig.10 FIG. 1 is a partial cross-sectional view of a fourth alternative working piece taken along line segment CC′ according to various embodiments of the present disclosure.

[0028] Fig.11A FIG. 1 is a partial top view of a fifth alternative working piece according to various embodiments of the present disclosure.

[0029] Fig. 11B As shown in various ways according to the present disclosure, along Fig.11A A partial cross-sectional view of a fifth alternative working piece taken along line segment CC'.

[0030] Fig. 11C FIG. 1 is an enlarged partial top view of a portion of a fifth alternative working piece according to various embodiments of the present disclosure.

[0031] Fig. 12A FIG. 1 is a partial top view of a sixth alternative working piece shown in various embodiments according to the present disclosure.

[0032] Fig. 12B As shown in various ways according to the present disclosure, along Fig. 12A A partial cross-sectional view of a sixth alternative working piece taken along line segment CC'.

[0033] Fig.13A FIG. 1 is a partial top view of a seventh alternative working piece according to various embodiments of the present disclosure.

[0034] Fig. 13B FIG. 1 is an enlarged partial top view of a portion of a seventh alternative working piece according to various embodiments of the present disclosure.

[0035] The reference numerals are as follows:

[0036] 100: Method

[0037] 102-112: Blocks

[0038] 200:Workpiece

[0039] 202:Substrate

[0040] 204: Active area

[0041] 204c: Channel area

[0042] 204sd: Source / Drain Region

[0043] 208: Isolation Features

[0044] 210a: Metal gate structure

[0045] 210a-1: Part 1 / Metal Gate Structure

[0046] 210a-2: Second part / metal gate structure

[0047] 210b: Metal gate structure

[0048] 210b-1: Partial / Metal Gate Structure

[0049] 210b-2: Partial / Metal Gate Structure

[0050] 212: Gate spacer

[0051] 212a: Remaining gate spacer

[0052] 212b: Remaining gate spacer

[0053] 214: Source / Drain Characteristics

[0054] 214a-214f: Source / Drain Characteristics

[0055] 218a: Source / drain contact

[0056] 218a-1: Part I

[0057] 218a-2: Part 2

[0058] 218b: Source / drain contact

[0059] 218b-1: Part I

[0060] 218b-2: Part 2

[0061] 218c: Source / drain contact

[0062] 218d: Source / drain contact

[0063] 218d-1: Part 1

[0064] 218d-2: Part 2

[0065] 218e: Source / drain contact

[0066] 218e-1: Part I

[0067] 218e-2: Part 2

[0068] 219: Area

[0069] 220a: Edge

[0070] 220a-1: Edge

[0071] 220a-3: Edge

[0072] 220b-1: The First Edge

[0073] 220b-2: The Second Edge

[0074] 220b-3: Edge

[0075] 220b-4: Edge

[0076] 222: Gate isolation structure

[0077] 222a: first dielectric layer

[0078] 222b: second dielectric layer

[0079] 222e: End

[0080] 222-1: Part 1

[0081] 222-2: Part 2

[0082] 222L: first gate isolation structure

[0083] 222R: Second gate isolation structure

[0084] 223: Boundary

[0085] 228: Dielectric structure

[0086] 228a: Remaining dielectric structure

[0087] 232: Dielectric barrier layer

[0088] 236: Dielectric structure

[0089] 240: Dielectric structure

[0090] 244: Gate contact through hole

[0091] 250: Contact through hole

[0092] 252:SAC layer

[0093] 252': SAC layer

[0094] 256: Gate isolation trench

[0095] 260a: Groove

[0096] 260a-1: Part 1

[0097] 260a-2: Part 2

[0098] 260b: Groove

[0099] 260b-1: Part I

[0100] 260b-2: Part 2

[0101] 260c: Groove

[0102] 300-900:Working parts

[0103] A-A',B-B',C-C': Line segment

[0104] D1-D9: Depth

[0105] W1-W6: Width DETAILED DESCRIPTION

[0106] The following disclosure provides many different embodiments or examples for implementing different features of the present disclosure. Specific examples of the various components and arrangements of the present disclosure are described below to simplify the description. Of course, these examples are not intended to limit the present disclosure. For example, if the description has a first feature formed on or above a second feature, it may include an embodiment in which the first feature and the second feature are formed in direct contact, and it may also include an embodiment in which an additional feature is formed between the first feature and the second feature so that the first feature and the second feature are not in direct contact. In addition, the present disclosure may repeat reference numbers and / or letters in multiple examples. The purpose of this repetition is to simplify and clarify, and does not itself specify the relationship between the various embodiments and / or configurations discussed.

[0107] Further, the present disclosure may use spatially relative terminology, such as "below," "below," "below," "above," "above," and the like, to describe the relationship of one element or feature to other elements or features in the drawings. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the drawings. The device may be oriented in different orientations (rotated 90 degrees or at other orientations), and the spatially relative terms used herein interpreted accordingly.

[0108] Further, when the terms "about," "approximately," and the like are used to describe a range of numbers, the terms are intended to encompass numbers within a reasonable range that takes into account variations inherently occurring during manufacturing as understood by those of ordinary skill in the art. For example, based on known manufacturing tolerances associated with manufacturing a feature having a characteristic associated with a number, a numerical value or range encompasses a reasonable range that includes the number, such as within + / -10% of the number. For example, a material layer having a thickness of "about 5 nanometers (nm)" may encompass a range of sizes from 4.25 nm to 5.75 nm, where the manufacturing tolerance associated with depositing the material layer known to those of ordinary skill in the art is + / -15%.

[0109] As integrated circuit (IC) technology moves toward smaller technology nodes, multi-gate devices are introduced to improve gate control by increasing gate-channel coupling, reducing off-state current, and reducing short-channel effect (SCE). Multi-gate generally refers to a device having a metal gate structure or a portion of a metal gate structure disposed on more than one side of the channel region. FinFETs and multi-bridge-channel (MBC) transistors are examples of multi-gate devices and have become popular and highly anticipated candidates for high performance and low leakage applications. FinFETs have an elevated channel that is wrapped by a gate on more than one side (e.g., the gate wraps around the top and sidewalls of a "fin" of semiconductor material extending from a substrate). MBC transistors have a metal gate structure that can extend and partially or completely surround the channel region to provide access to the channel region on two or more sides. Because its metal gate structure surrounds the channel region, the MBC transistor may also be referred to as a surrounding gate transistor (SGT) or a gate-all-around (GAA) transistor. The channel region of the MBC transistor may be formed by nanowires, nanosheets, other nanostructures, and / or other suitable structures. The shape of the channel region also gives the MBC transistor alternative names, such as nanosheet transistors or nanowire transistors. Many variations of the MBC transistor have been proposed to reduce the cell size, such as those known as fishbone structures or forksheet structures. In the forksheet structure, stacks of adjacent channel components may be separated by dielectric walls (also known as dielectric fins). The dielectric walls have a height that is generally substantially equal to or greater than the height of the topmost channel component or the height of the source / drain feature. Complementary metal-oxide-semiconductor field effect transistor (CMOSFET or CFET) dominates the semiconductor industry due to its high noise immunity and low static power consumption. CFET includes an n-type FET (NFET) and a p-type FET (PFET) arranged side by side on the same substrate, and the NFET and PFET share the same structure.In some embodiments, both the NFET and the PFET are planar devices, both are FinFETs, or both are MBC transistors.

[0110] The semiconductor structure may have an isolation feature between multiple segments of the metal gate structure, which isolation feature is called a gate isolation structure or a gate-cut structure. In one example, the metal gate structure may be cut into two or more parts and then separated by a gate isolation structure in a process called cutting metal gate (CMG). The gate isolation structure is longitudinally oriented in a direction substantially perpendicular to the direction of the metal gate structure. The formation of the gate isolation structure may be performed by forming a groove by a patterning process and filling the groove with one or more dielectric materials by deposition. The patterning process includes a photolithography process and an etching process, and a hard mask may be used to define the area for forming the gate isolation structure.

[0111] The semiconductor structure may have a source / drain contact formed over and electrically coupled to one or more source / drain features. An exemplary process for forming the source / drain contact may include forming a source / drain contact opening exposing the source / drain features, and then forming a conductive layer in the source / drain contact opening. However, during the formation of the source / drain contact opening, due to reasons such as etching variations, photomask coverage of a photolithography process, and / or critical dimension uniformity (CDU) limitations, the source / drain contact opening may be enlarged and / or offset, resulting in an electrical short between a segment of the metal gate structure and the source / drain contact formed in the source / drain contact opening.

[0112] The present disclosure provides a semiconductor structure and a method for forming the same. In one embodiment, the semiconductor structure includes a source / drain contact, the source / drain contact having a first portion disposed directly above the source / drain feature, and a second portion disposed directly above the isolation feature and adjacent to the gate isolation structure. In an exemplary embodiment, in order to reduce or avoid electrical shorting between a fragment of a metal gate structure (e.g., a metal gate structure cut by a gate isolation structure) and the source / drain contact, the second portion of the source / drain contact has a reduced width compared to the first portion. In some embodiments, the second portion of the source / drain contact also has a reduced depth compared to the first portion of the source / drain contact.

[0113] Now, various aspects of the present disclosure will be described in more detail with reference to the accompanying drawings. In this regard, Figure 1According to an embodiment of the present disclosure, a flow chart of a method 100 for forming a semiconductor structure is shown. FIG. 2A to FIG. 6D Describing method 100, FIG. 2A to FIG. 6D 1 is a partial top view or cross-sectional view of a workpiece 200 at different stages of manufacture according to an embodiment of method 100. Method 100 is merely an example and is not intended to limit the present disclosure to the contents explicitly described therein. Additional operations may be provided before, during, or after method 100, and for additional embodiments of the method, some of the operations described may be replaced, eliminated, or moved. To simplify the description, not all operations will be described in detail herein. Because workpiece 200 will be manufactured into a semiconductor structure at the end of the manufacturing process, workpiece 200 may be referred to as semiconductor structure 200 as required by the context. 7A to 13B 1 and 2 are partial top views or cross-sectional views of workpieces 300, 400, 500, 600, 700, 800, and 900, respectively, according to various alternatives of the present disclosure. Workpieces 300, 400, 500, 600, 700, 800, and 900 may be referred to as semiconductor structures 300, 400, 500, 600, 700, 800, and 900, respectively. For the avoidance of doubt, FIG. 2A to FIG. 13B The X, Y and Z directions in the reference numeral 2 are perpendicular to each other and are used in a consistent manner throughout the present disclosure. Throughout the present disclosure, similar reference symbols represent similar features unless otherwise specified.

[0114] Reference Figure 1 and FIG. 2A to FIG. 2C The method 100 includes block 102 , in which a work piece 200 is received. Figure 2A As shown in various ways according to the present disclosure, Figure 1 FIG. 2 is a partial top view of a workpiece 200 during various stages of operation of the method. Figure 2B and Figure 2C They are shown along Figure 2A The partial cross-sectional view of the workpiece 200 is taken along line segment BB′ and line segment CC′.

[0115] like FIG. 2A to FIG. 2CAs shown, the workpiece 200 includes a substrate 202. In one embodiment, the substrate 202 may be a silicon (Si) substrate. In some other embodiments, the substrate 202 may include other semiconductor materials, such as germanium (Ge), silicon germanium (SiGe) or III-V semiconductor materials. Exemplary III-V semiconductor materials may include gallium arsenide (GaAs), indium phosphide (InP), gallium phosphide (GaP), gallium nitride (GaN), gallium arsenide phosphide (GaAsP), aluminum indium arsenide (AlInAs), aluminum gallium arsenide (AlGaAs), gallium indium phosphide (GaInP) and indium gallium arsenide (InGaAs). The substrate 202 may include a plurality of n-type well regions and a plurality of p-type well regions. The p-type well region may be doped with a p-type dopant (i.e., boron (B)). The n-type well region may be doped with an n-type dopant (i.e., phosphorus (P) or arsenic (As)).

[0116] In some embodiments, the workpiece 200 includes a plurality of active regions 204 (eg, fin-shaped active regions). Figure 2A As shown, each active region 204 extends longitudinally along the X direction and is divided into a channel region 204c overlapping with metal gate structures 210a and 210b (to be described below), and a source / drain region 204sd not overlapping with the metal gate structures 210a and 210b. The source / drain region 204sd may be referred to as a source region or a drain region, and whether it is referred to individually or collectively depends on the context. Figure 2A The number of active regions 204 and the number of metal gate structures 210a and 210b shown in the figure are for illustrative purposes only and should not be construed as limiting the scope of the present disclosure. In the illustrated embodiment, the active region 204 is disposed above the substrate 202. In an embodiment where the workpiece 200 includes a FinFET, the active region 204 may be formed of a single semiconductor element (e.g., Si). In an embodiment where the workpiece 200 includes an MBC transistor, the active region 204 includes one or more nanostructures (e.g., multiple channel layers surrounded by metal gate structures 210a / 210b). Each nanostructure may be formed of silicon (Si).

[0117] In this embodiment, the workpiece 200 also includes an isolation feature 208 (eg, Figure 2C), an isolation feature 208 is formed around each active region 204 to isolate two adjacent active regions 204. The isolation feature 208 may also be referred to as a shallow trench isolation (STI) feature, and may include silicon oxide, silicon oxynitride, fluorine-doped silicate glass (FSG), a low-k dielectric, a combination thereof, and / or other suitable materials. In some embodiments, the workpiece 200 includes a dielectric structure 228 (described below) disposed above the isolation feature 208 and the source / drain features 214a-214f (described below).

[0118] In some embodiments, the workpiece 200 includes metal gate structures 210a and 210b disposed above the channel region 204c of the active region 204 and extending longitudinally along the Y direction, such that the metal gate structure 210a has a first portion interposed between source / drain features 214a and 214c and a second portion interposed between source / drain features 214b and 214d, and the metal gate structure 210b has a first portion interposed between source / drain features 214c and 214e and a second portion interposed between source / drain features 214d and 214f. Each of the metal gate structures 210a and 210b includes a high-k dielectric layer (i.e., having a dielectric constant greater than the dielectric constant of silicon oxide of about 3.9; not shown) disposed above the active region 204, and a metal gate electrode (not shown) disposed above the high-k dielectric layer. The metal gate electrode may further include at least one work function metal layer disposed above the high-k dielectric layer and a bulk conductive layer disposed thereon. The work function metal layer may be a p-type or n-type work function metal layer. Exemplary work function materials include TiN, TaN, WN, ZrSi2, MoSi2, TaSi2, NiSi2, Ti, TaAl, TaAlC, TiAlN, TaC, TaCN, TaSiN, other suitable work function materials, or combinations thereof. The bulk conductive layer may include copper (Cu), tungsten (W), aluminum (Al), cobalt (Co), other suitable materials, or combinations thereof. The metal gate structures 210a and 210b may further include many other thin layers (not shown), such as an interfacial layer disposed between the active region 204 and the high-k dielectric layer, a hard mask layer, a capping layer, a barrier layer, other suitable thin layers, or combinations thereof. The various thin layers of the metal gate structures 210a and 210b may be deposited by any suitable method, such as chemical oxidation, thermal oxidation, atomic layer deposition (ALD), chemical vapor deposition (CVD), physical vapor deposition (PVD), electroplating, other suitable methods or combinations thereof. A polishing process such as a chemical mechanical planarization / polishing (CMP) process may be performed to remove excess material from the top surfaces of the metal gate structures 210a and 210b, thereby flattening the top surface of the workpiece 200.

[0119] In some embodiments, the metal gate structures 210a and 210b are formed after other components (e.g., source / drain features 214a-214f) of the workpiece 200 are fabricated. This process is generally referred to as a gate replacement process, and includes forming a dummy gate structure (not shown) as a placeholder for the metal gate structures 210a and 210b, forming the source / drain features 214a-214f, forming a dielectric structure 228 over the dummy gate structure and the source / drain features 214a-214f, planarizing the dielectric structure 228 by, for example, CMP to expose the top surface of the dummy gate structure, removing the dummy gate structure in the dielectric structure 228 to form a trench exposing the channel region 204c of the active region 204, and forming the metal gate structures 210a and 210b in the trench to complete the gate replacement process.

[0120] In some embodiments, the dielectric structure 228 may include a contact etch-stop layer (CESL) and an interlayer dielectric (ILD) layer formed on the CESL. The ILD layer includes a dielectric material, such as tetraethylorthosilicate (TEOS), silicon oxide, a low-k dielectric material, doped silicon oxide, such as borophosphosilicate glass (BPSG), phosphosilicate glass (PSG), FSG, boron doped silicate glass (BSG), other suitable dielectric materials or combinations thereof. The ILD layer may include a multilayer structure having a variety of dielectric materials and may be formed by a deposition process, such as CVD, flowable CVD (FCVD), spin-on glass (SOG), other suitable methods or combinations thereof. The CESL may include silicon nitride, silicon oxynitride, silicon nitride with oxygen or carbon elements, other suitable materials, or combinations thereof, and may be formed by CVD, PVD, ALD, other suitable methods, or combinations thereof. The ILD layer may be deposited after depositing the CESL.

[0121] In some embodiments, the workpiece 200 includes source / drain features 214a-214f formed in and / or on the source / drain region 204sd of the active area 204, each of the source / drain features 214a-214f being disposed adjacent to the metal gate structures 210a and 210b. The source / drain features 214a-214f may be individually or collectively referred to as source / drain features 214. The source / drain features 214a-214f may be formed by any suitable technique, such as an etching process followed by one or more epitaxial growth processes. In one example, one or more etching processes are performed to remove portions of the active area 204 to form a recess (not shown) in the source / drain region 204sd. A cleaning process may be performed to clean the recess using a hydrofluoric acid (HF) solution or other suitable solution. Subsequently, one or more epitaxial growth processes are performed to grow epitaxial source / drain features in the recess. Each of the source / drain features 214a-214f may be adapted to form a p-type FinFET device, or an n-type FinFET device. The p-type source / drain features may include one or more layers of epitaxial silicon germanium (epitaxial SiGe) and may be doped with p-type dopants, such as boron, germanium, indium, and / or other p-type dopants. The n-type source / drain features may include one or more layers of epitaxial silicon (epitaxial Si) or epitaxial silicon carbide (epitaxial SiC) and may be doped with n-type dopants, such as arsenic, phosphorus, and / or other n-type dopants.

[0122] In some embodiments, the workpiece 200 further includes a gate spacer 212 disposed on the sidewalls of the metal gate structures 210a and 210b. The gate spacer 212 may include a dielectric material, such as an oxygen-containing material (e.g., silicon oxide, silicon oxycarbide, aluminum oxide, aluminum oxynitride, hafnium oxide, titanium oxide, aluminum zirconium oxide, zinc oxide, tantalum oxide, lanthanum oxide, yttrium oxide, silicon oxycarbonitride, etc.), a nitrogen-containing material (e.g., tantalum carbonitride, silicon nitride (SiN), zirconium nitride, silicon carbonitride, etc.), a silicon-containing material (e.g., hafnium silicide, silicon, zirconium silicide, etc.), other suitable materials or combinations thereof. The gate spacer 212 may be a single-layer structure or a multi-layer structure. It should be noted that the composition of the gate spacer 212 is different from the composition of the surrounding dielectric components, so that during a subsequent etching process, there may be an etching selectivity between the gate spacer 212 and the surrounding dielectric components. In one embodiment, the gate spacer 212 includes SiN. The gate spacers 212 may be formed by first depositing a blanket layer of spacer material over the workpiece 200 , and then performing an anisotropic etching process to remove portions of the spacer material to form the gate spacers 212 .

[0123] Reference Figure 1 and FIG. 3A to FIG. 3CThe method 100 includes block 104 , in which a gate isolation trench 256 is formed to divide the metal gate structure 210 a into two parts. Figure 3A A partial top view of the workpiece 200 is depicted, and Figure 3B and Figure 3C They are shown along Figure 3A The partial cross-sectional view of the workpiece 200 is taken along the line segment BB' and the line segment CC'. In some embodiments, the gate isolation trench 256 extends longitudinally along the X direction in a top view.

[0124] The gate isolation trench 256 may be formed using any suitable method. In one embodiment, a photolithography process and an etching process are performed on the workpiece 200 to form the gate isolation trench 256. Portions of the metal gate structure 210a, the gate spacer 212, the dielectric structure 228 and / or the isolation feature 208 are removed to form the gate isolation trench 256. The etching process may include wet etching, dry etching, or a combination thereof, and etches through the conductive material of the metal gate structure 210a. The etching process may use one or more etchants. In some embodiments, the gate isolation trench 256 includes tapered sidewalls. In the present embodiment, the gate isolation trench 256 extends through the metal gate structure 210a and extends downward into the isolation feature 208, such as Figure 3C As shown. In some other embodiments, etching may stop at the top surface of the isolation feature 208. The formation of the gate isolation trench 256 cuts the metal gate structure 210a into a first portion 210a-1 and a second portion 210a-2 (also referred to as the first metal gate structure 210a-1 and the second metal gate structure 210a-2, respectively). The first portion 210a-1 and the second portion 210a-2 may also be collectively referred to as the metal gate structure 210a. Figure 3C The dashed rectangle shown in FIG. 1 is the metal gate structure 210 a projected on the cross-sectional view along the line segment CC′.

[0125] Reference Figure 1 and FIG. 4A to FIG. 4C The method 100 includes block 106 , in which a gate isolation structure 222 is formed in the gate isolation trench 256 . Figure 4A A partial top view of the workpiece 200 is depicted, and Figure 4B and Figure 4C They are shown along Figure 4A The partial cross-sectional view of the workpiece 200 is taken along line segments BB' and CC'. The gate isolation structure 222 electrically and physically cuts / divides the metal gate structure 210a into two isolated portions (eg, a first portion 210a-1 and a second portion 210a-2).

[0126] The gate isolation structure 222 can cut and thus directly contact the metal gate electrodes of the metal gate structures 210a-1 and 210a-2. In one embodiment, the gate isolation structure 222 extends into the isolation feature 208. In some embodiments, the gate isolation structure 222 includes a plurality of thin layers, such as a first dielectric layer 222a and a second dielectric layer 222b embedded in the first dielectric layer 222a. The formation of the gate isolation structure 222 may include conformally depositing the first dielectric layer 222a over the workpiece 200, depositing the second dielectric layer 222b over the first dielectric layer 222a to fill the remaining portion of the gate isolation trench 256, and performing a planarization process on the workpiece 200 to remove excess portions of the first dielectric layer 222a and the second dielectric layer 222b located over the metal gate structures 210a and 210b, and define the final structure of the gate isolation structure 222. The term "conformally" may be used herein to facilitate describing a thin layer having a substantially uniform thickness across various regions of the workpiece 200. In some embodiments, the first dielectric layer 222a includes silicon nitride (SiN) and may be deposited by atomic layer deposition (ALD), chemical vapor deposition (CVD), or any other suitable deposition process. In one embodiment, the first dielectric layer 222a includes silicon nitride. In some embodiments, the second dielectric layer 222b includes a high-k dielectric material, a low-k dielectric material, other suitable materials, or combinations thereof. Exemplary materials for the second dielectric layer 222b include silicon oxide (SiO and SiO 2 ), silicon nitride, silicon carbide (SiC), silicon oxynitride (SiON), silicon oxycarbide (SiOC), silicon carbonitride (SiCN), silicon oxycarbonitride (SiCON), aluminum oxide, zirconium silicate (ZrSiO 4 ) and hafnium silicate (HfSiO 4 ). In some embodiments, the second dielectric layer 222b includes silicon oxide. The deposition of the second dielectric layer 222b can be performed by CVD, plasma-enhanced CVD (PECVD), flow CVD, PVD, ALD, other suitable methods or combinations thereof. In one embodiment, the second dielectric layer 222b includes silicon oxide. In some embodiments, the gate isolation structure 222 may be a single-layer structure. In some embodiments, the gate isolation structure 222 and the gate spacer 212 include different dielectric materials. In some embodiments, the dielectric material included in the gate spacer 212 has a dielectric constant greater than the dielectric material of the gate isolation structure 222. In one embodiment, the gate spacer 212 includes silicon nitride, and the gate isolation structure 222 includes silicon oxide.

[0127] Reference Figure 1 and FIG. 5A to FIG. 5D The method 100 includes block 108 , in which trenches (eg, trenches 260 a , 260 b , and / or 260 c ) are formed to expose source / drain features 214 . Figure 5A A partial top view of the workpiece 200 is depicted, and Figure 5B and Figure 5C They are shown along Figure 5A The partial cross-sectional view of the workpiece 200 taken along the line segment BB' and the line segment CC' shown in FIG. Figure 5D An enlarged top view of trenches 260a and 260b is shown.

[0128] In this operation, in order to form the trench 260a or 260b, a combination of a photolithography process and an etching process (e.g., dry etching, wet etching, and / or reactive ion etching (RIE)) is used to remove portions of the dielectric structure 228 and portions of the gate isolation structure 222 to expose the source / drain features 214. In an exemplary process, a hard mask layer and a photoresist are deposited on the workpiece 200. The photoresist layer is then exposed to patterned radiation that penetrates the photomask or is reflected from the photomask, baked in a post-exposure bake process, developed in a developer solution, and then rinsed to form a patterned photoresist layer. The patterned photoresist layer is then used as an etching mask to etch the hard mask layer to form a patterned hard mask layer. The patterned hard mask layer is then used as an etching mask to etch the dielectric structure 228 and the gate isolation structure 222. The etching process may be a dry etching process, including using argon (Ar), fluorine-containing etchants (e.g., SF 6 NF 3 , CH 2 F 2 , CHF 3 , C 4 F 8 and / or C 2 F 6 ), oxygen-containing etchants, chlorine-containing etchants (e.g. Cl 2 , CHCl 3 , CCl 4 and / or BCl 3 ), bromine-containing etchants (e.g. HBr and / or CHBr 3 ), iodine-containing etchant, oxygen, hydrogen, other suitable gases or combinations thereof.

[0129] In this embodiment, along Figure 5AThe cross-sectional view of the workpiece 200 taken along the line segment AA' shown is substantially the same as the cross-sectional view of the workpiece 200 taken along the line BB'. Therefore, in the description of the subsequent process stages, the cross-sectional view of the workpiece 200 taken along the line segment AA' is omitted. It should be understood by those skilled in the art that in those process stages, the cross-sectional views of the workpiece 200 taken along the line segment AA' are substantially mirror images of those cross-sectional views depicted for the cross-sectional views of the workpiece 200 taken along the line segment BB'. Although three trenches 260a-260c are depicted, it should be understood that the workpiece 200 may include any combination and number of trenches 260a-260c located in various relative positions. For example, depending on the position of the gate isolation structure 222, the workpiece may include a trench 260a that exposes the source / drain features 214c and 214d, and a trench 260c that exposes the source / drain features 214e and 214f. In the present embodiment, the trenches 260a, 260b and 260c include tapered sidewalls. In some other embodiments, the trenches 260a, 260b and 260c may include substantially vertical sidewalls.

[0130] In some embodiments, each of the trenches 260a-260c is formed to penetrate into the dielectric structure 228 and / or the gate isolation structure 222. More specifically, in some embodiments, Figure 5A From the top view shown, the gate isolation structure 222 and the trench 260a intersect each other. The trench 260a includes two first portions 260a-1 and a second portion 260a-2 spanning between the two first portions 260a-1. Figure 5D, separated by dotted lines. The two first portions 260a-1 expose source / drain features 214a and 214b, respectively. In some embodiments, the second portion 260a-2 does not overlap with the metal gate structure 210a projected on the cross-sectional view along the line segment CC'. From a top view, the shape of the groove 260a has a non-uniform width along its length. In one embodiment, the two first portions 260a-1 span a width W1 along the X direction and a depth D1 along the Z direction. The width W1 may be substantially equal to or less than the distance between adjacent gate spacers 212 on both sides of each of the grooves 260a, 260b and 260c. In some embodiments, the second portion 260a-2 spans a width W3 along the X direction and a depth D3 along the Z direction. The width W1 is greater than the width W3. In one embodiment, the ratio of the width W3 to the width W1 (i.e., W3 / W1) is in the range of about 0.5 to about 0.95. If W3 / W1 is too small, the contact resistance between the source / drain contact (e.g., source / drain contact 218a to be described below) formed in the trench 260a and the source / drain features (e.g., source / drain features 214a and 214b) thereunder may be too large. If W3 / W1 is too large, the second portion 260a-2 may be too close to the adjacent metal gate structures 210a-1 and 210a-2, so that the electrical short circuit problem between the metal gate structures 210a-1 and 210a-2 and the source / drain contact 218a may persist. In some embodiments, the depth D1 is greater than the depth D3. In one embodiment, the ratio of the depth D3 to the depth D1 is in the range of about 0.3 to about 0.95.

[0131] In some embodiments, Figure 5A From the top view shown in FIG. 1 , the end 222e of the gate isolation structure 222 overlaps the trench 260b. Similar to the trench 260a, the trench 260b includes two first portions 260b-1 and a second portion 260b-2 spanning between the two first portions 260b-1. The two first portions 260b-1 expose the source / drain features 214c and 214d, respectively. In some embodiments, referring to FIG. Figure 5C , a portion of the sidewall of the gate spacer 212 is exposed to the second portion 260b-2. In some embodiments, the second portion 260b-2 does not overlap with the metal gate structure 210a projected on the cross-sectional view along the line segment CC'. From a top view, the groove 260b has a shape with a non-uniform width along its length. In one embodiment, the two first portions 260b-1 span a width W1 along the X direction and a depth D1 along the Z direction. In some embodiments, as Figure 5CAs shown, the second portion 260b-2 spans a width W4 along the X direction and a depth D4 along the Z direction. The width W1 is greater than the width W4. In one embodiment, the ratio of the width W4 to the width W1 (i.e., W4 / W1) is in the range of about 0.7 to about 0.95. If W4 / W1 is too small, the contact resistance between the source / drain contact (e.g., source / drain contact 218b to be described below) formed in the trench 260b and the source / drain features (e.g., source / drain features 214c and 214d) thereunder may be too large. If W4 / W1 is too large, the second portion 260b-2 may be too close to the adjacent metal gate structures 210a-1 and 210a-2, so that the electrical short between the metal gate structures 210a-1 and 210a-2 and the source / drain contact 218b may persist. In some embodiments, the depth D1 is greater than the depth D4. In one embodiment, the ratio of depth D4 to depth D1 is in a range from about 0.5 to about 0.95.

[0132] In some embodiments, the width W4 is equal to or greater than the width W3. In one embodiment, the ratio of the width W3 to the width W4 (i.e., W3 / W4) is in a range of about 0.7 to about 1. If W3 / W4 is too small, the contact resistance between the source / drain contact 218a and the source / drain features thereunder (e.g., the source / drain features 214a and 214b) may be too large, thereby affecting the overall performance of the semiconductor structure, or the second portion 260b-2 of the trench 260b may be too close to the adjacent metal gate structures 210a-1 and 210a-2, so that an electrical short between the metal gate structures 210a-1 and 210a-2 and the source / drain contact 218b may persist. If the ratio of W3 / W4 is too large, the contact resistance between the source / drain contact 218b and the source / drain features thereunder (e.g., source / drain features 214c and 214d) may be too large, thereby affecting the overall performance of the semiconductor structure, or the second portion 260a-2 of the trench 260a may be too close to the adjacent metal gate structures 210a-1 and 210a-2, so that an electrical short between the metal gate structures 210a-1 and 210a-2 and the source / drain contact 218a may persist. In some embodiments, the depth D4 is equal to or greater than the depth D3. In one embodiment, the ratio of the depth D3 to the depth D4 is in the range of about 0.5 to about 1.

[0133] In some embodiments, trench 260c is spaced apart from gate isolation structure 222. Trench 260c exposes source / drain features 214e and 214f. Trench 260c has a shape having a substantially uniform width W2 along its length from a top view and a depth D2 along the Z direction. Width W2 is substantially equal to width W1. Depth D2 is substantially equal to depth D1.

[0134] Reference Figure 1 and FIG. 6A to FIG. 6D The method 100 includes block 110 , in which source / drain contacts 218 a , 218 b , and 218 c are formed in the trenches 260 a , 260 b , and 260 c , respectively. Fig. 6A A partial top view of the workpiece 200 is depicted, and Figure 6B and Figure 6C They are shown along Fig. 6A The partial cross-sectional view of the workpiece 200 taken along the line segment BB' and the line segment CC' shown in FIG. Fig.6D An enlarged top view of source / drain contacts 218a and 218b is shown.

[0135] Prior to forming the source / drain contacts 218a-218c, a silicide layer (not shown) may be formed over each of the source / drain features 214a-214f. In some embodiments, the silicide layer includes a metal silicide, such as nickel silicide, cobalt silicide, tungsten silicide, tantalum silicide, titanium silicide, platinum silicide, erbium silicide, palladium silicide, other suitable silicides, or combinations thereof. The silicide layer may be formed by a deposition process, such as CVD, ALD, PVD, other suitable processes, or combinations thereof. For example, a metal layer (e.g., nickel) may be deposited over the source / drain features 214a-214f. Next, the workpiece 200 is annealed to react the metal layer with the semiconductor material of the source / drain features 214a-214f. Thereafter, the unreacted metal layer is removed, leaving the silicide layer over the source / drain features 214a-214f. Alternatively, the silicide layer may be formed directly over the source / drain features 214 a - 214 f by any suitable deposition method, such as CVD, ALD, PVD, other suitable methods, or combinations thereof.

[0136] The formation of the source / drain contacts 218a, 218b, and 218c may include depositing a conductive layer (not shown) in the trenches 260a, 260b, and 260c and over portions of the metal gate structures 210a and 210b, the gate spacers 212, and the dielectric structure 228. The conductive layer may include any suitable material, such as W, Co, Ru, Cu, Ta, Ti, Al, Mo, other suitable conductive materials, or combinations thereof. The conductive layer may be deposited by any suitable method, such as CVD, PVD, ALD, electroplating, other suitable methods, or combinations thereof. Afterwards, the method 100 uses a suitable method such as CMP to planarize the top surface of the workpiece 200 to form source / drain contacts 218a, 218b, and 218c above the source / drain features 214 and in the trenches 260a, 260b, and 260c, respectively, so that the top surface of the conductive layer (i.e., the formed source / drain contacts 218a, 218b, and 218c) is substantially coplanar with the top surface of the metal gate structures 210a and 210b. In some embodiments, before depositing the conductive layer, a glue layer (not shown) may be formed over the workpiece 200 to partially fill the trenches 260a-260c. The glue layer may include TiN, TaN, etc.

[0137] The source / drain contacts 218a-218c follow the shape of the trenches 260a-260c, respectively. That is, the dimensions (e.g., width, depth) of the source / drain contacts 218a, 218b, and 218c are substantially the same as the trenches 260a, 260b, and 260c, respectively. For example, the first portions 218a-1 and 218b-1 of the source / drain contacts 218a and 218b have a depth D1, the second portion 218a-2 of the source / drain contact 218a has a depth D3, and the second portion 218b-2 of the source / drain contact 218b has a depth D4. In some embodiments, first portions 218a-1 and 218b-1 of source / drain contacts 218a and 218b have width W1, second portion 218a-2 of source / drain contact 218a has width W3, and second portion 218b-2 of source / drain contact 218b has width W4. Source / drain contact 218c has substantially the same width (i.e., depth W2) and substantially the same depth (i.e., depth D2).

[0138] In addition, the source / drain contact 218a includes two first portions 218a-1 located directly above the source / drain features 214a and 214b and electrically coupled to the source / drain features 214a and 214b, respectively, and a second portion 218a-2 extending between the two first portions 218a-1. In some embodiments, from a top view, the second portion 218a-2 of the source / drain contact 218a includes two edges 220a (e.g., Fig.6D See Figure 6C , the second portion 218 a - 2 does not overlap with the metal gate structure 210 a projected on the cross-sectional view along the line segment CC′. In some embodiments, the second portion 218 a - 2 is embedded in the gate isolation structure 222 .

[0139] The source / drain contact 218b includes two first portions 218b-1 located directly above and electrically coupled to the source / drain features 214c and 214d, respectively, and a second portion 218b-2 extending between the two first portions 218b-1. Fig.6D In the illustrated embodiment, the second portion 218b-2 of the source / drain contact 218b includes a first edge 220b-1 that is bent inwardly. The second edge 220b-2 of the second portion 218b-2 of the source / drain contact 218b, which is opposite to the first edge 220b-1, is aligned with the edge 220b-3 of the first portion 218b-1 of the source / drain contact 218b along the Y direction. In other words, from a top view, the first portion 218b-1 and the second portion 218b-2 of the source / drain contact 218b share a continuous edge extending along the Y direction, and the continuous edge is substantially straight. In other words, there is no significant offset between the second edge 220b-2 and the edge 220b-3 along the Y direction. A distance between a first edge 220b-1 of the second portion 218b-2 of the source / drain contact 218b and the metal gate structure 210a is smaller than a distance between a second edge 220b-2 of the second portion 218b-2 of the source / drain contact 218b and the metal gate structure 210a.

[0140] In some embodiments, reference Figure 6C, the boundary 223 of the gate isolation structure 222 is located directly below the second portion 218b-2 of the source / drain contact 218b. The bottom surface of the second portion 218b-2 is in direct contact with both the gate isolation structure 222 and the dielectric structure 228. In one embodiment, a portion of the dielectric structure 228 is sandwiched between the second portion 218b-2 and the gate spacer 212. In some embodiments, the second portion 218b-2 is in direct contact with the sidewall of the gate isolation structure 222. In some embodiments, the source / drain contact 218b does not overlap with the metal gate structure 210a projected on the cross-sectional view along the line segment CC'. The area 219 surrounded by the dotted line surrounding the second portion 218b-2 represents the area in which the source / drain contact 218b can be formed even if there are etching variations, overlay shifts, etc. during the formation of the trench 260b. In some embodiments, the etching rate of the gate spacer 212 is lower than the etching rate of the gate isolation structure 222. Therefore, during the formation of the trench 260b, the gate isolation structure 222 is etched more than the gate spacer 212. Because the second portion 218b-2 has a width (e.g., width W4) that is less than the width of the two first portions 218b-1, the distance from the second portion 218b-2 to the projected metal gate structure 210a is increased. Therefore, even if there are manufacturing variations during the formation of the trench 260b, the possibility of the second portion 218b-2 directly contacting the ends of the metal gate structures 210a-1 / 210a-2 is reduced due to the increase in distance. Therefore, an electrical short circuit between the metal gate structure 210a and the second portion 218b-2 can be avoided. For similar reasons, the distance from the second portion 218a-2 of the source / drain contact 218a to the projected metal gate structure 210a is increased, which also eliminates an electrical short circuit between the metal gate structure 210a and the second portion 218a-2.

[0141] Refer back Figure 1 , method 100 includes block 112, in which further processes are performed to complete the manufacture of workpiece 200. These further processes may include forming a multi-layer interconnect (MLI) structure (not shown) above workpiece 200. In some embodiments, the MLI structure may include multiple intermetal dielectric (IMD) layers and multiple metal lines or contact vias in each IMD layer. In some embodiments, the IMD layer and dielectric structure 228 may share similar components. The metal lines and contact vias in each IMD layer may be formed of a metal, such as aluminum, tungsten, ruthenium, or copper. In some embodiments, the metal lines and contact vias may be lined with a barrier layer to insulate the metal lines and contact vias from the IMD layers.

[0142] In this embodiment, the gate isolation structure 222 is formed later than the metal gate structures 210a and 210b. In some other embodiments, the gate isolation structure 222 may be formed before or after the dummy gate structure is formed. For example, the gate isolation structure 222 may be formed to divide the dummy gate structure into two parts, and the two parts of the dummy gate structure may then be replaced by two metal gate structures (e.g., metal gate structures 210a-1 and 210a-2), respectively.

[0143] Fig. 7A A partial top view of a first alternative workpiece 300 is depicted, and Figure 7B and Figure 7C They are shown along Fig. 7A The partial cross-sectional view of the workpiece 300 is taken along line segment BB′ and line segment CC′. 7A to 7C The workpiece 300 shown in FIG. FIG. 6A to FIG. 6D The workpiece 200 described above. One of the differences between the workpiece 300 and the workpiece 200 includes that in this alternative embodiment, the workpiece 300 includes a dielectric barrier layer 232. More specifically, to prevent diffusion of the conductive layer, after forming the trenches 260a-260c, the dielectric barrier layer 232 is formed over the workpiece 300 and then etched back to cover only the sidewalls of the trenches 260a-260c and expose the source / drain features 214. The source / drain contacts 218a, 218b, and 218c may then be formed in the trenches 260a-260c. That is, the sidewall surfaces of each of the source / drain contacts 218a, 218b, and 218c are continuously lined by the dielectric barrier layer 232. In some embodiments, the dielectric barrier layer 232 may include silicon nitride or other suitable materials.

[0144] Fig. 8A A partial top view of a second alternative workpiece 400 is depicted, and Figure 8B and Figure 8C They are shown along Fig. 8A The partial cross-sectional view of the workpiece 400 is taken along line segment BB′ and line segment CC′. FIG. 8A to FIG. 8C The workpiece 400 shown in FIG. FIG. 6A to FIG. 6DThe workpiece 200 is described. One of the differences between the workpiece 400 and the workpiece 200 includes that in this alternative embodiment, the workpiece 400 includes a self-aligned cap (SAC) layer 252 formed over the metal gate structures 210a and 210b. In an exemplary process, the SAC recess can be formed by removing (e.g., etching) the top portion of the metal gate structures 210a and 210b. Then, a dielectric material (not shown) can be deposited over the workpiece 400 including the SAC recess by CVD, PECVD, or a suitable deposition process. The dielectric material can include silicon oxide, silicon nitride, silicon carbide, silicon carbonitride, silicon oxynitride, silicon carbonitride, aluminum oxide, aluminum nitride, aluminum oxynitride, zirconium oxide, zirconium nitride, zirconium oxide aluminum, hafnium oxide, or a suitable dielectric material. After the dielectric material is deposited, a planarization process such as CMP may be performed to remove excess dielectric material above the dielectric structure 228, thereby forming a SAC layer 252 directly above the metal gate structures 210a and 210b. After the SAC layer 252 is formed, a photolithography process and an etching process are then performed to form a gate isolation trench 256. In the present embodiment, due to the recess of the metal gate structures 210a and 210b, the top surface of the source / drain contacts 218a / 218b / 218c is higher than the top surface of the recessed metal gate structures 210a and 210b. In some embodiments, the top surfaces of the source / drain contacts 218a, 218b, and 218c are coplanar with the top surface of the SAC layer 252.

[0145] In the depicted embodiment, the sidewalls of the SAC layer 252 are in direct contact with at least one gate spacer 212, and the bottom surface of the SAC layer 252 is in direct contact with the top surfaces of the high-k dielectric layer and the metal gate electrode of the metal gate structures 210a and 210b. In some other embodiments, the SAC layer 252 may have other configurations. For example, the SAC layer groove may be formed by digging into the top portion of the metal gate structures 210a and 210b and digging into the top portion of the gate spacer 212, and the resulting SAC layer 252 may be formed directly on the dug gate spacer 212 and the metal gate structures 210a and 210b. The top surface of the dug gate spacer 212 may be higher than the top surface of the metal gate structures 210a and 210b.

[0146] Fig.9A A partial top view of a third alternative workpiece 500 is depicted, and Fig. 9B Shows along Fig. 8A The partial cross-sectional view of the workpiece 500 is taken along line segment BB′. FIG. 9A to FIG. 9B The workpiece 500 shown in FIG. FIG. 6A to FIG. 6DOne of the differences between workpiece 500 and workpiece 200 includes that in this alternative embodiment, the configuration of the source / drain contacts of workpiece 500 is different from the configuration of the source / drain contacts of workpiece 200.

[0147] In some embodiments, the workpiece 500 includes one or more dielectric structures 236 and 240 formed above the metal gate structures 210a and 210b, and the source / drain contacts 218a, 218b, and 218c extend upwardly above the top surfaces of the metal gate structures 210a and 210b and extend through the dielectric structure 236. The workpiece 500 may further include one or more contact vias 250 and a gate contact via 244, wherein the contact vias 250 are embedded in the dielectric structure 240, located above the source / drain contacts 218a, 218b, and / or 218c and electrically coupled to the source / drain contacts 218a, 218b, and / or 218c, and the gate contact via 244 is located above the metal gate structure 210b and electrically coupled to the metal gate structure 210b. In some embodiments, a cross-sectional view of the workpiece 500 along line segment CC' may be similar to FIG. Figure 6C The workpiece 200 shown in FIG. 1 differs in that one or more dielectric structures 236 and 240 are disposed above the gate isolation structure 222 , the dielectric structure 228 , and the metal gate structures 210 a and 210 b , and the source / drain contacts 218 a , 218 b , and 218 c extend upwardly into / through the dielectric structure 236 .

[0148] In an exemplary process, dielectric structure 236 is formed over dielectric structure 228. Photolithography and etching processes are performed on workpiece 500 to form trenches 260a-260b through dielectric structure 236, dielectric structure 228, and gate isolation structure 222, so that the upper surfaces of the corresponding source / drain features 214 thereunder are exposed. In subsequent processes, source / drain contacts 218a, 218b, and 218c are formed in trenches 260a-260b, similar to FIG. 6A to FIG. 6D Further processes may include forming a dielectric structure 240 over the dielectric structure 236 , forming a contact via 250 in the dielectric structure 240 , and forming a gate contact via 244 .

[0149] Fig.10 A partial cross-sectional view of a fourth alternative working member 600 is depicted. A partial top view of a fourth alternative working member 600 is similar to Fig. 6A , the workpiece 600 is moved along Fig. 6A The partial cross-sectional view taken along the line segment BB' shown is similar to Figure 6B . Fig.10The workpiece 600 is shown along Fig. 6A The partial cross-sectional view taken along the line segment CC' shown. FIG. 6A to FIG. 6D In the aforementioned embodiment, in order to form the gate isolation trench 256, the gate spacer 212 and the portion of the metal gate structure 210a exposed by the gate isolation trench 256 are substantially removed. Fig.10 In the fourth alternative embodiment shown, when forming the gate isolation trench 256, a selective etching process is performed to selectively remove the portion of the metal gate structure 210a exposed by the gate isolation trench 256, and the exposed portion of the gate spacer 212 is slightly etched, so that after the selective etching, a portion of the gate spacer 212 (also referred to as the remaining gate spacer 212a) and a portion of the dielectric structure 228 (also referred to as the remaining dielectric structure 228a) are exposed by the gate isolation trench 256. In some embodiments, the sidewalls of the remaining gate spacer 212a are substantially not etched. Any suitable method, such as wet etching, dry etching, or a combination thereof, can be used in the selective etching process, and a suitable etchant can be used to etch various materials.

[0150] In the present embodiment, the gate isolation structure 222 formed in the gate isolation trench 256 includes a first portion 222-1 located directly above the remaining gate spacer 212a, and a second portion 222-2 located between two adjacent remaining gate spacers 212a. In some embodiments, the first portion 222-1 of the gate isolation structure 222 is also located directly above the remaining dielectric structure 228a. In some embodiments, the second portion 222-2 of the gate isolation structure 222 extends into the isolation feature 208 and has a depth D7. The first portion 222-1 of the gate isolation structure 222 has a depth D8. The depth D7 may be greater than the depth D9 of the metal gate structures 210a and 210b. In some embodiments, the ratio of the depth D7 to the depth D9 is in the range of about 1.05 to about 3. If this ratio is too small, the gate isolation structure 222 may not be able to completely divide the metal gate structure 210a into two isolated portions. If this ratio is too large, the gate isolation structure 222 may extend through the isolation feature 208 and into the substrate 202, resulting in an increase in leakage current. The depth D7 may be greater than the depth D8. In some embodiments, the ratio of the depth D7 to the depth D8 is in the range of about 1.05 to about 5.

[0151] Still refer to Fig.10, an upper portion of the second portion 218b-2 of the source / drain contact 218b is separated from the second portion 222-2 of the gate isolation structure 222 by the first portion 222-1 of the gate isolation structure 222, and a lower portion of the second portion 218b-2 of the source / drain contact 218b is separated from the second portion 222-2 of the gate isolation structure 222 by the remaining dielectric structure 228a and the remaining gate spacer 212a. In the depicted embodiment, a bottom surface of the second portion 218b-2 of the source / drain contact 218b is lower than a top surface of an adjacent remaining gate spacer 212a. In some other embodiments, a bottom surface of the second portion 218b-2 of the source / drain contact 218b is coplanar with a top surface of an adjacent remaining gate spacer 212a, or is higher than a top surface of an adjacent remaining gate spacer 212a. In some embodiments, the second portion 218a-2 of the source / drain contact 218a is located directly above the remaining dielectric structure 228a. The bottom surface of the second portion 218a-2 of the source / drain contact 218a can be above, below, or at the same height as the top surface of the adjacent remaining gate spacer 212a.

[0152] Similar to reference photo Figure 6C In the described embodiment, the area 219 around the second portion 218b-2 of the source / drain contact 218b represents an area in which the source / drain contact 218b may be formed even if there are etching variations, overlay shifts, etc. during the formation of the trench 260b. For reasons similar to those described above, the possibility of the second portion 218b-2 directly contacting the end of the metal gate structure 210a is reduced. In addition, in some embodiments, because the etching rate of the remaining gate spacer 212a is lower than the etching rate of the gate isolation structure 222 when forming the trench 260b, the adjacent remaining gate spacer 212a provides more burden to prevent the second portion 218b-2 from directly contacting the end of the metal gate structure 210a. Therefore, electrical shorting between the metal gate structure 210a and the second portion 218b-2 of the source / drain contact 218b can be avoided. For similar reasons, the electrical short between the metal gate structure 210a and the second portion 218a-2 of the source / drain contact 218a is also eliminated.

[0153] Fig.11A A partial top view of a fifth alternative workpiece 700 is depicted. Fig. 11B Shows along Fig.11A The partial cross-sectional view of the workpiece 700 taken along the line segment CC' is shown. Fig. 11C An enlarged top view of source / drain contacts 218d and 218e is shown. Fig.11AThe partial cross-sectional view taken along the line segment BB' shown is similar to Figure 6B , which is omitted for simplicity of description. The workpiece 700 is similar to the workpiece 700 of FIG. FIG. 6A to FIG. 6C The workpiece 200, and one of the differences between the workpiece 700 and the workpiece 200, includes that the gate isolation structure of the workpiece 700 has a different configuration from that of the workpiece 200. More specifically, the workpiece 700 includes a first gate isolation structure 222L configured to cut the metal gate structure 210a into two parts (i.e., a first part 210a-1 and a second part 210a-2, also referred to as metal gate structures 210a-1 and 210a-2, and collectively referred to as metal gate structures 210a), and a second gate isolation structure 222R configured to cut the metal gate structure 210b into two parts 210b-1 and 210b-2 (also referred to as metal gate structures 210b-1 and 210b-2, and collectively referred to as metal gate structures 210b). The formation of the first gate isolation structure 222L and the second gate isolation structure 222R is similar to the formation of the gate isolation structure 222, except that the width spanned by each of the two gate isolation trenches (not shown) is smaller than the width spanned by the trench 256, and each of the two gate isolation trenches does not divide the gate spacer into physically isolated segments. In other words, the edge of each of the two gate isolation trenches is also limited by the two partially etched gate spacers 212. In this way, FIG. 11A to FIG. 11C As shown, the portion of the gate spacer 212 disposed directly above the isolation feature 208 and in direct contact with the first gate isolation structure 222L and the second gate isolation structure 222R (also referred to as the remaining gate spacer 212b) has a width along the X direction that is smaller than the width along the X direction of the portion of the gate spacer 212 directly disposed on the sidewall surface of the metal gate structures 210a and 210b, and the remaining gate spacer 212b is in direct contact with the first gate isolation structure 222L or the second gate isolation structure 222R. The remaining gate spacer 212b has the same height as the portion of the gate spacer 212 directly disposed on the sidewall surface of the metal gate structures 210a and 210b.

[0154] Similar to FIG. 6A to FIG. 6D The source / drain contact 218a of FIG. 11A to FIG. 11C , the source / drain contact 218d has two first portions 218d-1 located directly above the source / drain features 214a and 214b, and a second portion 218d-2 extending between the two first portions 218d-1. The second portion 218d-2 is between and adjacent to the first gate isolation structure 222L and the second gate isolation structure 222R. Fig. 11BIn the illustrated embodiment, the second portion 218d-2 is embedded in the dielectric structure 228, wherein the dielectric structure 228 is located between two adjacent remaining gate spacers 212b. More specifically, the second portion 218d-2 is separated from the first gate isolation structure 222L and the second gate isolation structure 222R by the remaining gate spacers 212b and the dielectric structure 228.

[0155] Similar to FIG. 6A to FIG. 6D The source / drain contact 218e has two first portions 218e-1 located directly above the source / drain features 214c and 214d, and a second portion 218e-2 extending between the two first portions 218e-1. The second portion 218e-2 is adjacent to the second gate isolation structure 222R on one side. In some embodiments, the second portion 218e-2 is embedded in a dielectric structure 228, which is between an adjacent remaining gate spacer 212b and an adjacent gate spacer 212. In some embodiments, the second portion 218e-2 is separated from the second gate isolation structure 222R by the remaining gate spacer 212b and the dielectric structure 228. In some embodiments, the source / drain contact 218e is in direct contact with the adjacent gate spacer 212.

[0156] Similar to reference Figure 6C In the embodiment described, area 219 (shown in Fig. 11B ) represents an area in which the source / drain contact 218e can be formed even if there are etching variations, overlay shifts, etc. during the formation of the trench 260e (a trench for forming the source / drain contact 218e, not shown). In some embodiments, the etching rate of etching the gate spacer 212 is lower than the etching rate of etching the dielectric structure 228. Therefore, during the formation of the trench 260e, the dielectric structure 228 is etched more than the gate spacer 212. For reasons similar to those described above, the possibility of the second portion 218e-2 directly contacting the end of the metal gate structure 210b is reduced. In addition, in some embodiments, because the etching rate of etching the remaining gate spacer 212b is lower than the etching rate of etching the second gate isolation structure 222R when forming the trench 260e, the adjacent remaining gate spacer 212b provides more burden to prevent the second portion 218e-2 from directly contacting the end of the metal gate structure 210b. Therefore, electrical shorting between the metal gate structure 210b and the second portion 218e-2 of the source / drain contact 218e is avoided. For similar reasons, electrical shorting between the metal gate structures 210a and 210b and the second portion 218d-2 of the source / drain contact 218d is also eliminated.

[0157] The source / drain contacts 218d and 218e have shapes similar to the source / drain contacts 218a and 218b, respectively. In some embodiments, the second portion 218d-2 of the source / drain contact 218d has a width W5 along the X direction and a depth D5 along the Z direction. In some embodiments, the width W5 is less than the width W1. In some embodiments, the ratio of the width W5 to the width W1 (i.e., W5 / W1) is in the range of about 0.5 to about 0.95. If W5 / W1 is too small, the contact resistance between the source / drain contact 218d and the source / drain features thereunder (e.g., source / drain features 214a and 214b) may be too large. If W5 / W1 is too large, the second portion 260d-2 may be too close to the adjacent metal gate structures 210a and 210b, so that an electrical short between the metal gate structures 210a and 210b and the source / drain contact 218d may persist. In some embodiments, depth D5 is less than depth D1. In some embodiments, a ratio of depth D5 to depth D1 is in a range of about 0.3 to about 0.95.

[0158] In some embodiments, the second portion 218e-2 of the source / drain contact 218e has a width W6 along the X direction and a depth D6 along the Z direction. In some embodiments, the width W6 is less than the width W1. In some embodiments, the ratio of the width W6 to the width W1 (i.e., W6 / W1) is in the range of about 0.5 to about 0.95, or in the range of about 0.7 to about 0.95. If W6 / W1 is too small, the contact resistance between the source / drain contact 218e and the source / drain features thereunder (e.g., source / drain features 214c and 214d) may be too large. If W6 / W1 is too large, the second portion 260e-2 may be too close to the adjacent metal gate structure 210b, so that an electrical short between the metal gate structure 210b and the source / drain contact 218e may persist. In some embodiments, the depth D6 is less than the depth D1. In one embodiment, the ratio of the depth D6 to the depth D1 is in the range of about 0.5 to about 0.95.

[0159] In some embodiments, the width W6 is equal to or greater than the width W5. In some embodiments, the ratio of the width W5 to the width W6 (i.e., W5 / W6) is in a range of about 0.7 to about 1. If W5 / W6 is too small, the contact resistance between the source / drain contact 218d and the source / drain features thereunder (e.g., the source / drain features 214a and 214b) may be too large, thereby affecting the overall performance of the semiconductor structure, or the second portion 218e-2 may be too close to the adjacent metal gate structure 210b, so that an electrical short between the metal gate structure 210b and the source / drain contact 218e may persist. If W5 / W6 is too large, the contact resistance between the source / drain contact 218e and the source / drain features thereunder (e.g., source / drain features 214c and 214d) may be too large, thereby affecting the overall performance of the semiconductor structure, or the second portion 218d-2 may be too close to the adjacent metal gate structures 210a and 210b, so that an electrical short between the metal gate structures 210a and 210b and the source / drain contact 218d may persist. In some embodiments, the depth D6 is equal to or greater than the depth D5. In one embodiment, the ratio of the depth D5 to the depth D6 is in the range of about 0.5 to about 1.

[0160] Fig. 12A A partial top view of a sixth alternative workpiece 800 is depicted. Fig. 12B Shows along Fig. 12A The partial cross-sectional view of the workpiece 800 is taken along the line segment CC' shown in FIG. Fig. 12A The partial cross-sectional view taken along the line segment BB' shown is similar to Figure 8B One difference between workpiece 800 and workpiece 700 includes that in this alternative embodiment, workpiece 800 includes a SAC layer 252' formed over metal gate structures 210a and 210b. SAC layer 252' may have FIG. 8A to FIG. 8C In some embodiments, the top surfaces of the source / drain contacts 218 d , 218 e , and 218 c are higher than the top surface of the metal gate structure 210 .

[0161] In reference 6A to 12A In the aforementioned embodiments, the source / drain contacts are configured to have non-uniform widths along their lengths, and exemplary top views of the source / drain contacts are shown. In some alternative embodiments, the source / drain contacts (e.g., source / drain contacts 218a and 218b) have different shapes when viewed from a top view. Fig.13A A partial top view of a seventh alternative work piece 900 is depicted. Fig. 13BAn enlarged top view of source / drain contacts 218a and 218b is shown. One of the differences between work piece 900 and work piece 200 includes that in this alternative embodiment, both edges 220a-1 of second portion 218a-2 of source / drain contact 218a and first edge 220b-1 of second portion 218b-2 of source / drain contact 218b are substantially straight from the top view and recessed from edges 220a-3 and 220b-4 of first portion 218a-1 and 218b-1, respectively. In other words, from the top view, the profile of source / drain contact 218a resembles a dumbbell. The dimensions (e.g., width, depth) of source / drain contacts 218a and 218b may be the same as previously described.

[0162] Various combinations of embodiments of semiconductor structures and methods of manufacturing the same are within the scope of the present disclosure. For example, the workpiece may include a SAC layer 252 and a dielectric barrier layer 232. In other examples, the source / drain contacts 218a, 218b, 218c, 218d, and / or 218e extend above the top surface of the metal gate structures 210a and 210b and have FIG. 13A to FIG. 13B The source / drain contacts 218a, 218b, 218c, 218d, and / or 218e may be provided in any number and at any position relative to each other.

[0163] Although not intended to be limiting, one or more embodiments of the present disclosure provide numerous benefits to semiconductor structures and methods of forming the same. For example, one advantage is that the present disclosure reduces / avoids electrical shorts between source / drain contacts and adjacent metal gate structures without sacrificing relatively low contact resistance between the source / drain contacts and the source / drain features thereunder. The present disclosure is compatible with a variety of semiconductor manufacturing processes and with a variety of semiconductor structures (e.g., semiconductor structures having SAC layers and / or dielectric barrier layers). The semiconductor structure may include a planar transistor or a multi-gate device, such as a FinFET, GAA, nanosheet, fork sheet, or CFET.

[0164] The present disclosure provides many different embodiments. Semiconductor structures and methods for manufacturing the same are disclosed herein. In an exemplary manner, the present disclosure is directed to a semiconductor structure. The semiconductor structure includes a source / drain feature located above a substrate, a metal gate structure extending longitudinally along a first direction and adjacent to the source / drain feature, and a gate isolation structure extending longitudinally along a second direction substantially perpendicular to the first direction. The gate isolation structure divides the metal gate structure into two isolated parts. The semiconductor structure also includes a source / drain contact, which is electrically coupled to the source / drain feature and includes a first portion located directly above the source / drain feature, and a second portion extending from the first portion along the first direction. The first portion has a first width along the second direction, and the second portion has a second width along the second direction. The first width is greater than the second width.

[0165] In some embodiments, the second portion of the source / drain contact includes two edges that are bent inward in a top view. In some embodiments, in a cross-sectional view, a boundary of the gate isolation structure is located directly below the second portion of the source / drain contact.

[0166] In some embodiments, a first portion of the source / drain contact has a first depth and a second portion of the source / drain contact has a second depth that is less than the first depth.

[0167] In some embodiments, the semiconductor structure further comprises an isolation feature located above the substrate and below the gate isolation structure, and a plurality of gate spacers extending longitudinally along the first direction. The plurality of gate spacers comprises a first portion located on a plurality of sidewalls of the metal gate structure, and a second portion disposed directly above the isolation feature. The second portion of the plurality of gate spacers is located directly below the first portion of the gate isolation structure.

[0168] In some embodiments, the gate isolation structure further includes a second portion adjacent to the second portions of the plurality of gate spacers. The second portion of the gate isolation structure extends into the isolation feature and has a bottom surface lower than a bottom surface of the first portion of the gate isolation structure.

[0169] In some embodiments, the top surface of the source / drain contacts is higher than the top surface of the metal gate structure.

[0170] In some embodiments, the source / drain feature is a first source / drain feature and the source / drain contact is a first source / drain contact. The semiconductor structure further includes a second source / drain feature, such that the metal gate structure is disposed between the first source / drain feature and the second source / drain feature. In some embodiments, the semiconductor structure further includes a second source / drain contact electrically coupled to the second source / drain feature and having a third portion directly above the second source / drain feature, and a fourth portion extending from the third portion along the first direction. The third portion has a third width, and the fourth portion has a fourth width less than the third width.

[0171] In some embodiments, the fourth portion of the second source / drain contact includes a first edge that is bent inward in a top view, and a second edge opposite the first edge and aligned with the edge of the third portion.

[0172] In some embodiments, the fourth portion of the second source / drain contact has a depth that is less than a depth of the third portion of the second source / drain contact and greater than a depth of the second portion of the first source / drain contact.

[0173] In another exemplary embodiment, the present disclosure is directed to a semiconductor structure. The semiconductor structure includes a first source / drain feature and a second source / drain feature located above a substrate, a first metal gate structure and a second metal gate structure extending longitudinally above the substrate along a first direction and adjacent to the first source / drain feature and the second source / drain feature, respectively, and a gate isolation structure extending longitudinally along a second direction substantially perpendicular to the first direction. The first metal gate structure and the second metal gate structure are isolated by the gate isolation structure. The semiconductor structure also includes a source / drain contact, the source / drain contact including two first portions located directly above the first source / drain feature and the second source / drain feature, and a second portion connecting the two first portions. The second portion is adjacent to the gate isolation structure, and the two first portions and the second portion have different widths.

[0174] In some embodiments, a second portion of the source / drain contact is embedded in the gate isolation structure.

[0175] In some embodiments, a second portion of the source / drain contact is directly above a portion of the gate isolation structure and directly contacts a sidewall of the gate isolation structure.

[0176] In some embodiments, the semiconductor structure further includes an isolation feature disposed between the first source / drain feature and the second source / drain feature, and a plurality of gate spacers. The plurality of gate spacers have a first portion located on a plurality of sidewalls of the first metal gate structure and the second metal gate structure, and a second portion disposed directly above the isolation feature. The second portion of the source / drain contact is separated from the gate isolation structure by the second portion of the plurality of gate spacers.

[0177] In some embodiments, the semiconductor structure further comprises a dielectric layer adjacent to the gate spacer, wherein the source / drain contacts are embedded in the dielectric layer. In some embodiments, in a top view, the profile of the source / drain features is approximately dumbbell-shaped.

[0178] In yet another exemplary embodiment, the present disclosure is directed to a semiconductor structure. The semiconductor structure includes a substrate, and a first active region and a second active region located above the substrate and parallel to each other. The first active region includes a first source / drain feature, and the second active region includes a second source / drain feature. The semiconductor structure also includes a metal gate structure, which extends longitudinally along a first direction, is located above the first active region and the second active region, and is adjacent to the first source / drain feature and the second source / drain feature. The semiconductor structure also includes a source / drain contact, and the source / drain contact includes two first portions located directly above the first source / drain feature and the second source / drain feature, respectively, and a second portion extending between the two first portions. The two first portions have a first width along a second direction substantially perpendicular to the first direction, and the second portion has a second width along the second direction. The first width is greater than the second width.

[0179] In some embodiments, the semiconductor structure further includes a plurality of gate spacers located on a plurality of sidewalls of the metal gate structure, and a gate isolation structure extending longitudinally along the second direction and between the first active region and the second active region. The gate isolation structure divides the metal gate structure into two isolated parts and includes a dielectric material different from the gate spacers.

[0180] In some embodiments, the gate isolation structure includes an outer layer and an inner layer embedded in the outer layer.

[0181] In some embodiments, the semiconductor structure further includes a first gate isolation structure and a second gate isolation structure extending longitudinally along the second direction and between the first active region and the second active region. The first gate isolation structure divides the metal gate structure into two isolated parts, and the second part of the source / drain contact is between the first gate isolation structure and the second gate isolation structure.

[0182] The foregoing text summarizes the features of multiple embodiments so that those skilled in the art can better understand the methods of the present disclosure. Those skilled in the art should understand that they can easily design or modify other processes and structures based on the present disclosure to achieve the same purpose and / or achieve the same advantages as the embodiments or examples described herein. Those skilled in the art should also understand that these equivalent structures do not depart from the spirit and scope of the present disclosure, and various changes, substitutions and modifications can be made to the present disclosure without departing from the spirit and scope of the present disclosure.

Claims

1. A semiconductor structure, characterized in that: include: a source / drain feature located above a substrate; a metal gate structure extending longitudinally along a first direction and adjacent to the source / drain features; a gate isolation structure extending longitudinally along a second direction substantially perpendicular to the first direction, wherein the gate isolation structure divides the metal gate structure into two isolated parts; as well as a source / drain contact electrically coupled to the source / drain feature and comprising a first portion directly above the source / drain feature and a second portion extending from the first portion along the first direction; The first portion has a first width along the second direction, and the second portion has a second width along the second direction, and the first width is greater than the second width.

2. The semiconductor structure according to claim 1, wherein: The second portion of the source / drain contact includes two edges that are bent inwardly in a top view.

3. The semiconductor structure according to claim 1, wherein: In a cross-sectional view, a boundary of the gate isolation structure is located directly below the second portion of the source / drain contact.

4. The semiconductor structure according to claim 1, wherein: Also includes: an isolation feature located above the substrate and below the gate isolation structure; as well as A plurality of gate spacers extend longitudinally along the first direction and include a first portion located on a plurality of sidewalls of the metal gate structure and a second portion disposed directly above the isolation feature, wherein the second portion of the gate spacer is located directly below a first portion of the gate isolation structure.

5. The semiconductor structure according to claim 1, wherein: The source / drain feature is a first source / drain feature and the source / drain contact is a first source / drain contact, wherein the semiconductor structure further comprises: a second source / drain feature, such that the metal gate structure is disposed between the first source / drain feature and the second source / drain feature; and a second source / drain contact electrically coupled to the second source / drain feature and having a third portion located directly above the second source / drain feature and a fourth portion extending from the third portion along the first direction; The third portion has a third width, and the fourth portion has a fourth width that is smaller than the third width.

6. A semiconductor structure, characterized in that: include: a first source / drain feature and a second source / drain feature located above a substrate; A first metal gate structure and a second metal gate structure extend longitudinally above the substrate along a first direction and are adjacent to the first source / drain feature and the second source / drain feature, respectively; a gate isolation structure extending longitudinally along a second direction substantially perpendicular to the first direction, wherein the first metal gate structure and the second metal gate structure are isolated by the gate isolation structure; as well as a source / drain contact, comprising two first portions located directly above the first source / drain feature and the second source / drain feature, and a second portion connecting the two first portions; wherein the second portion is adjacent to the gate isolation structure; and The two first parts and the second part have different widths.

7. The semiconductor structure according to claim 6, wherein: The second portion of the source / drain contact is located directly above a portion of the gate isolation structure and directly contacts a side wall of the gate isolation structure.

8. The semiconductor structure according to claim 6, wherein: Also includes: an isolation feature disposed between the first source / drain feature and the second source / drain feature; as well as A plurality of gate spacers have a first portion located on a plurality of sidewalls of the first metal gate structure and the second metal gate structure, and a second portion disposed directly above the isolation feature, wherein the second portion of the source / drain contact is separated from the gate isolation structure by the second portion of the gate spacer.

9. A semiconductor structure, characterized in that: include: a substrate; A first active region and a second active region are located above the substrate and are parallel to each other, wherein the first active region includes a first source / drain feature, and the second active region includes a second source / drain feature; a metal gate structure extending longitudinally along a first direction, located above the first active region and the second active region, and adjacent to the first source / drain feature and the second source / drain feature; as well as a source / drain contact, comprising two first portions located directly above the first source / drain feature and the second source / drain feature, respectively, and a second portion extending between the two first portions; The two first portions have a first width along a second direction substantially perpendicular to the first direction, and the second portion has a second width along the second direction, and the first width is greater than the second width.

10. The semiconductor structure according to claim 9, wherein: The device further comprises a first gate isolation structure and a second gate isolation structure, wherein the first gate isolation structure and the second gate isolation structure extend longitudinally along the second direction and are located between the first active region and the second active region. The first gate isolation structure divides the metal gate structure into two isolated parts, and The second portion of the source / drain contact is located between the first gate isolation structure and the second gate isolation structure.

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