Control circuit and control system
By combining the enable signal and reset signal in the control circuit, it determines whether the watchdog module performs reset operations, solving the problem of improper reset operations in the dead cycle and development and debugging in the prior art, and achieving more flexible and reliable system management.
Patent Information
- Application Number
- CN202421297204.1
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-06-06
- Publication Date
- 2025-04-08
- Estimated Expiration
- 2034-06-06
AI Technical Summary
The existing watchdog chip only decides whether to perform reset operations based on whether the system is working normally, resulting in problems such as dead loops or failure to perform normally in development and debugging in some applications.
A control circuit is designed, including a control module, a watchdog module and a switch module, and by combining the enable signal and the reset signal, an execution signal is generated to determine whether to perform a reset operation.
It realizes that whether the control module performs reset operations is not only determined based on its working conditions, but also based on the enable signal, thereby avoiding dead cycles and ensuring the normal progress of development and debugging.
Smart Images
Figure CN222734475U_ABST
Abstract
Description
Technical Field
[0001] The present application relates to the technical field of electronic circuits, and more specifically, to a control circuit and a control system. Background Art
[0002] The watchdog chips currently on the market only determine whether the system performs a reset operation based on whether the system can work normally, resulting in corresponding restrictions in some applications. For example, when the system is powered on for too long and the watchdog cannot be fed in time, the system performs a reset operation, which makes the system easily enter an infinite loop. For another example, during the software development and debugging stage, failure to feed the watchdog in time causes the system to reset, so that the software development and debugging work cannot be implemented normally. Therefore, the system only performs a reset operation based on whether it can work normally, which causes corresponding inconveniences in the corresponding applications of the system. Utility Model Content
[0003] In view of the above problems, the present application proposes a control circuit and a control system, which can determine whether the system performs a reset operation not only based on whether the system can work normally, so as to avoid causing corresponding restrictions on the corresponding applications of the system.
[0004] In a first aspect, the present application provides a control circuit, which includes: a control module, a watchdog module and a switch module, wherein: a first end of the control module is connected to an input end of the watchdog module, a second end of the control module is connected to a first input end of the switch module, a third end of the control module is connected to an output end of the switch module, and an output end of the watchdog module is connected to a second input end of the switch module; the control module is used to generate an enable signal and send the enable signal to the switch module; the watchdog module is used to generate a reset signal according to a working condition of the control module and send the reset signal to the switch module; the switch module is used to generate an execution signal according to the enable signal and the reset signal and send the execution signal to the control module; the control module is also used to execute corresponding operations according to the execution signal.
[0005] In a second aspect, the present application also provides a control system, which includes: a robot and the above-mentioned control circuit.
[0006] The technical solution provided by the present application, the control circuit includes: a control module, a watchdog module and a switch module, wherein: the first end of the control module is connected to the input end of the watchdog module, the second end of the control module is connected to the first input end of the switch module, the third end of the control module is connected to the output end of the switch module, and the output end of the watchdog module is connected to the second input end of the switch module; the control module is used to generate an enable signal and send the enable signal to the switch module; the watchdog module is used to generate a reset signal according to the working condition of the control module and send the reset signal to the switch module; the switch module is used to generate an execution signal according to the enable signal and the reset signal and send the execution signal to the control module; the control module is also used to execute the corresponding operation according to the execution signal. Thus, the control circuit generates an execution signal according to the working condition of the control module and the enable signal, so as to realize whether the control module performs the reset operation not only based on the working condition of the control module, but also determined according to the enable signal. BRIEF DESCRIPTION OF THE DRAWINGS
[0007] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following is a brief introduction to the drawings required for the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present application, not all embodiments. Based on the embodiments of the present application, all other embodiments and drawings obtained by ordinary technicians in this field without creative work are within the scope of protection of the present utility model.
[0008] Figure 1 It is a structural schematic diagram of a control circuit provided in an embodiment of the present application.
[0009] Figure 2 It is a structural schematic diagram of another control circuit provided in an embodiment of the present application.
[0010] Figure 3 It is a structural schematic diagram of a rectifier unit provided in an embodiment of the present application. DETAILED DESCRIPTION
[0011] In order to make the purpose, technical solutions and advantages of the present application clearer, the present application will be further described in detail below in conjunction with the accompanying drawings. The described embodiments should not be regarded as limiting the present application. All other embodiments obtained by ordinary technicians in the field without making creative work are within the scope of protection of this application.
[0012] In the following description, reference is made to "some embodiments", which describes a subset of all possible embodiments, but it is understood that "some embodiments" may be the same subset or different subsets of all possible embodiments, and may be combined with each other without conflict. In the following description, reference is made to the term "multiple" to mean at least two.
[0013] In the following description, the terms "first\second" involved are merely used to distinguish similar objects and do not represent a specific ordering of the objects. It can be understood that "first\second" can be interchanged with a specific order or sequence where permitted, so that the embodiments of the present application described herein can be implemented in an order other than that illustrated or described herein.
[0014] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application belongs. The terms used herein are only for the purpose of describing the embodiments of this application and are not intended to limit this application.
[0015] Due to the limited number of pins of the watchdog chip (for example, the most commonly used watchdog chip on the market is composed of an external watchdog chip of the SOT-23-5 chip. For example, the chip series of TI TPS38, the chip series of Microchip MCP131X / 2X or the chip series of ST STM632x.), there is no built-in watchdog enable signal, so there are corresponding constraints in some applications. For example, the system is powered on for too long and the dog cannot be fed in time, resulting in a system reset. The system enters the power-on state again, and the system is reset again because the dog cannot be fed in time due to the long power-on period. This repeats and enters an infinite loop. For another example, the system is reset if the dog is not fed in time during the software development and debugging stage, resulting in the inability to proceed normally in the software development and debugging stage. For another example, in application scenarios related to system functional safety, the system diagnostic cycle is required to be at the millisecond level. If the watchdog chip does not have a built-in watchdog enable signal, the system is very easy to reset, thereby affecting the relevant operations of the system. That is to say, the watchdog chips currently on the market only determine whether the system performs a reset operation based on whether the system can work normally, so there are corresponding restrictions in some applications.
[0016] Therefore, the system performs a reset operation only according to whether it can work normally, which causes corresponding inconvenience to the corresponding application of the system.
[0017] In order to improve the above-mentioned problems, the present application provides a control circuit and a control system, wherein the control circuit includes: a control module, a watchdog module and a switch module, wherein: a first end of the control module is connected to an input end of the watchdog module, a second end of the control module is connected to a first input end of the switch module, a third end of the control module is connected to an output end of the switch module, and an output end of the watchdog module is connected to a second input end of the switch module; the control module is used to generate an enable signal and send the enable signal to the switch module; the watchdog module is used to generate a reset signal according to the working condition of the control module and send the reset signal to the switch module; the switch module is used to generate an execution signal according to the enable signal and the reset signal and send the execution signal to the control module; the control module is also used to execute corresponding operations according to the execution signal.
[0018] Therefore, the control circuit generates an execution signal according to the working condition of the control module and the enable signal, so that whether the control module performs the reset operation is determined not only according to the working condition of the control module, but also according to the enable signal.
[0019] The technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application.
[0020] See also Figure 1 , Figure 1 is a schematic diagram of a control circuit provided in an embodiment of the present application. Figure 1 As shown, Figure 1 The control circuit 100 in the embodiment includes a control module 110 , a watchdog module 120 and a switch module 130 .
[0021] Among them, the first end of the control module 110 is connected to the input end of the watchdog module 120, the second end of the control module 110 is connected to the first input end of the switch module 130, the third end of the control module 110 is connected to the output end of the switch module 130, and the output end of the watchdog module 120 is connected to the second input end of the switch module 130.
[0022] The control module 110 is used to generate an enable signal and send the enable signal to the switch module 130; the watchdog module 120 is used to generate a reset signal according to the working condition of the control module 110 and send the reset signal to the switch module 130; the switch module 130 is used to generate an execution signal according to the enable signal and the reset signal and send the execution signal to the control module 110; the control module 110 is also used to execute corresponding operations according to the execution signal.
[0023] In some embodiments, the control module 110 may be a central processing unit (CPU). In some embodiments, the control module 110 may be a processor. In a specific embodiment, the control module 110 may be a chip of model STM32F407.
[0024] In some implementations, the watchdog module 120 may be a watchdog chip. In a specific embodiment, the watchdog module 120 may be a chip of model TPS3820.
[0025] The watchdog module 120 generates a reset signal according to the working condition of the control module 110. For example, when the watchdog module 120 determines that the control module 110 is working normally, the watchdog module 120 generates a shielding signal. For another example, when the watchdog module 120 determines that the control module 110 cannot work normally (for example, the control module 110 enters an infinite loop), the watchdog module 120 generates a reset signal.
[0026] In some implementations, the switch module 130 may be a buffer chip. In a specific embodiment, the switch module 130 may be a chip of model SN74LV1 T126.
[0027] The enable signal generated by the control module 110 is input to the switch module 130 through the first input terminal of the switch module 130, and the reset signal generated by the watchdog module 120 is input to the switch module 130 through the output terminal and the second input terminal of the switch module 130. When the switch module 130 receives the enable signal and the reset signal, the switch module 130 generates an execution signal according to the enable signal and the reset signal, and sends the execution signal to the third terminal of the control module 110 through the output terminal of the switch module 130. The control module 110 then performs a corresponding operation according to the execution signal.
[0028] More specifically, in some embodiments, the enable signal includes a first level and a second level. The levels corresponding to the first level and the second level are different. For example, the first level is a high level. The second level is a low level. In some embodiments, the reset signal includes a first reset signal and a second reset signal. Among them, the levels corresponding to the first reset signal and the second reset signal are different. In some embodiments, the execution signal includes a reset execution signal and a shield execution signal.
[0029] Exemplarily, when the enable signal is at the first level and the reset signal is the first reset signal, the switch module 130 generates a reset execution signal based on the enable signal and the reset signal, and the output end of the switch module 130 sends the reset execution signal to the third end of the control module 110. The control module 110 performs a reset operation according to the reset execution signal, that is, executes an internal reset program.
[0030] Exemplarily, when the enable signal is at the first level and the reset signal is the second reset signal, the switch module 130 generates a shielding execution signal based on the enable signal and the reset signal, and the output end of the switch module 130 sends the shielding execution signal to the third end of the control module 110. The control module 110 does not perform the reset operation according to the shielding execution signal, that is, does not execute the internal reset program.
[0031] Exemplarily, when the enable signal is at the second level and the reset signal is the first reset signal or the second reset signal, the switch module 130 generates a shielding execution signal based on the enable signal and the reset signal, and the output end of the switch module 130 sends the shielding execution signal to the third end of the control module 110. The control module 110 does not perform the reset operation according to the shielding execution signal, that is, does not execute the internal reset program.
[0032] By adjusting the level of the enable signal and the reset signal, the switch module 130 is generated to generate a reset execution signal or a shielding execution signal, so as to control the control module 110 to perform a reset operation or the control module 110 not to perform a reset operation. This avoids the watchdog module 120 causing the control module 110 to perform a reset operation when it is unnecessary, thereby affecting the corresponding use of the circuit.
[0033] Furthermore, the control module 110 is also used to generate a pulse signal and send the pulse signal to the watchdog module 120; the watchdog module 120 is specifically used to generate a first reset signal and send the first reset signal to the switch module 130 when no pulse signal is received; the switch module 130 is specifically used to generate a reset execution signal according to the enable signal and the first reset signal when the enable signal is at a first level; the control module 110 is specifically used to perform a reset operation according to the reset execution signal.
[0034] The first level is a high level. The first reset signal is a high level.
[0035] When the enable signal received by the switch module 130 is a first level and the switch module 130 receives a first reset signal, the switch module 130 is activated, the switch module 130 generates a reset execution signal according to the first level and the first reset signal, and sends the generated reset execution signal to the third end of the control module 110 through the output end, so that the control module 110 performs a reset operation according to the reset execution signal.
[0036] In some embodiments, the watchdog module 120 is specifically configured to generate a first reset signal when no pulse signal is received within a preset time period. When the input end of the watchdog module 120 does not receive a pulse signal, the watchdog module 120 starts timing, and if no pulse signal is received within the preset time period, the watchdog module 120 generates a first reset signal, that is, the output end of the watchdog module 120 generates a high level.
[0037] The watchdog function of the circuit is activated by outputting a high-level first reset signal at the output end of the watchdog module 120 and a high-level enable signal at the second end of the control module 110, so that the output end of the switch module 130 outputs a reset execution signal to control the control module 110 to perform a reset operation according to the reset execution signal, thereby avoiding that when an abnormality occurs in the control module 110, the control module 110 continues to be in an abnormal state due to failure to reset.
[0038] Furthermore, the watchdog module 120 is specifically used to generate a second reset signal when a pulse signal is received, and send the second reset signal to the switch module; the switch module 130 is specifically used to generate a shielding execution signal according to the enable signal and the second reset signal when the enable signal is at a first level; the control module is specifically used to shield the reset operation according to the shielding execution signal.
[0039] The second reset signal is at a low level.
[0040] That is, when the enable signal is at the first level, if the second input terminal of the switch module 130 receives the first reset signal, the switch module 130 generates a reset execution signal according to the first level and the first reset signal to control the control module 110 to perform a reset operation.
[0041] When the enable signal is at the first level, if the second input terminal of the switch module 130 receives the second reset signal, the switch module 130 generates a shielding execution signal according to the first level and the second reset signal to control the control module 110 not to perform the reset operation.
[0042] That is, the watchdog module 120 generates the first reset signal or the second reset signal accordingly according to whether the pulse signal generated by the control module 110 is received.
[0043] The watchdog module 120 and the switch module 130 cooperate with each other so that the control module 110 can be reset in time in an abnormal situation. However, when the control module 110 is too long to output a pulse signal through the first end, the watchdog module 120 will think that the control module 110 is abnormal, and will cooperate with the switch module 130 to reset the control module 110. This situation easily causes the circuit to enter an infinite loop. That is, the control module 110 has not yet been turned on, the watchdog module 120 and the switch module 130 reset the control module 110, the control module 110 restarts, the watchdog module 120 and the switch module 130 reset the control module 110 again, and the control module 110 restarts.
[0044] Moreover, during the circuit development and debugging stage, when the control module 110 does not output a pulse signal through the first end in a timely manner during the testing of the corresponding functions of the circuit, the watchdog module 120 will consider that the control module 110 is abnormal, and will cooperate with the switch module 130 to reset the control module 110, causing the corresponding function testing of the circuit to be unable to proceed normally.
[0045] That is to say, in other corresponding applications of the control circuit 100, the control circuit 100 needs to shield the reset operation to avoid the use of other corresponding applications of the control circuit 100. Based on the above situation, in some embodiments, the switch module 130 is specifically used to generate a shielding execution signal according to the enable signal and the reset signal when the enable signal is at the second level; the control module 1101 is specifically used to shield the reset operation according to the shielding execution signal.
[0046] That is, when the enable signal is at the second level, no matter the output terminal of the watchdog module 120 outputs the first reset signal or the second reset signal, the switch module 130 generates a shielding execution signal according to the second level and the reset signal to control the control module 110 not to perform the reset operation.
[0047] More specifically, see Figure 2 , Figure 2 is a schematic diagram of the structure of another control circuit provided in an embodiment of the present application. Figure 2 As shown, the watchdog module 120 may include a watchdog chip U1 and a first resistor R1.
[0048] Among them, the input end of the watchdog chip U1 is connected to the first end of the control module 110, the power supply end of the watchdog chip U1 is connected to the power supply VCC, the output end of the watchdog chip U1 is respectively connected to the first input end of the switch module 130 and one end of the first resistor R1, and the other end of the first resistor R1 is connected to the power supply VCC.
[0049] In a specific embodiment, the watchdog chip U1 is a chip of model TPS3820. The input end of the watchdog chip U1 (WD I end of the TPS3820 chip) is connected to the first end of the control module 110 (timing IO port of the STM32F407 chip), the power supply end of the watchdog chip U1 (VDD end of the TPS3820 chip) is connected to the power supply VCC, and the output end of the watchdog chip U1 (VDD end of the TPS3820 chip) is connected to the power supply VCC. ) are respectively connected to the first input terminal of the switch module 130 and one end of the first resistor R1, and the other end of the first resistor R1 is connected to the power supply VCC.
[0050] The first resistor R1 is a pull-up resistor to ensure that during the power-on initialization process of the control circuit 100 , the second input end of the switch module 130 receives a signal more reliably, that is, the level of the second input end of the switch module 130 is more reliable.
[0051] For more details, please refer to Figure 2 , the switch module 130 may include a buffer chip U2, a second resistor R2 and a third resistor R3, wherein:
[0052] The first input end of the buffer chip U2 is connected to the second end of the control module 110 and one end of the second resistor R2 respectively, the second input end of the buffer chip U2 is connected to the output end of the watchdog module 120, the third end of the buffer chip U2 is connected to the third end of the control module 110 and one end of the third resistor R3 respectively, the other end of the second resistor R2 is used for grounding, and the other end of the third resistor R3 is connected to the power supply VCC.
[0053] In a specific embodiment, the buffer chip U2 is a chip of model SN74LV1 T126, the first input end of the buffer chip U2 (OE end of the SN74LV1 T126 chip) is respectively connected to the second end of the control module 110 (GPIO end of the STM32F407 chip) and one end of the second resistor R2, and the second input end of the buffer chip U2 (A end of the SN74LV1 T126 chip) is connected to the output end of the watchdog module 120 (the A end of the TPS3820 chip). The third end of the buffer chip U2 (the Y end of the SN74LV1 T126 chip) is connected to the third end of the control module 110 (the The other end of the second resistor R2 is connected to the ground, and the other end of the third resistor R3 is connected to the power supply (VCC).
[0054] Among them, the second resistor R2 is a pull-down resistor, and the third resistor R3 is a pull-up resistor. The second resistor R2 and the third resistor R3 are used to ensure that during the power-on initialization process of the control circuit 100, the signal received by the first input end of the switch module 130 and the signal output by the output end are relatively reliable, that is, the level of the first input end of the switch module 130 and the level of the output end are relatively reliable.
[0055] For further information, please refer to Figure 2 The switch module 130 may further include a filter capacitor C, one end of the filter capacitor C is connected to one end of the second resistor R2, and the other end of the filter capacitor C is grounded. The signal received by the first input end of the switch module 130 is filtered by the filter capacitor C to reduce the influence of interference or noise on the switch module 130 generating the execution signal.
[0056] Therefore, it can be seen that when the watchdog needs to be shielded, it is only necessary to keep the OE terminal of the buffer chip U2 at a low level. At this time, no matter whether the A terminal of the buffer chip U2 receives a high level or a low level, the output terminal of the buffer chip U2 is in a high-impedance state. At this time, the third resistor R3 provides a high voltage to the third terminal of the control module 110, so that the control module 110 does not perform a reset operation.
[0057] For example, in order to ensure that the control circuit 100 can perform software initialization normally after power-on, during the software initialization process after the control circuit 100 is powered on, the second terminal of the control module 110 outputs a second level to make the output terminal of the buffer chip U2 in a high impedance state, and at this time, the third terminal of the control module 110 is made high level by the third resistor R3, so that the control module 110 does not perform a reset operation, so as to ensure that the control module 110 performs the initialization action normally.
[0058] In the case where the control circuit 100 requires a watchdog function, the first end of the control module 110 outputs a square wave signal to the watchdog chip U1, so that the watchdog chip U1 outputs a high level at the output end, and the second end of the control module 110 outputs a first level to activate the watchdog function of the control circuit 100. Thus, in the case where the control module 110 fails and cannot send a pulse signal to the watchdog module 120, the watchdog module 120 generates a reset signal, and then cooperates with the switch module 130 to reset the control module 110 in time.
[0059] After the watchdog function of the control circuit 100 is activated, when the WD I terminal of the watchdog chip U1 does not receive the pulse signal sent from the first terminal of the control module 110, the watchdog chip U1 The Y terminal of the buffer chip U2 outputs a low level, and the control module 110 is reset.
[0060] After the watchdog function of the control circuit 100 is activated, when the WD I terminal of the watchdog chip U1 receives a pulse signal sent from the first terminal of the control module 110, the RESET terminal of the watchdog chip U1 outputs a high level, and the second terminal of the control module 110 outputs a high level. At this time, the Y terminal of the buffer chip U2 outputs a high level, and the control module 110 shields reset.
[0061] See also Figure 3 , Figure 3 It is a structural diagram of a control system provided in an embodiment of the present application, and the control system includes: a robot 210 and the above-mentioned control circuit 100.
[0062] Those skilled in the art can clearly understand that, for the convenience and brevity of description, the specific working process of the control circuit described above can refer to the corresponding process in the aforementioned method embodiment, which will not be repeated here.
[0063] The embodiment of the present application provides a control circuit and a control system, the control circuit includes: a control module, a watchdog module and a switch module, wherein: the first end of the control module is connected to the input end of the watchdog module, the second end of the control module is connected to the first input end of the switch module, the third end of the control module is connected to the output end of the switch module, and the output end of the watchdog module is connected to the second input end of the switch module; the control module is used to generate an enable signal and send the enable signal to the switch module; the watchdog module is used to generate a reset signal according to the working condition of the control module and send the reset signal to the switch module; the switch module is used to generate an execution signal according to the enable signal and the reset signal and send the execution signal to the control module; the control module is also used to execute the corresponding operation according to the execution signal. Thus, the control circuit generates an execution signal according to the working condition of the control module and the enable signal, so as to realize that whether the control module executes the reset operation is not only determined based on the working condition of the control module, but also determined based on the enable signal.
[0064] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present application, rather than to limit it. Although the present application has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present application.
Claims
1. A control circuit, characterized in that: It includes a control module, a watchdog module and a switch module, wherein: The first end of the control module is connected to the input end of the watchdog module, the second end of the control module is connected to the first input end of the switch module, the third end of the control module is connected to the output end of the switch module, and the output end of the watchdog module is connected to the second input end of the switch module; The control module is used to generate an enable signal and send the enable signal to the switch module; The watchdog module is used to generate a reset signal according to the working condition of the control module and send the reset signal to the switch module; The switch module is used to generate an execution signal according to the enable signal and the reset signal, and send the execution signal to the control module; The control module is further configured to execute a corresponding operation according to the execution signal.
2. The control circuit according to claim 1, characterized in that: The watchdog module includes a watchdog chip and a first resistor, wherein: The input end of the watchdog chip is connected to the first end of the control module, the power supply end of the watchdog chip is connected to the power supply, the output end of the watchdog chip is respectively connected to the first input end of the switch module and one end of the first resistor, and the other end of the first resistor is connected to the power supply.
3. The control circuit according to claim 2, characterized in that: The switch module includes a buffer chip, a second resistor and a third resistor, wherein: The first input end of the buffer chip is connected to the second end of the control module and one end of the second resistor respectively, the second input end of the buffer chip is connected to the output end of the watchdog module, the third end of the buffer chip is connected to the third end of the control module and one end of the third resistor respectively, the other end of the second resistor is used for grounding, and the other end of the third resistor is connected to the power supply.
4. The control circuit according to claim 3, characterized in that: The switch module further includes a filter capacitor, one end of which is connected to one end of the second resistor, and the other end of which is grounded.
5. The control circuit according to claim 1, characterized in that: The control module is further used to generate a pulse signal and send the pulse signal to the watchdog module; The watchdog module is specifically configured to generate a first reset signal and send the first reset signal to the switch module when the pulse signal is not received; The switch module is specifically configured to generate a reset execution signal according to the enable signal and the first reset signal when the enable signal is at a first level; The control module is specifically configured to perform a reset operation according to the reset execution signal.
6. The control circuit according to claim 5, characterized in that: The watchdog module is specifically configured to generate the first reset signal when the pulse signal is not received within a preset time period.
7. The control circuit according to claim 1, characterized in that: The control module is further used to generate a pulse signal and send the pulse signal to the watchdog module; The watchdog module is specifically configured to generate a second reset signal when receiving the pulse signal, and send the second reset signal to the switch module; The switch module is specifically configured to generate a shielding execution signal according to the enable signal and the second reset signal when the enable signal is at a first level; The control module is specifically configured to perform a signal shielding reset operation according to the shielding.
8. The control circuit according to claim 1, characterized in that: The switch module is specifically configured to generate a shielding execution signal according to the enable signal and the reset signal when the enable signal is at the second level; The control module is specifically configured to perform a signal shielding reset operation according to the shielding.
9. A control system, characterized in that: include: A robot and a control circuit as claimed in any one of claims 1 to 8.