Control circuit of release

Abstract

The utility model provides a control circuit of a release. The control circuit of the release comprises a comparison circuit, an AND gate circuit and a release driving circuit. A first input end of the comparison circuit is connected with an acquisition voltage signal obtained by acquiring bus current, a second input end of the comparison circuit is connected with a threshold voltage signal, an output end of the comparison circuit is electrically connected with a first input end of the AND gate circuit, and a second input end of the AND gate circuit is connected with a tripping voltage detection signal. The output end of the AND gate circuit is electrically connected with the driving end of the release driving circuit; and the AND gate circuit is used for outputting a driving signal to the tripper driving circuit when the comparison signal output by the comparison circuit and the accessed tripping voltage detection signal both meet the tripping requirement. The whole process is realized by adopting a hardware mode, compared with a software mode, the consumed time is shorter, and the timeliness of MCR starting is improved; in addition, due to the fact that a tripping voltage detection signal is considered, tripping control is more reliable.

Description

Technical Field

[0001] The utility model relates to the technical field of releasers, in particular to a control circuit of a releaser. Background Art

[0002] When the frame circuit breaker is closed, if the connected current exceeds the preset value, the MCR (connection current release) disconnects the circuit breaker without artificial delay to protect the circuit breaker. The current MCR uses a single-chip microcomputer to determine whether the current exceeds the preset value when closed based on the collected voltage signal obtained by collecting the bus current. If it exceeds the preset value, the release is driven to be in the tripping state.

[0003] However, the time for using software to perform MCR judgment is composed of power-on time (MCU power-on), initialization time (MCU power-on to ADC acquisition), waveform acquisition time and release action time. The whole process takes a long time, making the timeliness of MCR startup poor. Utility Model Content

[0004] In view of the deficiencies in the prior art, the utility model provides a control circuit for a release.

[0005] In one embodiment, the utility model provides a control circuit of a release, the control circuit of the release comprising:

[0006] Comparison circuit, AND gate circuit and release drive circuit;

[0007] The first input terminal of the comparison circuit is connected to the collected voltage signal obtained by collecting the bus current, the second input terminal of the comparison circuit is connected to the threshold voltage signal, the output terminal of the comparison circuit is electrically connected to the first input terminal of the AND gate circuit, the second input terminal of the AND gate circuit is connected to the trip voltage detection signal, and the output terminal of the AND gate circuit is electrically connected to the driving terminal of the release drive circuit;

[0008] The AND gate circuit is used to output a driving signal to the release drive circuit when the comparison signal output by the comparison circuit and the input trip voltage detection signal both meet the trip requirements, so that the release drive circuit drives the release to maintain the trip state.

[0009] In one embodiment, the control circuit of the trip unit further includes a processing unit;

[0010] The output terminal of the processing unit is electrically connected to the enable terminal of the AND gate circuit;

[0011] The processing unit is used for outputting a low-level enable signal to the enable end of the AND gate circuit when the release is in a closed state, so as to put the AND gate circuit in a shutdown state.

[0012] In one embodiment, the control circuit of the trip device further includes a monostable trigger, the comparison circuit includes a first comparator, a second comparator and a pull-up resistor, and the threshold voltage signal includes an upper threshold voltage signal and a lower threshold voltage signal;

[0013] The non-inverting input terminal of the first comparator and the inverting input terminal of the second comparator are both connected to the collected voltage signal, the inverting input terminal of the first comparator is connected to the lower threshold voltage signal, the non-inverting input terminal of the second comparator is connected to the upper threshold voltage signal, the output terminal of the first comparator, the output terminal of the second comparator and the input terminal of the monostable trigger are electrically connected to the pull-up resistor respectively, and the output terminal of the monostable trigger is electrically connected to the first input terminal of the AND gate circuit;

[0014] The monostable trigger is used to output a pulse trigger signal to the AND gate circuit when the received comparison signal is at a low level.

[0015] In one embodiment, the control circuit of the trip unit further includes a delay circuit;

[0016] The first end of the delay circuit is connected to the working voltage, and the second end of the delay circuit is electrically connected to the reset end of the monostable trigger;

[0017] The delay circuit is used to control the start of the monostable trigger by delaying the preset time after the working voltage is connected;

[0018] The delay circuit includes a capacitor and a resistor;

[0019] The first end of the resistor is connected to the working voltage, the second end of the resistor is electrically connected to the first end of the capacitor and the reset end of the monostable trigger respectively, and the second end of the capacitor is grounded.

[0020] In one embodiment, the control circuit of the trip unit further includes a threshold voltage generating circuit;

[0021] The output terminal of the threshold voltage generating circuit is electrically connected to the second input terminal of the comparison circuit to output a threshold voltage signal.

[0022] In one embodiment, the control circuit of the trip device further includes a processing unit, and the threshold voltage generating circuit includes a reference source chip;

[0023] The output end of the processing unit is electrically connected to the input end of the reference source chip, and the output end of the reference source chip is electrically connected to the second input end of the comparison circuit to output a threshold voltage signal.

[0024] In one embodiment, the control end of the processing unit is electrically connected to the controlled end of the reference source chip to output a storage signal so that the reference source chip stores and fixes the value corresponding to the threshold voltage signal.

[0025] In one embodiment, the threshold voltage signal includes an upper threshold voltage signal and a lower threshold voltage signal, and the comparison circuit includes a first comparator and a second comparator; the control circuit of the trip device also includes a processing unit, and the threshold voltage generation circuit includes a reference source chip, a subtractor, and an adder;

[0026] The output end of the processing unit is electrically connected to the input end of the reference source chip, and the control end of the processing unit is electrically connected to the controlled end of the reference source chip; the output end of the reference source chip is electrically connected to the second input end of the subtractor and the first input end of the adder respectively to output a set voltage signal;

[0027] The first input terminal of the subtractor is connected to the reference voltage signal, the second input terminal of the subtractor is connected to the set voltage signal, and the output terminal of the subtractor is electrically connected to the inverting input terminal of the first comparator to output a lower threshold voltage signal;

[0028] The first input terminal of the adder is respectively connected to the reference voltage signal and the set voltage signal, the second input terminal of the adder is grounded, and the output terminal of the adder is electrically connected to the in-phase input terminal of the second comparator to output an upper threshold voltage signal.

[0029] In one embodiment, the control circuit of the trip unit further includes a processing unit and an OR gate circuit;

[0030] The input end of the processing unit is connected to the collected voltage signal, the output end of the processing unit is electrically connected to the first input end of the OR gate circuit, the second input end of the OR gate circuit is electrically connected to the output end of the AND gate circuit, and the output end of the OR gate circuit is electrically connected to the driving end of the release driving circuit.

[0031] In one embodiment, the OR gate circuit includes a first diode and a second diode;

[0032] The anode of the first diode is electrically connected to the output end of the processing unit, the anode of the second diode is electrically connected to the output end of the AND gate circuit, and the cathode of the first diode and the cathode of the second diode are electrically connected to the driving end of the release driving circuit respectively.

[0033] Through the control circuit of the above-mentioned release, a comparison circuit, an AND gate circuit and a release drive circuit are set. The comparison circuit can judge the size of the bus current and output a corresponding comparison signal, while the AND gate circuit can simultaneously access the comparison signal and the trip voltage detection signal. Only when both meet the trip requirements at the same time will the drive signal be output to the release drive circuit to achieve the tripping of the release. The whole process is implemented in hardware, which takes less time than the software method, improving the timeliness of MCR startup; in addition, since the trip voltage detection signal is taken into account, the trip control is more reliable. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative work.

[0035] Figure 1 This is a schematic diagram of the structure of a control circuit of a release in one embodiment of the utility model;

[0036] Figure 2 This is a schematic diagram of the structure of an AND gate circuit in one embodiment of the utility model;

[0037] Figure 3 A schematic diagram of the structure of a comparison circuit and a monostable trigger in one embodiment of the utility model;

[0038] Figure 4 This is a schematic diagram of the structure of a reference source chip in one embodiment of the utility model;

[0039] Figure 5 This is a schematic diagram of the structure of a voltage follower circuit in one embodiment of the utility model;

[0040] Figure 6 It is a structural schematic diagram of a subtractor in one embodiment of the utility model;

[0041] Figure 7 This is a schematic diagram of the structure of an adder in one embodiment of the utility model;

[0042] Figure 8 It is a structural schematic diagram of a control circuit of a trip device including an OR gate circuit in one embodiment of the utility model;

[0043] Fig. 9 The figure is a schematic diagram of the structure of an OR gate circuit and a release driving circuit in one embodiment of the utility model. DETAILED DESCRIPTION

[0044] The following will be combined with the drawings in the embodiments of the utility model to clearly and completely describe the technical solutions in the embodiments of the utility model. Obviously, the described embodiments are only part of the embodiments of the utility model, not all of the embodiments. Based on the embodiments of the utility model, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the utility model.

[0045] In the description of the present utility model, it should be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside" and the like indicate positions or positional relationships based on the positions or positional relationships shown in the drawings, which are only for the convenience of describing the present utility model and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the present utility model. In addition, the terms "first" and "second" are only used for descriptive purposes, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, the features defined as "first" and "second" may explicitly or implicitly include one or more of the features. In the description of the present application, the meaning of "multiple" is two or more, unless otherwise clearly and specifically defined. In the present application, the word "exemplary" is used to mean "used as an example, illustration or description". Any embodiment described as "exemplary" in the present application is not necessarily interpreted as being more preferred or more advantageous than other embodiments. In order to enable any person skilled in the art to implement and use the utility model, the following description is given. In the following description, details are listed for the purpose of explanation. It should be understood that one of ordinary skill in the art can recognize that the utility model can be implemented without using these specific details. In other examples, well-known structures and processes will not be elaborated in detail to avoid unnecessary details that make the description of the utility model obscure. Therefore, the utility model is not intended to be limited to the embodiments shown, but is consistent with the widest range of principles and features disclosed in this application.

[0046] First, as Figure 1 As shown, in one embodiment, the utility model provides a control circuit of a release, and the control circuit of the release includes a comparison circuit, an AND gate circuit and a release driving circuit.

[0047] The first input terminal of the comparison circuit is connected to the collected voltage signal obtained by collecting the bus current, the second input terminal of the comparison circuit is connected to the threshold voltage signal, the output terminal of the comparison circuit is electrically connected to the first input terminal of the AND gate circuit, the second input terminal of the AND gate circuit is connected to the trip voltage detection signal AUX_CHK1, and the output terminal of the AND gate circuit is electrically connected to the driving end of the release drive circuit.

[0048] The AND gate circuit is used to output a driving signal to the tripper drive circuit when the comparison signal output by the comparison circuit and the input tripping voltage detection signal AUX_CHK1 both meet the tripping requirements, so that the tripper drive circuit drives the tripper to maintain the tripping state.

[0049] Among them, the AND gate circuit usually outputs a high level when high levels are input to both input terminals at the same time.

[0050] Among them, in this embodiment, the comparison circuit can be directly electrically connected to the AND gate circuit, that is, the comparison signal output by the comparison circuit is directly output to the AND gate circuit. Under this premise, when the comparison signal and the trip voltage detection signal AUX_CHK1 are both high level, it can be considered that they respectively represent that the trip requirement is met, so that the AND gate circuit outputs a high level drive signal to the trip drive circuit. In other words, when the comparison circuit outputs a high level comparison signal, it means that the bus current does not meet the trip closing requirement. Similarly, when the trip voltage detection signal AUX_CHK1 is high level, it means that the current trip voltage is sufficient to support the trip to complete the trip.

[0051] Through the control circuit of the above-mentioned release, a comparison circuit, an AND gate circuit and a release drive circuit are set. The comparison circuit can judge the size of the bus current and output a corresponding comparison signal, while the AND gate circuit can simultaneously access the comparison signal and the trip voltage detection signal. Only when both meet the trip requirements at the same time will the drive signal be output to the release drive circuit to achieve the tripping of the release. The whole process is implemented in hardware, which takes less time than the software method, and improves the timeliness of the MCR (connection current release) startup; in addition, since the trip voltage detection signal is taken into account, the trip control is more reliable.

[0052] like Figure 1 As shown, in one embodiment, the control circuit of the trip unit further includes a processing unit;

[0053] The output terminal of the processing unit is electrically connected to the enable terminal of the AND gate circuit;

[0054] The processing unit is used for outputting a low-level enable signal to the enable end of the AND gate circuit when the release is in a closed state, so as to put the AND gate circuit in a shutdown state.

[0055] Among them, the enable signal is usually used to control the start and stop of a device or chip. The present application mainly implements MCR by hardware before the circuit breaker is closed to ensure the reliability when the circuit breaker is closed. After the circuit breaker is closed, MCR is no longer needed. If MCR continues to exist, it is easy to have a significant impact on the normal power supply of the circuit breaker. Therefore, in this embodiment, the AND gate circuit is enabled and controlled by the processing unit. When the release is in a closed state (that is, the circuit breaker is closed), a low-level enable signal is output to the enable end of the AND gate circuit, so that the AND gate circuit is in a shutdown state. After that, even if the bus current does not meet the requirements and the trip voltage is sufficient to support the release to complete the tripping, that is, the two input ends of the AND gate circuit receive a high level at the same time, the AND gate circuit cannot output a high-level drive signal to the release drive circuit.

[0056] The processing unit includes but is not limited to a single chip microcomputer.

[0057] Specifically, Figure 2 As shown, the AND gate circuit includes an AND gate chip U15, the first input terminal 1A of the AND gate chip U15 is connected to the trigger signal drive through the diode D2, the second input terminal 1B of the AND gate chip U15 is connected to the trip voltage detection signal AUX_CHK1, and the enable terminal 2A of the AND gate chip U15 is connected to the enable signal MCU_MCR_EN through the pull-up resistor R115.

[0058] The trigger signal drive is obtained based on the comparison signal. When the comparison circuit is directly electrically connected to the AND gate circuit, the trigger signal drive is equal to the comparison signal. When the comparison circuit is electrically connected to the AND gate circuit through another circuit, the comparison signal is output to the circuit, and the circuit outputs the trigger signal drive according to the input comparison signal.

[0059] It is understandable that in Figure 2 In the embodiment, when the connected trigger signal drive, the trip voltage detection signal AUX_CHK1 and the enable signal MCU_MCR_EN are all at high level at the same time, the AND gate chip U15 outputs a high level drive signal Drive_NMOS.

[0060] Among them, when the trigger signal drive is at a high level, the diode D2 is cut off, and the +3.3V working voltage can be output to the first input terminal 1A of the AND gate chip U15 through the resistor R113, and the first input terminal 1A of the AND gate chip U15 receives a high level; conversely, when the trigger signal drive is at a low level, the diode D2 is turned on, the +3.3V working voltage is pulled down, and the first input terminal 1A of the AND gate chip U15 receives a low level.

[0061] Among them, since the enable signal MCU_MCR_EN output by the processing unit is input to the enable terminal 2A of the AND gate chip U15 through the pull-up resistor R115, when the processing unit works normally, it can output a low-level enable signal MCU_MCR_EN, pull down the +3.3V voltage connected to the pull-up resistor R115, so that the enable terminal 2A of the AND gate chip U15 is connected to a low level; when the processing unit is in initialization, it cannot output the enable signal MCU_MCR_EN, and is in a high-impedance state. The +3.3V voltage connected to the pull-up resistor R115 will not be pulled down, so that the enable terminal 2A of the AND gate chip U15 is connected to a high level; when the processing unit works normally, it can also output a high-level enable signal MCU_MCR_EN. In this case, regardless of the presence or absence of the pull-up resistor R115, the enable terminal 2A of the AND gate chip U15 can be connected to a high level.

[0062] By controlling the enabling of the AND gate circuit through the processing unit, the reliability of the MCR control can be further improved.

[0063] like Figure 3 As shown, in one embodiment, the control circuit of the release further includes a monostable trigger U13, the comparison circuit includes a first comparator U12B, a second comparator U12A and a pull-up resistor R89, and the threshold voltage signal includes an upper threshold voltage signal MCR_VREF_UP and a lower threshold voltage signal MCR_VREF_DOWN.

[0064] The non-inverting input terminal of the first comparator U12B and the inverting input terminal of the second comparator U12A are both connected to the collection voltage signal RC_IA, the inverting input terminal of the first comparator U12B is connected to the lower threshold voltage signal MCR_VREF_DOWN, the non-inverting input terminal of the second comparator U12A is connected to the upper threshold voltage signal MCR_VREF_UP, the output terminal of the first comparator U12B, the output terminal of the second comparator U12A and the input terminal TRIGGER of the monostable trigger U13 are electrically connected to the pull-up resistor R89 ​​respectively, and the output terminal OUTPUT of the monostable trigger U13 is electrically connected to the first input terminal of the AND gate circuit to output the trigger signal drive.

[0065] The monostable trigger U13 is used to output a pulse trigger signal drive to the AND gate circuit when the received comparison signal is at a low level.

[0066] Among them, in this embodiment, the comparison signal is output by the first comparator U12B, the second comparator U12A and the pull-up resistor R89. When the acquisition voltage signal RC_IA is less than the upper threshold voltage signal MCR_VREF_UP and greater than the lower threshold voltage signal MCR_VREF_DOWN, the first comparator U12B and the second comparator U12A both output a high impedance state, the +5V connected to the pull-up resistor R89 ​​is not pulled down, and the input terminal TRIGGER of the monostable trigger U13 is connected to the high-level comparison signal; when the acquisition voltage signal RC_IA is greater than the upper threshold voltage signal MCR_VREF_UP or less than the lower threshold voltage signal MCR_VREF_DOWN, the first comparator U12B outputs GND or the second comparator U12A outputs GND, the +5V voltage connected to the pull-up resistor R89 ​​is pulled down, and the input terminal TRIGGER of the monostable trigger U13 is connected to the low-level comparison signal.

[0067] From the above analysis, it can be seen that when the bus current does not meet the requirements (that is, the bus current is too large or too small), the input terminal TRIGGER of the monostable trigger U13 is connected to a low-level comparison signal, and when the bus current does not meet the requirements, the release needs to remain tripped, so the AND gate circuit needs to be connected to a high-level trigger signal drive, and the monostable trigger achieves the purpose of low-level input and high-level output. In this embodiment, the comparison circuit is not directly electrically connected to the AND gate circuit, but is electrically connected through the monostable trigger U13, that is, the comparison signal output by the comparison circuit is not directly output to the AND gate circuit. Under this premise, when the comparison signal is low, it can be considered that it represents that the tripping requirements are met. In other words, in this embodiment, when the comparison circuit outputs a low-level comparison signal, it means that the bus current does not meet the release closing requirements.

[0068] It should be noted that when the monostable trigger U13 detects that the voltage is lower than 5 / 3V (the comparison signal is at a low level), it outputs a pulse, and the size of the output pulse is determined by the resistor R103 and the capacitor C64. In this application, the output pulse can be roughly understood as the output of a high level, that is, the above-mentioned monostable trigger U13 outputting a high-level trigger signal drive does not contradict the output pulse at this time.

[0069] in, Figure 3 Only the control scheme of the A-phase transmission line is shown in the figure. In other embodiments, the control scheme of the B-phase transmission line and the control scheme of the C-phase transmission line may also be included. Specifically, with the control scheme of the A-phase transmission line, the B-phase transmission line and the C-phase transmission line also correspond to two comparators respectively. The connection method of the two comparators corresponding to the B-phase transmission line and the C-phase transmission line can refer to the above-mentioned A-phase transmission line. When there are the control schemes of the A-phase transmission line, the B-phase transmission line and the C-phase transmission line (i.e., the control schemes of the three-phase transmission line) at the same time, there are a total of six comparators, and the output terminals of the six comparators are respectively connected to Figure 3 The pull-up resistor R89 ​​in the circuit is electrically connected. As long as the bus current of one phase does not meet the requirement, the +5V voltage connected to the pull-up resistor R89 ​​is pulled down, and the input terminal TRIGGER of the monostable trigger U13 is connected to a low-level comparison signal.

[0070] In one embodiment, the control circuit of the release further includes a delay circuit.

[0071] The first end of the delay circuit is connected to the working voltage, and the second end of the delay circuit is electrically connected to the reset end of the monostable trigger.

[0072] The delay circuit is used to control the start of the monostable trigger by delaying a preset time after the working voltage is connected.

[0073] The delay circuit can be implemented by various typical delay chips.

[0074] Among them, due to certain changes in the process of power establishment, the collected voltage signal connected to the comparison circuit does not meet the circuit breaker closing requirements. If the subsequent tripping operation is performed at this time, it is easy to cause misoperation. Therefore, in view of this situation, this embodiment sets a delay circuit so that the monostable trigger will not start immediately after the working voltage is connected, but controls the monostable trigger to start after a preset time. The preset time must not be less than the time required for the power supply to be established and stabilized.

[0075] like Figure 3 As shown, in one embodiment, the delay circuit includes a capacitor C80 and a resistor R130.

[0076] The first end of the resistor R130 is connected to the working voltage (such as +5V working voltage), the second end of the resistor R130 is electrically connected to the first end of the capacitor C80 and the reset end RESET of the monostable trigger U13 respectively, and the second end of the capacitor C80 is grounded.

[0077] The capacitor C80 and the resistor R130 form a simple RC delay circuit, which has a simple structure and can well realize the delayed start of the monostable trigger U13.

[0078] like Figure 1 As shown, in one embodiment, the control circuit of the release further includes a threshold voltage generating circuit.

[0079] The output terminal of the threshold voltage generating circuit is electrically connected to the second input terminal of the comparison circuit to output a threshold voltage signal.

[0080] Among them, the threshold voltage generating circuit can output a threshold voltage signal of corresponding amplitude according to actual needs.

[0081] In one embodiment, the control circuit of the trip unit further includes a processing unit such as Figure 4 As shown, the threshold voltage generating circuit includes a reference source chip U17.

[0082] The output end of the processing unit is electrically connected to the input end VIN of the reference source chip U17 to output the DAC_MCR signal, the control end of the processing unit is electrically connected to the controlled end ADJ of the reference source chip U17 to output the MCR_ADJ storage signal, and the output end VOUT of the reference source chip U17 is electrically connected to the second input end of the comparison circuit to output the MCR_V signal.

[0083] In this embodiment, the output terminal VOUT of the reference source chip U17 is directly electrically connected to the subsequent comparison circuit, that is, the MCR_V signal output by the output terminal VOUT of the reference source chip U17 can be understood as a threshold voltage signal.

[0084] Among them, Figure 4 In the embodiment, the reference source chip U17 has a storage function. When the input terminal VIN of the reference source chip U17 is connected to the DAC_MCR signal, its controlled terminal ADJ is connected to the MCR_ADJ storage signal, and the value corresponding to the DAC_MCR signal can be stored and fixed. After the next power-on, the MCR_V signal corresponding to the stored value can also be directly output. That is, the DAC_MCR signal and the MCR_ADJ storage signal connected based on the processor can realize the output of the MCR_V signal with adjustable amplitude.

[0085] The above embodiments have mentioned that the threshold voltage signal may include an upper threshold voltage signal and a lower threshold voltage signal. Based on this premise, two reference source chips U17 in this embodiment may be provided to output adjustable upper threshold voltage signals and lower threshold voltage signals respectively.

[0086] In other embodiments, the output terminal of the processing unit may be electrically connected to the input terminal VIN of the reference source chip U17 through a voltage follower circuit to achieve impedance matching. Figure 5 As shown, the voltage follower circuit includes an operational amplifier U8A, and the in-phase input terminal of the operational amplifier U8A is electrically connected to the output terminal of the processing unit through a resistor R127 to access the MCU_DAC signal; Figure 4 and Figure 5 As shown, the inverting input terminal of the operational amplifier U8A is electrically connected to the output terminal of the operational amplifier U8A and the input terminal VIN of the reference source chip U17 through the resistor R35 to output the DAC_MCR signal.

[0087] In one embodiment, the threshold voltage signal includes an upper threshold voltage signal and a lower threshold voltage signal, and the comparison circuit includes a first comparator and a second comparator; the control circuit of the release also includes a processing unit, and the threshold voltage generating circuit includes a reference source chip, a subtractor and an adder.

[0088] Among them, the above embodiment has mentioned that two reference source chips can be set to output adjustable upper threshold voltage signal and lower threshold voltage signal respectively. In this embodiment, a subtractor and an adder can be used to output the upper threshold voltage signal and the lower threshold voltage signal, and the reference source chip is also used to achieve the adjustment.

[0089] like Figure 4 As shown, the output end of the processing unit is electrically connected to the input end VIN of the reference source chip U17 to output the DAC_MCR signal, the control end of the processing unit is electrically connected to the controlled end ADJ of the reference source chip U17 to access the MCR_ADJ signal, and the output end VOUT of the reference source chip U17 is electrically connected to the second input end of the comparison circuit to output the MCR_V signal.

[0090] Among them, in this embodiment, the output terminal VOUT of the reference source chip U17 is not directly electrically connected to the subsequent comparison circuit, but is electrically connected through an adder and a subtractor, that is, the MCR_V signal output by the output terminal VOUT of the reference source chip U17 can be understood as a set voltage signal.

[0091] like Figure 6 As shown, the subtractor includes an operational amplifier U11B, the non-inverting input terminal of the operational amplifier U11B is connected to the reference voltage signal (such as the reference voltage signal of VREF_2.5V) through resistors R101 and R105, the inverting input terminal of the operational amplifier U11B is connected to the set voltage signal MCR_V through resistors R98 and R99 and the operational amplifier U11A, and the output terminal of the operational amplifier U11B is electrically connected to the inverting input terminal of the first comparator to output the lower threshold voltage signal MCR_VREF_DOWN.

[0092] The operational amplifier U11A is used to fine-tune the connected setting voltage signal MCR_V, so as to output a first setting voltage signal with an amplitude slightly smaller than the setting voltage signal MCR_V. Since the resistance values ​​of the resistors R99, R98, R101 and R105 are the same, the lower threshold voltage signal MCR_VREF_DOWN outputted from the output end of the operational amplifier U11B is equal to the difference between the reference voltage signal VREF_2.5V and the first setting voltage signal. Since the amplitude of the first setting voltage signal is slightly smaller than the setting voltage signal MCR_V, the output lower threshold voltage signal MCR_VREF_DOWN is slightly larger than the difference between the reference voltage signal VREF_2.5V and the setting voltage signal MCR_V.

[0093] like Figure 7 As shown, the adder includes an operational amplifier U11D, a first input terminal of the operational amplifier U11D is connected to a reference voltage signal (such as a reference voltage signal of VREF_2.5V) through a resistor R122 and a set voltage signal MCR_V through a resistor R124 and an operational amplifier U11C, an inverting input terminal of the operational amplifier U11D is grounded through a resistor 121 and a resistor R119, and an output terminal of the operational amplifier U11D is electrically connected to a non-inverting input terminal of the second comparator to output an upper threshold voltage signal MCR_VREF_UP.

[0094] Among them, the operational amplifier U11C is used to fine-tune the connected setting voltage signal MCR_V, so as to output a second setting voltage signal with an amplitude slightly smaller than the setting voltage signal MCR_V. Since the resistance values ​​of the resistors R119, R121, R122 and R124 are the same, the upper threshold voltage signal MCR_VREF_UP outputted by the output terminal of the operational amplifier U11D is equal to the sum of the reference voltage signal VREF_2.5V and the second setting voltage signal. Since the amplitude of the second setting voltage signal is slightly smaller than the setting voltage signal MCR_V, the output upper threshold voltage signal MCR_VREF_UP is slightly smaller than the sum of the reference voltage signal VREF_2.5V and the setting voltage signal MCR_V.

[0095] By fine-tuning, the lower threshold voltage signal MCR_VREF_DOWN is made larger than the actual value, and the upper threshold voltage signal MCR_VREF_UP is made smaller than the actual value, that is, a smaller window is obtained, thereby ensuring that the subsequent tripping judgment is more stable.

[0096] like Figure 8 As shown, in one embodiment, the control circuit of the trip unit further includes a processing unit and an OR gate circuit.

[0097] The input end of the processing unit is connected to the collected voltage signal, the output end of the processing unit is electrically connected to the first input end of the OR gate circuit, the second input end of the OR gate circuit is electrically connected to the output end of the AND gate circuit, and the output end of the OR gate circuit is electrically connected to the driving end of the release driving circuit.

[0098] Among them, the core of this application is to implement MCR by hardware, while the traditional solution is to implement MCR by software. In this embodiment, both methods can be compatible at the same time, that is, the AND gate circuit and the processing unit output their own drive signals to the release drive circuit through the OR gate circuit. When any of the drive signals is at a high level, the OR gate circuit outputs a high level.

[0099] like Fig. 9 As shown, in one embodiment, the OR gate circuit includes a first diode D3 and a second diode D4.

[0100] The anode of the first diode D3 is electrically connected to the output end of the processing unit to access the drive signal Trip, the anode of the second diode D4 is electrically connected to the output end of the AND gate circuit to access the drive signal Drive_NMOS, and the cathode of the first diode D3 and the cathode of the second diode D4 are electrically connected to the drive end of the release drive circuit (such as the gate of the MOS tube Q2), respectively.

[0101] When either the driving signal Trip or the driving signal Drive_NMOS is at a high level, the MOS tube Q2 is turned on, the +12V working voltage passes through the resistor R73, the tripper J10 and the MOS tube Q2 to the ground, and the tripper J10 is energized to realize the tripping operation.

[0102] It should be added that the devices not mentioned above in the figure are all basic components for realizing the basic functions of the circuit and will not be described in detail here.

[0103] In a second aspect, in one embodiment, the utility model further provides a circuit breaker, the circuit breaker comprising a release and a control circuit of the release in any one of the above embodiments.

[0104] Through the above-mentioned circuit breaker, a comparison circuit, an AND gate circuit and a tripper drive circuit are set. The comparison circuit can judge the magnitude of the bus current and output a corresponding comparison signal, while the AND gate circuit can simultaneously access the comparison signal and the tripping voltage detection signal. Only when both meet the tripping requirements at the same time will the drive signal be output to the tripper drive circuit to achieve the tripping of the tripper. The whole process is implemented in hardware, which takes less time than the software method, improving the timeliness of MCR startup; in addition, since the tripping voltage detection signal is taken into account, the tripping control is more reliable.

[0105] In the above embodiments, the description of each embodiment has its own emphasis. For parts that are not described in detail in a certain embodiment, please refer to the detailed description of other embodiments above, and will not be repeated here.

[0106] The control circuit and circuit breaker of a release provided by the utility model are introduced in detail above. The principle and implementation mode of the utility model are explained in this article by using specific examples. The description of the above embodiments is only used to help understand the method and core idea of ​​the utility model. At the same time, for technicians in this field, according to the idea of ​​the utility model, there will be changes in the specific implementation mode and application scope. In summary, the content of this specification should not be understood as limiting the utility model.

[0107] The technical features of the above embodiments may be combined arbitrarily. To make the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

Claims

1. A control circuit of a trip device, characterized in that: The control circuit of the release comprises: Comparison circuit, AND gate circuit and release drive circuit; The first input terminal of the comparison circuit is connected to a collected voltage signal obtained by collecting bus current, the second input terminal of the comparison circuit is connected to a threshold voltage signal, the output terminal of the comparison circuit is electrically connected to the first input terminal of the AND gate circuit, the second input terminal of the AND gate circuit is connected to a trip voltage detection signal, and the output terminal of the AND gate circuit is electrically connected to a driving terminal of the release drive circuit; The AND gate circuit is used to output a driving signal to the release drive circuit when the comparison signal output by the comparison circuit and the input trip voltage detection signal both meet the trip requirement, so that the release drive circuit drives the release to maintain a trip state.

2. The control circuit of the release according to claim 1, characterized in that: The control circuit of the release also includes a processing unit; The output terminal of the processing unit is electrically connected to the enable terminal of the AND gate circuit; The processing unit is used for outputting a low-level enable signal to the enable end of the AND gate circuit when the release is in a closed state, so as to put the AND gate circuit in a shutdown state.

3. The control circuit of the release according to claim 1, characterized in that: The control circuit of the release device further includes a monostable trigger, the comparison circuit includes a first comparator, a second comparator and a pull-up resistor, and the threshold voltage signal includes an upper threshold voltage signal and a lower threshold voltage signal; The non-inverting input terminal of the first comparator and the inverting input terminal of the second comparator are both connected to the collected voltage signal, the inverting input terminal of the first comparator is connected to the lower threshold voltage signal, and the non-inverting input terminal of the second comparator is connected to the upper threshold voltage signal, the output terminal of the first comparator, the output terminal of the second comparator and the input terminal of the monostable trigger are electrically connected to the pull-up resistor respectively, and the output terminal of the monostable trigger is electrically connected to the first input terminal of the AND gate circuit; The monostable trigger is used for outputting a pulse trigger signal to the AND gate circuit when the received comparison signal is at a low level.

4. The control circuit of the release according to claim 3, characterized in that: The control circuit of the release also includes a delay circuit; The first end of the delay circuit is connected to the working voltage, and the second end of the delay circuit is electrically connected to the reset end of the monostable trigger; The delay circuit is used to delay the monostable trigger for a preset time after the working voltage is connected; the delay circuit includes a capacitor and a resistor; The first end of the resistor is connected to the working voltage, the second end of the resistor is electrically connected to the first end of the capacitor and the reset end of the monostable trigger respectively, and the second end of the capacitor is grounded.

5. The control circuit of the release according to any one of claims 1 to 4, characterized in that: The control circuit of the release also includes a threshold voltage generating circuit; The output terminal of the threshold voltage generating circuit is electrically connected to the second input terminal of the comparison circuit to output the threshold voltage signal.

6. The control circuit of the release according to claim 5, characterized in that: The control circuit of the release further includes a processing unit, and the threshold voltage generating circuit includes a reference source chip; The output end of the processing unit is electrically connected to the input end of the reference source chip, and the output end of the reference source chip is electrically connected to the second input end of the comparison circuit to output the threshold voltage signal.

7. The control circuit of the release according to claim 6, characterized in that: The control end of the processing unit is electrically connected to the controlled end of the reference source chip to output a storage signal so that the reference source chip stores and fixes the value corresponding to the threshold voltage signal.

8. The control circuit of the release according to claim 5, characterized in that: The threshold voltage signal includes an upper threshold voltage signal and a lower threshold voltage signal, and the comparison circuit includes a first comparator and a second comparator; the control circuit of the trip device also includes a processing unit, and the threshold voltage generation circuit includes a reference source chip, a subtractor and an adder; The output end of the processing unit is electrically connected to the input end of the reference source chip, and the control end of the processing unit is electrically connected to the controlled end of the reference source chip; the output end of the reference source chip is electrically connected to the second input end of the subtractor and the first input end of the adder, respectively, to output a set voltage signal; The first input terminal of the subtractor is connected to the reference voltage signal, the second input terminal of the subtractor is connected to the set voltage signal, and the output terminal of the subtractor is electrically connected to the inverting input terminal of the first comparator to output the lower threshold voltage signal; The first input terminal of the adder is respectively connected to the reference voltage signal and the set voltage signal, the second input terminal of the adder is grounded, and the output terminal of the adder is electrically connected to the non-inverting input terminal of the second comparator to output the upper threshold voltage signal.

9. The control circuit of the release according to any one of claims 1 to 4, characterized in that: The control circuit of the release also includes a processing unit and an OR gate circuit; The input end of the processing unit is connected to the collected voltage signal, the output end of the processing unit is electrically connected to the first input end of the OR gate circuit, the second input end of the OR gate circuit is electrically connected to the output end of the AND gate circuit, and the output end of the OR gate circuit is electrically connected to the driving end of the release driving circuit.

10. The control circuit of the release according to claim 9, characterized in that: The OR gate circuit includes a first diode and a second diode; The anode of the first diode is electrically connected to the output end of the processing unit, the anode of the second diode is electrically connected to the output end of the AND gate circuit, and the cathode of the first diode and the cathode of the second diode are electrically connected to the driving end of the release driving circuit respectively.

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