Chip package and optical module

Abstract

The utility model provides a chip package and an optical module. The chip package comprises a substrate, a cover plate, a first chip, a second chip and a heat conduction part. The first chip is a main heat source relative to the second chip, and the first chip has a higher heat dissipation requirement relative to the second chip. In the invention, in order to improve the heat dissipation performance of the first chip, the heat conduction part is arranged below the first chip and the second chip, so that the heat generated by the first chip is transferred to the second chip side with relatively low heat dissipation requirement through the heat conduction part, and the heat dissipation path of the first chip is further expanded. According to the invention, the heat transfer in the cavity is realized through the heat conduction part, the heat generated by the first chip can be transferred in the package, the heat generated by the first chip is transferred to the second chip side in the package through the heat conduction part, and then the heat is transferred to the outside through the cover plate or the substrate, so that the heat dissipation channel and the heat dissipation path are expanded, and the heat dissipation efficiency is improved. Therefore, the effective heat dissipation area of the cover plate or the substrate is enlarged, and the heat dissipation capability is improved.

Description

Technical Field

[0001] The present disclosure relates to the field of optical communication technology, and in particular to a chip package and an optical module. Background Art

[0002] With the development of optical communication technology, chips are moving towards high integration and miniaturization, and the chip power density is constantly increasing. Chip heat dissipation design has become one of the key factors in improving chip working reliability. Utility Model Content

[0003] The embodiments of the present disclosure provide a chip package and an optical module to improve the heat dissipation performance of the chip.

[0004] The chip package provided by the present disclosure includes:

[0005] substrate;

[0006] A cover plate, connected to the base plate to form a cavity;

[0007] A first chip is disposed in the cavity, and a portion of heat generated by the first chip is transferred to the outside via the cover plate or the substrate;

[0008] A second chip is disposed in the cavity, and heat generated by the second chip is transferred to the outside via the cover plate or the substrate; wherein the power density of the second chip is less than the power density of the first chip, and the junction temperature allowed by the second chip is higher than the junction temperature allowed by the first chip;

[0009] The heat conducting part has a bottom surface disposed on the substrate surface and a top surface supporting the first chip and the second chip respectively;

[0010] Another part of the heat generated by the first chip is transferred to the second chip via the thermal conduction portion, and then transferred to the outside via the cover plate or the substrate.

[0011] The chip package provided in the present disclosure includes a substrate, a cover plate, a first chip, a second chip and a thermal conduction part. The substrate and the cover plate are connected to form a cavity. The first chip, the second chip and the thermal conduction part are arranged in the cavity. Part of the heat generated by the first chip is transferred to the outside through the cover plate or the substrate. The heat generated by the second chip is also transferred to the outside through the cover plate or the substrate. If the power density of the first chip is greater than the power density of the second chip, the heat generated by the first chip is greater than the heat generated by the second chip, and then the temperature of the first chip is higher than the temperature of the second chip. At the same time, the junction temperature allowed by the second chip is higher than the junction temperature allowed by the first chip, then the first chip is the main heat source relative to the second chip, and the first chip has a higher heat dissipation requirement than the second chip. In the present disclosure, in order to improve the heat dissipation performance of the first chip, a thermal conduction part is arranged below the first chip and the second chip to transfer the heat generated by the first chip to the second chip side with relatively low heat dissipation requirements via the thermal conduction part, thereby expanding the heat dissipation path of the first chip. Since the temperature of the first chip is higher than the temperature of the second chip, the heat generated by the first chip is transferred to the second chip through the thermal conduction part under the temperature difference drive, and then transferred to the outside through the cover plate or the substrate. It can be seen that in the present disclosure, the heat dissipation path of the heat generated by the first chip includes: a part of the heat generated by the first chip is transferred to the outside through the cover plate or substrate, and the other part of the heat is transferred to the second chip side through the thermal conduction part, and then transferred to the outside through the cover plate or substrate. In the present disclosure, by setting a thermal conduction part under the first chip and the second chip, the heat transfer in the cavity is realized, the heat generated by the first chip can be transferred inside the package, and the heat generated by the first chip is transferred to the second chip side inside the package through the thermal conduction part, and then the heat is transferred to the outside through the cover plate or substrate, which expands the heat dissipation channel and heat dissipation path, thereby expanding the effective heat dissipation area of ​​the cover plate or substrate and greatly improving the heat dissipation capacity. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] In order to more clearly illustrate the technical solutions in the present disclosure, the following briefly introduces the drawings used in some embodiments of the present disclosure. Obviously, the drawings described below are only drawings of some embodiments of the present disclosure. For ordinary technicians in this field, other drawings can also be obtained based on these drawings. In addition, the drawings described below can be regarded as schematic diagrams, and are not limitations on the actual size of the product involved in the embodiments of the present disclosure, the actual process of the method, the actual timing of the signal, etc.

[0013] Figure 1 A structural diagram of a chip package provided according to some embodiments of the present disclosure;

[0014] Figure 2 A schematic diagram of the heat dissipation principle of a chip package provided according to some embodiments of the present disclosure;

[0015] Figure 3 A partial architecture diagram of an optical communication system provided according to some embodiments of the present disclosure;

[0016] Figure 4 A partial structural diagram of a host computer provided according to some embodiments of the present disclosure;

[0017] Figure 5 A structural diagram of an optical module provided according to some embodiments of the present disclosure;

[0018] Figure 6 An exploded view of an optical module provided according to some embodiments of the present disclosure;

[0019] Figure 7 An internal structure diagram of an optical module provided according to some embodiments of the present disclosure;

[0020] Figure 8 An exploded view of a coherent optical component provided according to some embodiments of the present disclosure;

[0021] Fig. 9 A partial structural diagram of a coherent optical component provided according to some embodiments of the present disclosure;

[0022] Fig.10 A partial cross-sectional view of a coherent optical component provided according to some embodiments of the present disclosure;

[0023] Fig.11 A partial exploded view of a coherent optical component provided according to some embodiments of the present disclosure;

[0024] Fig.12 A schematic diagram of chip heat dissipation of a coherent optical component provided according to some embodiments of the present disclosure. DETAILED DESCRIPTION

[0025] Some embodiments of the present disclosure will be described in detail below in conjunction with the accompanying drawings. However, the described embodiments are only a part of the embodiments of the present disclosure, rather than all of the embodiments. Based on the embodiments provided by the present disclosure, all other embodiments obtained by ordinary technicians in this field are within the scope of protection of the present disclosure.

[0026] Unless the context requires otherwise, throughout the specification and claims, the term "comprising" is to be interpreted as having an open, inclusive meaning, that is, "including, but not limited to"; the terms "first" and "second" are not to be understood as indicating or implying relative importance or indicating an upper limit on quantity; the term "plurality" means two or more; the term "connected" is to be understood in a broad sense, for example, "connected" can be a fixed connection, a detachable connection, or an integral connection, and can be directly connected or indirectly connected through an intermediate medium; the use of the terms "suitable for" or "configured to" implies open and inclusive language, which does not exclude devices that are suitable for or configured to perform additional tasks or steps; descriptions such as "parallel", "perpendicular", "same", "consistent", and "flush" are not limited to absolute mathematical theoretical relationships, but also include an acceptable error range generated in practice, and also include differences based on the same design concept but due to manufacturing reasons.

[0027] With the development of optical communication technology, chips are moving towards high integration and miniaturization, and the chip power density is constantly increasing. Chip heat dissipation design has become one of the key factors in improving chip working reliability.

[0028] In the present disclosure, a thermal conduction portion is provided below the first chip and the second chip to realize heat transfer within the cavity. The heat generated by the first chip can be transferred inside the package. The heat generated by the first chip is transferred to the second chip side inside the package through the thermal conduction portion, and then the heat is transferred to the outside through the cover plate or the substrate, thereby expanding the heat dissipation channel and the heat dissipation path, thereby expanding the effective heat dissipation area of ​​the cover plate or the substrate, and greatly improving the heat dissipation capacity.

[0029] Figure 1 FIG. 1 is a structural diagram of a chip package provided according to some embodiments of the present disclosure. Figure 1 As shown, the present disclosure provides a chip package. The chip package may include a substrate 1101. The substrate 1101 has a supporting function.

[0030] For example, the substrate 1101 may be a resin substrate with poor heat dissipation performance. For example, the substrate 1101 may be a ceramic, glass or other substrate with good thermal conductivity so as to have electrical connection performance and heat dissipation performance.

[0031] The chip package may include a first chip 1102 . The first chip 1102 is disposed on a surface of a substrate 1101 .

[0032] The first chip 1102 may be an electrical chip, or may be an optical chip.

[0033] The chip package may include a second chip 1103. The second chip 1103 is disposed on a surface of the substrate 1101. The second chip 1103 may be an electrical chip, or may be an optical chip.

[0034] The first chip 1102 is configured as an electrical chip or an optical chip, and the second chip 1103 is configured as an electrical chip or an optical chip.

[0035] Exemplarily, the first chip 1102 may be an electrical chip, and the second chip 1103 may be an electrical chip.

[0036] By way of example, the first chip 1102 may be an electrical chip, and the second chip 1103 may be an optical chip.

[0037] Exemplarily, the first chip 1102 may be an optical chip, and the second chip 1103 may be an optical chip.

[0038] Exemplarily, the first chip 1102 may be an optical chip, and the second chip 1103 may be an electrical chip.

[0039] The chip package may include a cover plate 1104. The cover plate 1104 is connected to the substrate 1101 to form a cavity. The first chip 1102 and the second chip 1103 are respectively arranged in the cavity. The cover plate 1104 is mainly used for heat dissipation and controlling package warping.

[0040] The cover plate 1104 may be made of metal materials such as copper, zinc, or ceramic materials.

[0041] The heat dissipation performance of the cover plate 1104 is better than that of the substrate 1101. The heat generated by the first chip 1102 and the second chip 1103 can be transferred to the outside through the cover plate 1104. The heat can also be transferred to the outside through the substrate 1101.

[0042] In some embodiments, when the first chip 1102 and the second chip 1103 are arranged on the surface of the substrate 1101, the chip surface has a wire bonding pad, the area available for heat dissipation is small, and the chip is at a certain distance from the cover plate 1104. Due to the poor heat transfer performance of the air, a small part of the heat generated by the chip is dissipated to the outside through the cover plate 1104.

[0043] In some embodiments, based on the fact that the heat dissipation performance of the cover plate 1104 is better than that of the substrate 1101 , the first chip 1102 and the second chip 1103 can be disposed on the surface of the cover plate 1104 and then electrically connected to the circuit board through an adapter plate.

[0044] In some embodiments, the chip package may include a first thermal interface material 1105 .

[0045] The first thermal interface material 1105 is disposed between the first chip 1102 and the cover plate 1104. The first thermal interface material 1105 can increase the thermal conductivity between the first chip 1102 and the cover plate 1104.

[0046] The first thermal interface material 1105 includes various heat dissipation materials such as heat dissipation gel, heat dissipation silicone grease, metal, solder, graphene, etc., and has good thermal conductivity.

[0047] Exemplarily, the first thermal interface material 1105 transfers the heat generated by the first chip 1102 upward to the surface of the cover plate 1104 .

[0048] In some embodiments, the chip package may include a second thermal interface material 1106 .

[0049] The second thermal interface material 1106 is disposed between the second chip 1103 and the cover plate 1104. The second thermal interface material 1106 can increase the thermal conductivity between the second chip 1103 and the cover plate 1104.

[0050] The second thermal interface material 1106 includes various heat dissipation materials such as heat dissipation gel, heat dissipation silicone grease, metal, solder, graphene, etc., and has good thermal conductivity.

[0051] Exemplarily, the second thermal interface material 1106 transfers the heat generated by the second chip 1103 upward to the surface of the cover plate 1104 .

[0052] The chip package may include a thermal via 1107. Based on the thermal via 1107, heat can be transferred inside the package, and the heat generated by the first chip 1102 is transferred to the second chip 1103 side inside the package through the thermal via 1107, thereby expanding the heat dissipation path of the first chip 1102.

[0053] The material of the thermal conductive portion 1107 can be the same as that of the substrate 1101 , or can be a different material from that of the substrate 1101 .

[0054] The material of the thermal conductive part 1107 may include metal, alloy, resin, graphene, ALN and other ceramics.

[0055] The thermal conduction part 1107 may be disposed on the surface of the substrate 1101. The top surface of the thermal conduction part 1107 is fixedly connected to the bottom surfaces of the first chip 1102 and the second chip 1103, respectively, to support the first chip 1102 and the second chip 1103. Exemplarily, a recessed part is formed on the surface of the substrate 1101, and the thermal conduction part 1107 is embedded in the recessed part as an embedded structure. When the thermal conduction part 1107 is an embedded structure, the thermal conduction part 1107 may be located on the surface of the substrate 1101, or may penetrate multiple layers of the substrate 1101.

[0056] Exemplarily, the thermal conductive portion 1107 may be a layer of metal wiring of the substrate 1101. That is, the metal wiring is set as the thermal conductive portion 1107. The metal wiring has the functions of heat dissipation and electrical interconnection.

[0057] For example, the power density of the first chip 1102 is greater than the power density of the second chip 1103 , so the heat generated by the first chip 1102 is greater than the heat generated by the second chip 1103 , and the temperature of the first chip 1102 is higher than the temperature of the second chip 1103 .

[0058] In some embodiments, the junction temperature allowed by the first chip 1102 is lower than the junction temperature allowed by the second chip 1103. The junction temperature refers to the temperature at the junction of the P layer and the N layer in the middle of the chip. The junction temperature is generally defined by the upper limit of the safe junction temperature corresponding to the maximum dissipated power. When the temperature of the chip exceeds the allowed junction temperature, the working reliability of the chip is greatly reduced.

[0059] The temperature of the first chip 1102 is higher than that of the second chip 1103. At the same time, the junction temperature allowed by the second chip 1103 is higher than that allowed by the first chip 1102. Therefore, the first chip 1102 is the main heat source relative to the second chip 1103, and the first chip 1102 has a higher heat dissipation requirement than the second chip 1103.

[0060] In the present disclosure, in order to improve the heat dissipation performance of the first chip 1102 and meet the heat dissipation requirements of the first chip 1102, a thermal conductive portion is provided below the first chip 1102 and the second chip 1103 to transfer the heat generated by the first chip 1102 to the side of the second chip 1103 where the heat dissipation requirement is relatively low via the thermal conductive portion, thereby expanding the heat dissipation path of the first chip 1102.

[0061] Since the temperature of the first chip 1102 is higher than that of the second chip 1103 , the heat generated by the first chip 1102 driven by the temperature difference is transferred to the second chip 1103 through the thermal conduction part, and then transferred to the outside through the cover plate 1104 or the substrate 1101 .

[0062] The junction temperature allowed by the second chip 1103 is higher than the junction temperature allowed by the first chip 1102, which means that the second chip 1103 can withstand a higher temperature. Therefore, when the heat generated by the first chip 1102 is transferred to the second chip 1103 through the thermal conductive part 1107, the working performance of the second chip 1103 is less affected. This also provides feasibility for heat transfer inside the package.

[0063] In some embodiments, a portion of the heat generated by the first chip 1102 is transferred upward to the cover plate 1104 or the substrate 1101 via the first thermal interface material 1105, and then transferred to the outside; another portion of the heat generated by the first chip 1102 is transferred downward to the thermal conductive portion 1107, and then the heat is laterally transmitted along the inside of the thermal conductive portion 1107 to the side of the second chip 1103, and then transferred upward through the second thermal interface material 1106, the cover plate 1104 or the substrate 1101.

[0064] In the present disclosure, a thermal conduction portion 1107 is provided below the first chip 1102 and the second chip 1103 to achieve heat transfer within the cavity. The heat generated by the first chip 1102 can be transferred inside the package. The heat generated by the first chip 1102 is transferred to the second chip 1103 side inside the package through the thermal conduction portion 1107, and then the heat is transferred to the outside through the cover plate 1104 or the substrate 1101, thereby expanding the heat dissipation channel and heat dissipation path of the first chip 1102, thereby expanding the effective heat dissipation area of ​​the cover plate 1104 or the substrate 1101, greatly improving the heat dissipation capacity, and thus ensuring the working performance of the first chip 1102.

[0065] Figure 2 FIG. 1 is a schematic diagram of the heat dissipation principle of a chip package provided according to some embodiments of the present disclosure. Figure 2 As shown, the chip package includes a thermal via 1107 .

[0066] The first chip 1102 and the second chip 1103 are respectively disposed on the surface of the thermal conductive portion 1107 .

[0067] A first thermal interface material 1105 is disposed above the first chip 1102 .

[0068] A second thermal interface material 1106 is disposed above the second chip 1103 .

[0069] A first thermal interface material 1105 and a first chip 1102 are respectively disposed at upper and lower positions of one end of the thermal conductive portion 1107 .

[0070] A second thermal interface material 1106 and a second chip 1103 are respectively disposed at the upper and lower positions of the other end of the thermal conductive portion 1107 .

[0071] In the present disclosure, the heat generated by the first chip 1102 can be transferred inside the package. The heat generated by the first chip 1102 can be transferred to the second chip 1103 side inside the package through the thermal conduction part 1107, and then the heat is transferred to the outside through the cover plate 1104 or the substrate 1101, thereby expanding the heat dissipation channel and heat dissipation path of the first chip 1102.

[0072] In some embodiments of the present disclosure, heat transfer inside the package is achieved by providing a thermal conductive portion 1107. Exemplarily, the heat dissipation path of the heat generated by the first chip 1102 includes: a portion of the heat generated by the first chip 1102 is transferred upward to the cover plate 1104 or the substrate 1101 via the first thermal interface material 1105, and then transferred to the outside; another portion of the heat generated by the first chip 1102 is transferred downward to the thermal conductive portion 1107, and then the heat is laterally transferred along the inside of the thermal conductive portion 1107 to the side of the second chip 1103, and then transferred upward through the second thermal interface material 1106, the cover plate 1104 or the substrate 1101.

[0073] In the present disclosure, a thermal conductive portion 1107 is provided to achieve internal heat transfer within the package, thereby expanding the heat dissipation channel and heat dissipation path of the first chip 1102 with higher heat dissipation requirements. This increases the effective heat dissipation area of ​​the cover plate 1104 or the substrate 1101, greatly improving the heat dissipation capacity, and thus ensuring the working performance of the first chip 1102.

[0074] In the present disclosure, based on the above chip packaging, the above chip packaging can be applied to optical communication technology, and can also be applied to other applications. The application of chip packaging is exemplified below by taking the application of the above chip packaging to an optical module as an example.

[0075] In optical communication technology, in order to establish information transmission between information processing devices, it is necessary to load information onto light and use the propagation of light to achieve information transmission. Here, the light loaded with information is an optical signal. When optical signals are transmitted in information transmission equipment, the loss of optical power can be reduced, so high-speed, long-distance, and low-cost information transmission can be achieved. The signals that information processing equipment can recognize and process are electrical signals. Information processing equipment usually includes optical network terminals (Optical Network Unit, ONU), gateways, routers, switches, mobile phones, computers, servers, tablets, televisions, etc., and information transmission equipment usually includes optical fibers and optical waveguides.

[0076] The optical module can realize the mutual conversion between optical signals and electrical signals between information processing equipment and information transmission equipment. For example, at least one of the optical signal input end or the optical signal output end of the optical module is connected to an optical fiber, and at least one of the electrical signal input end or the electrical signal output end of the optical module is connected to an optical network terminal; the first optical signal from the optical fiber is transmitted to the optical module, and the optical module converts the first optical signal into a first electrical signal, and transmits the first electrical signal to the optical network terminal; the second electrical signal from the optical network terminal is transmitted to the optical module, and the optical module converts the second electrical signal into a second optical signal, and transmits the second optical signal to the optical fiber. Since multiple information processing devices can transmit information through electrical signals, at least one of the multiple information processing devices needs to be directly connected to the optical module, and all information processing devices do not need to be directly connected to the optical module. Here, the information processing device directly connected to the optical module is called the upper computer of the optical module. In addition, the optical signal input end or the optical signal output end of the optical module can be called an optical port, and the electrical signal input end or the electrical signal output end of the optical module can be called an electrical port.

[0077] Figure 3 FIG. 1 is a partial architecture diagram of an optical communication system provided according to some embodiments of the present application. Figure 3 As shown, the optical communication system mainly includes a remote information processing device 1000 , a local information processing device 2000 , a host computer 100 , an optical module 200 , an optical fiber 101 and a network cable 103 .

[0078] One end of the optical fiber 101 extends toward the remote information processing device 1000, and the other end of the optical fiber 101 is connected to the optical module 200 through the optical port of the optical module 200. The optical signal can be totally reflected in the optical fiber 101, and the propagation of the optical signal in the total reflection direction can almost maintain the original optical power. The optical signal undergoes multiple total reflections in the optical fiber 101 to transmit the optical signal from the remote information processing device 1000 to the optical module 200, or to transmit the optical signal from the optical module 200 to the remote information processing device 1000, thereby realizing long-distance, low-power loss information transmission.

[0079] The optical communication system may include one or more optical fibers 101, and the optical fibers 101 are detachably connected or fixedly connected to the optical module 200. The host computer 100 is configured to provide data signals to the optical module 200, receive data signals from the optical module 200, or monitor or control the working state of the optical module 200.

[0080] The host computer 100 includes a substantially rectangular housing and an optical module interface 102 disposed on the housing. The optical module interface 102 is configured to connect to the optical module 200 so that the host computer 100 and the optical module 200 establish a unidirectional or bidirectional electrical signal connection.

[0081] The host computer 100 also includes an external electrical interface, which can be connected to an electrical signal network. For example, the external electrical interface includes a Universal Serial Bus (USB) interface or a network cable interface 104, and the network cable interface 104 is configured to access the network cable 103 so that the host computer 100 establishes a unidirectional or bidirectional electrical signal connection with the network cable 103. One end of the network cable 103 is connected to the local information processing device 2000, and the other end of the network cable 103 is connected to the host computer 100, so as to establish an electrical signal connection between the local information processing device 2000 and the host computer 100 through the network cable 103. For example, the third electrical signal sent by the local information processing device 2000 is transmitted to the host computer 100 through the network cable 103, and the host computer 100 generates a second electrical signal according to the third electrical signal. The second electrical signal from the host computer 100 is transmitted to the optical module 200, and the optical module 200 converts the second electrical signal into a second optical signal, and transmits the second optical signal to the optical fiber 101, and the second optical signal is transmitted to the remote information processing device 1000 in the optical fiber 101. For example, the first optical signal from the remote information processing device 1000 is transmitted through the optical fiber 101, and the first optical signal from the optical fiber 101 is transmitted to the optical module 200, and the optical module 200 converts the first optical signal into a first electrical signal, and the optical module 200 transmits the first electrical signal to the host computer 100, and the host computer 100 generates a fourth electrical signal according to the first electrical signal, and transmits the fourth electrical signal to the local information processing device 2000. It should be noted that the optical module is a tool for realizing the mutual conversion between optical signals and electrical signals. During the conversion process between the optical signals and electrical signals, the information does not change, but the encoding and decoding methods of the information can change.

[0082] In addition to the optical network terminal, the host computer 100 also includes an optical line terminal (OLT), an optical network device (ONT), or a data center server.

[0083] Figure 4 1 is a partial structural diagram of a host computer according to some embodiments of the present application. In order to clearly show the connection relationship between the optical module 200 and the host computer 100, Figure 4 Only the structure of the host computer 100 related to the optical module 200 is shown. Figure 4 As shown, the host computer 100 further includes a PCB circuit board 105 disposed in the housing, a cage 106 disposed on the surface of the PCB circuit board 105, a heat sink 107 disposed on the cage 106, and an electrical connector disposed inside the cage 106. The electrical connector is configured to access the electrical port of the optical module 200; the heat sink 107 has a protruding structure such as fins to increase the heat dissipation area.

[0084] The optical module 200 is inserted into the cage 106 of the host computer 100, and the cage 106 fixes the optical module 200. The heat generated by the optical module 200 is transferred to the cage 106 and then diffused through the heat sink 107. After the optical module 200 is inserted into the cage 106, the electrical port of the optical module 200 is connected to the electrical connector inside the cage 106, so that the optical module 200 establishes a bidirectional electrical signal connection with the host computer 100. In addition, the optical port of the optical module 200 is connected to the optical fiber 101, so that the optical module 200 establishes a bidirectional optical signal connection with the optical fiber 101.

[0085] Figure 5 is a structural diagram of an optical module provided according to some embodiments of the present application, Figure 6 FIG. 1 is an exploded view of an optical module provided according to some embodiments of the present application. Figure 5 and Figure 6 As shown, the optical module 200 includes a shell, a circuit board 300 disposed in the shell, a tunable laser 900 , a coherent optical component 1100 and a DSP chip 1200 .

[0086] The housing comprises an upper housing 201 and a lower housing 202 . The upper housing 201 covers the lower housing 202 to form the housing having two openings 204 and 205 . The outer contour of the housing is generally a square body.

[0087] In some embodiments, the lower shell 202 includes a bottom plate 2021 and two lower side plates 2022 located on both sides of the bottom plate 2021 and arranged perpendicular to the bottom plate 2021; the upper shell 201 includes a cover plate 2011, and the cover plate 2011 covers the two lower side plates 2022 of the lower shell 202 to form the above-mentioned shell.

[0088] In some embodiments, the lower shell 202 includes a bottom plate 2021 and two lower side plates 2022 located on both sides of the bottom plate 2021 and vertically arranged with the bottom plate 2021; the upper shell 201 includes a cover plate 2011 and two upper side plates located on both sides of the cover plate 2011 and vertically arranged with the cover plate 2011, and the two upper side plates are combined with the two lower side plates 2022 to realize that the upper shell 201 covers the lower shell 202.

[0089] The direction of the line connecting the two openings 204 and 205 may be consistent with the length direction of the optical module 200, or may be inconsistent with the length direction of the optical module 200. For example, the opening 204 is located at the end of the optical module 200 ( Figure 5 The opening 205 is also located at the end of the optical module 200 ( Figure 5Alternatively, the opening 204 is located at the end of the optical module 200, and the opening 205 is located at the side of the optical module 200. The opening 204 is an electrical port, and the gold finger 301 of the circuit board 300 extends from the opening 204 and is inserted into the electrical connector of the host computer 100; the opening 205 is an optical port, which is configured to access the external optical fiber 101, so that the optical fiber 101 is connected to the tunable laser 900 and the coherent optical component 1100 in the optical module 200.

[0090] The upper housing 201 and the lower housing 202 are combined to facilitate the installation of the circuit board 300, the tunable laser 900, the coherent optical component 1100, etc. into the above housing, and the upper housing 201 and the lower housing 202 can encapsulate and protect the above components. In addition, when assembling the circuit board 300, the tunable laser 900, the coherent optical component 1100, etc., it is convenient to deploy the positioning components, heat dissipation components, and electromagnetic shielding components of these components, which is conducive to the automated production.

[0091] In some embodiments, the upper shell 201 and the lower shell 202 are made of metal materials to facilitate electromagnetic shielding and heat dissipation.

[0092] In some embodiments, the optical module 200 further includes an unlocking component 600 located outside its housing. The unlocking component 600 is configured to achieve a fixed connection between the optical module 200 and the host computer, or to release the fixed connection between the optical module 200 and the host computer.

[0093] For example, the unlocking component 600 is located on the outside of the two lower side plates 2022 of the lower housing 202, and includes a snap-fit ​​component that matches the cage 106 of the host computer 100. When the optical module 200 is inserted into the cage 106, the snap-fit ​​component of the unlocking component 600 fixes the optical module 200 in the cage 106; when the unlocking component 600 is pulled, the snap-fit ​​component of the unlocking component 600 moves accordingly, thereby changing the connection relationship between the snap-fit ​​component and the host computer, so as to release the fixation of the optical module 200 and the host computer, so that the optical module 200 can be pulled out of the cage 106.

[0094] The circuit board 300 includes circuit traces, electronic components and chips, etc. The electronic components and chips are connected according to the circuit design through the circuit traces to realize the functions of power supply, electrical signal transmission and grounding. The electronic components may include capacitors, resistors, transistors, metal-oxide-semiconductor field-effect transistors (Metal-Oxide-Semiconductor Field-Effect Transistor, MOSFET), etc. The chips may include microcontroller units (Microcontroller Unit, MCU), laser driver chips, transimpedance amplifiers (Transimpedance Amplifier, TIA), limiting amplifiers (Limiting amplifier), clock and data recovery chips (Clock and Data Recovery, CDR), power management chips, digital signal processing (Digital Signal Processing, DSP) chips.

[0095] The circuit board 300 is generally a rigid circuit board. Due to its relatively hard material, the rigid circuit board can also realize the load-bearing function. For example, the rigid circuit board can stably carry the above-mentioned electronic components and chips; the rigid circuit board can also be inserted into the electrical connector in the cage 106 of the host computer 100.

[0096] The circuit board 300 also includes a gold finger 301 formed on the end surface thereof. The gold finger 301 is composed of a plurality of independent pins. The circuit board 300 is inserted into the cage 106, and the gold finger 301 is connected to the electrical connector in the cage 106. The gold finger 301 can be provided on only one side of the circuit board 300 (e.g. Figure 4 The upper surface shown in the figure) can also be set on the upper and lower surfaces of the circuit board 300 to provide more pins, so as to adapt to occasions where the number of pins is large. The gold finger 301 is configured to establish an electrical connection with the host computer to achieve power supply, grounding, two-wire synchronous serial (Inter-Integrated Circuit, I2C) signal transmission, data signal transmission, etc. Of course, flexible circuit boards are also used in some optical modules. Flexible circuit boards are generally used in conjunction with rigid circuit boards to supplement rigid circuit boards.

[0097] Figure 7 FIG. 1 is an internal structure diagram of an optical module provided according to some embodiments of the present application. Figure 7As shown, in some embodiments, a tunable laser 900, a coherent optical component 1100 and a DSP chip 1200 are respectively provided on the surface of the circuit board 300. The coherent optical component 1100 includes a coherent optical modulator inside, and the coherent optical modulator is used to modulate the optical signal. Exemplarily, the coherent optical modulator is a silicon-based coherent optical modulator, a thin-film lithium niobate-based coherent optical modulator or a hybrid-based coherent optical modulator.

[0098] The tunable laser 900 is used as an external light source of the coherent light modulator. The tunable laser 900 emits light from the side, and the light it emits enters the coherent light modulator. Exemplarily, the tunable laser 900 can output light of different wavelengths.

[0099] The host computer transmits the electrical signal to the DSP chip 1200 through the gold finger 301. In some embodiments, the optical signal will be distorted during the transmission process of the optical fiber link. In the above embodiment of the present application, the DSP chip 1200 is used to counteract and compensate for the distortion, thereby reducing the impact of the distortion on the system bit error rate. The DSP chip 1200 can perform various signal compensation processes, such as chromatic dispersion compensation and polarization mode dispersion compensation. Exemplarily, the DSP chip 1200 converts the 16-channel PAM-4 electrical signal emitted by the host computer into four-channel transmitting end PAM-4 electrical signals, and the coherent optical modulator modulates the received four-channel PAM-4 electrical signal to the light emitted by the tunable laser 900, thereby generating a transmitting optical signal.

[0100] Figure 8 FIG. 1 is an exploded view of a coherent optical component provided according to some embodiments of the present disclosure. Figure 8 As shown, the coherent optical component 1100 may include a housing, which includes a base plate 1111 and a cover plate 1114 that are connected to each other from top to bottom.

[0101] Exemplarily, the substrate 1111 can be electrically connected to the circuit board 300 by means of solder balls or the like.

[0102] The coherent optical component 1100 may include an optical chip 1118. The optical chip 1118 has the function of modulating and demodulating optical signals.

[0103] Exemplarily, the optical chip 1118 may be a silicon optical chip, a lithium niobate chip, or a hybrid integrated optical chip.

[0104] The coherent optical component 1100 may include a first electrical chip 1112. The first electrical chip 1112 is disposed on one side of the optical chip 1118.

[0105] One end of the first electrical chip 1112 is point-connected to the optical chip 1118 , and the other end is electrically connected to the substrate 1111 .

[0106] Exemplarily, the first electrical chip 1112 may be a modulation driver chip.

[0107] In some embodiments of the present disclosure, the optical chip 1118 modulates the light to be modulated according to the electrical signal. Exemplarily, the electrical signal is loaded into the light to be modulated, thereby modulating it into an optical signal carrying data.

[0108] The optical chip 1118 has certain requirements on the amplitude of the received electrical signal, etc. Therefore, the electrical signal will be processed before entering the optical chip 1118. For this purpose, a modulation driving chip is also formed on the surface of the substrate 1111.

[0109] The modulation driving chip is disposed on one side of the optical chip 1118. The modulation driving chip is electrically connected to the optical chip 1118.

[0110] The modulation driver chip processes the electrical signal transmitted to the optical chip 1118 and increases the amplitude of the electrical signal to meet the requirements of the optical chip 1118. The electrical signal is then loaded onto the light to be modulated through the optical chip 1118 to generate an optical transmission signal carrying information.

[0111] For example, one end of the first electrical chip 1112 may be electrically connected to the optical chip 1118 by wire bonding, and the other end of the first electrical chip 1112 may be electrically connected to the substrate 1111 by wire bonding.

[0112] The coherent optical component 1100 may include a second electrical chip 1113. The second electrical chip 1113 is disposed on one side of the optical chip 1118.

[0113] One end of the second electrical chip 1113 is electrically connected to the optical chip 1118 , and the other end of the second electrical chip 1113 is electrically connected to the substrate 1111 .

[0114] Exemplarily, the second electrical chip 1113 may be a transimpedance amplifier chip.

[0115] The optical chip 1118 can demodulate the optical signal into an electrical signal, thereby realizing the demodulation of the optical signal.

[0116] In some embodiments, the electrical signal may be amplified by a transimpedance amplifier chip. To this end, a transimpedance amplifier chip is disposed on one side of the optical chip 1118 to amplify the demodulated electrical signal.

[0117] For example, one end of the second electrical chip 1113 may be electrically connected to the optical chip 1118 by wire bonding, and the other end of the second electrical chip 1113 may be electrically connected to the substrate 1111 by wire bonding.

[0118] In the present disclosure, the junction temperature allowed by the first electrical chip 1112 is lower than the junction temperature allowed by the optical chip 1118 , so the first electrical chip 1112 has a higher heat dissipation requirement than the optical chip 1118 .

[0119] In the present disclosure, the junction temperature allowed by the second electrical chip 1113 is lower than the junction temperature allowed by the optical chip 1118 , so the second electrical chip 1113 has a higher heat dissipation requirement than the optical chip 1118 .

[0120] In some embodiments, when the first electrical chip 1112 and the second electrical chip 1113 are arranged on the surface of the substrate 1111, the chip surface has a wire bonding pad, the area available for heat dissipation is small, and the chip is at a certain distance from the cover plate 1114. Due to the poor heat transfer performance of the air, a small part of the heat generated by the chip is dissipated to the outside through the cover plate 1114.

[0121] In some embodiments, based on the fact that the heat dissipation performance of the cover plate 1114 is better than that of the substrate 1111 , the first electrical chip 1112 and the second electrical chip 1113 can be disposed on the surface of the cover plate 1114 and then electrically connected to the circuit board 300 through an adapter plate.

[0122] In some embodiments, the coherent optical assembly 1100 can include a first thermal interface material 1115 .

[0123] The first thermal interface material 1115 is disposed between the first electrical chip and the top surface of the housing.

[0124] The first thermal interface material 1115 is disposed between the first electrical chip 1112 and the cover plate 1114. The first thermal interface material 1115 can increase the thermal conductivity between the first electrical chip 1112 and the cover plate 1114. The first thermal interface material 1115 has good thermal conductivity.

[0125] The first thermal interface material 1105 includes various heat dissipation materials such as heat dissipation gel, heat dissipation silicone grease, metal, solder, graphene, etc.

[0126] Exemplarily, the first thermal interface material 1115 transfers the heat generated by the first electrical chip 1112 upward to the surface of the cover plate 1114 .

[0127] In some embodiments, the coherent optical assembly 1100 can include a second thermal interface material 1116 .

[0128] The second thermal interface material 1116 is disposed between the second electrical chip and the top surface of the housing.

[0129] The second thermal interface material 1106 is disposed between the second electrical chip 1113 and the cover plate 1114. The second thermal interface material 1116 can increase the thermal conductivity between the second electrical chip 1113 and the cover plate 1114.

[0130] The second thermal interface material 1106 includes various heat dissipation materials such as heat dissipation gel, heat dissipation silicone grease, metal, solder, graphene, etc., and has good thermal conductivity.

[0131] Exemplarily, the second thermal interface material 1116 transfers the heat generated by the second electrical chip 1113 upward to the surface of the cover plate 1114 .

[0132] The chip package may include a thermal via 1117. Based on the thermal via 1117, heat can be transferred inside the package, and the heat generated by the first electrical chip 1112 is transferred to the second electrical chip 1113 and the side inside the package through the thermal via 1117, thereby expanding the heat dissipation path of the first electrical chip 1112.

[0133] Exemplarily, a portion of the heat generated by the first electrical chip 1112 is transferred upward to the outside via the first thermal interface material 1115 and the top surface of the housing. Another portion of the heat generated by the first electrical chip 1112 is transferred downward to the outside via the thermal conductive portion 1117, the second electrical chip 1113, the second thermal interface material 1116, and the top surface of the housing in sequence.

[0134] The material of the thermal conductive portion 1117 can be the same as that of the substrate 1111 , or can be a different material from that of the substrate 1111 .

[0135] The material of the thermal conductive portion 1117 may include metal, alloy, resin, graphene, ALN and other ceramics.

[0136] The thermal conductive portion 1117 may be disposed on the surface of the substrate 1101. The top surface of the thermal conductive portion 1117 is fixedly connected to the bottom surfaces of the first electrical chip 1112 and the second electrical chip 1113 respectively to support the first electrical chip 1112 and the second electrical chip 1113.

[0137] Exemplarily, a recess 1119 is formed on the surface of the substrate 1111, and the thermal conductive portion 1117 is embedded in the recess 1119 as an embedded structure. When the thermal conductive portion 1117 is an embedded structure, the thermal conductive portion 1117 can be located on the surface of the substrate 1111 or can penetrate multiple layers of the substrate 1101.

[0138] Exemplarily, the thermal conductive portion 1117 may be a layer of metal wiring of the substrate 1111. The metal wiring has the functions of heat dissipation and electrical interconnection.

[0139] The first electrical chip 1112 and the second electrical chip 1113 have higher heat dissipation requirements than the optical chip 1118. At the same time, since the heat dissipation performance of the substrate 1111 is poor and the substrate 1111 is soldered to the circuit board 300, the heat generated by the first electrical chip 1112 and the second electrical chip 1113 may cause thermal interference to other devices on the circuit board 300.

[0140] In some embodiments, the power density of the first electrical chip 1112 is greater than the power density of the second electrical chip 1113. Therefore, the heat generated by the first electrical chip 1112 is greater than the heat generated by the second electrical chip 1113, and the temperature of the first electrical chip 1112 is higher than the temperature of the second electrical chip 1113.

[0141] In some embodiments, the allowed junction temperature of the first electrical chip 1112 is lower than the allowed junction temperature of the second electrical chip 1113 .

[0142] The temperature of the first electrical chip 1112 is higher than that of the second electrical chip 1113. At the same time, the junction temperature allowed by the second electrical chip 1113 is higher than that allowed by the first electrical chip 1112. Therefore, the first electrical chip 1112 is the main heat source relative to the second electrical chip 1113, and the thermal interference caused by the first electrical chip 1112 to other devices on the circuit board 300 is relatively greater. Therefore, the first electrical chip 1112 has a higher heat dissipation requirement than the second electrical chip 1113.

[0143] In the present disclosure, in order to improve the heat dissipation performance of the first electric chip 1112 and meet the heat dissipation requirements of the first electric chip 1112, a thermal conductive portion 1117 is provided below the first electric chip 1112 and the second electric chip 1113 to transfer the heat generated by the first electric chip 1112 to the side of the second electric chip 1113 where the heat dissipation requirement is relatively low via the thermal conductive portion 1117, thereby expanding the heat dissipation path of the first electric chip 1112.

[0144] Since the temperature of the first electric chip 1112 is higher than that of the second electric chip 1113 , the heat generated by the first electric chip 1112 driven by the temperature difference is transferred to the second electric chip 1113 through the thermal conduction portion, and then transferred through the cover plate 1114 or the substrate 1111 .

[0145] The junction temperature allowed by the second electrical chip 1113 is higher than the junction temperature allowed by the first electrical chip 1112, which means that the second electrical chip 1113 can withstand a higher temperature. Therefore, when the heat generated by the second electrical chip 1113 is transferred to the second electrical chip 1113 through the thermal conductive portion 1117, the working performance of the second electrical chip 1113 is less affected. This also provides feasibility for heat transfer inside the package.

[0146] In some embodiments, a portion of the heat generated by the first electric chip 1112 is transferred upward to the cover plate 1114 or the substrate 1111 via the first thermal interface material 1115, and then transferred to the outside; another portion of the heat generated by the first electric chip 1112 is transferred downward to the thermal conductive portion 1117, and then the heat is laterally transmitted along the inside of the thermal conductive portion 1117 to the side of the second electric chip 1113, and then transferred upward through the second thermal interface material 1116, the cover plate 1114 or the substrate 1111.

[0147] In the present disclosure, heat transfer in the cavity is achieved by setting a thermal conduction part 1117 below the first electric chip 1112 and the second electric chip 1113, and the heat generated by the first electric chip 1112 can be transferred inside the package. The heat generated by the first electric chip 1112 is transferred to the second electric chip 1113 side inside the package through the thermal conduction part 1117, and then the heat is transferred to the outside through the cover plate 1114 or the substrate 1111, which expands the heat dissipation channel and heat dissipation path of the first electric chip 1112, thereby expanding the effective heat dissipation area of ​​the cover plate 1114 or the substrate 1111, greatly improving the heat dissipation capacity, thereby ensuring the working performance of the first electric chip 1112, and reducing the thermal interference to other devices on the surface of the circuit board 300.

[0148] Fig. 9 FIG. 1 is a partial structural diagram of a coherent optical component provided according to some embodiments of the present disclosure. Fig. 9 As shown, the surface of the thermal conductive portion 1117 is provided with a first electrical chip 1112 and a second electrical chip 1113 respectively.

[0149] A first thermal interface material 1115 is disposed above the first electrical chip 1112 .

[0150] A second thermal interface material 1116 is disposed above the second electrical chip 1113 .

[0151] A first thermal interface material 1115 and a first electrical chip 1112 are respectively disposed at upper and lower positions of one end of the thermal conductive portion 1117 .

[0152] A second thermal interface material 1116 and a second electrical chip 1113 are respectively disposed at the upper and lower positions of the other end of the thermal conductive portion 1117 .

[0153] The heat generated by the first electric chip 1112 can be transferred inside the package. The heat generated by the first electric chip 1112 is transferred to the second electric chip 1113 side inside the package through the thermal conduction part 1117, and then the heat is transferred to the outside through the cover plate 1114 or the substrate 1111, thereby expanding the heat dissipation channel and heat dissipation path of the first electric chip 1112, greatly improving the heat dissipation capacity, thereby ensuring the working performance of the first electric chip 1112, and reducing thermal interference to other devices on the surface of the circuit board 300.

[0154] Fig.10 FIG. 1 is a partial cross-sectional view of a coherent optical component provided according to some embodiments of the present disclosure. Fig.10 As shown, the coherent optical component 1100 includes a substrate 1111 and a cover 1114 which are overlapped with each other.

[0155] A thermal conductive portion 1117 may be provided on the surface of the substrate 1111 .

[0156] One end of the thermal conductive portion 1117 is provided with a first electrical chip 1112 and a first thermal interface material 1115 from bottom to top.

[0157] One end of the thermal conductive portion 1117 is provided with a second electrical chip 1113 and a second thermal interface material 1116 from bottom to top.

[0158] The first thermal interface material 1115 can increase the thermal conductivity between the first electrical chip 1112 and the cover plate 1114 .

[0159] The second thermal interface material 1116 can increase the thermal conductivity between the second electrical chip 1113 and the cover plate 1114 .

[0160] The heat transfer in the cavity can be realized through the thermal conductive part 1117. The heat generated by the first electric chip 1112 can be transferred inside the package. The heat generated by the first electric chip 1112 is transferred to the second electric chip 1113 side inside the package through the thermal conductive part 1117, and then the heat is transferred to the outside through the cover plate 1114 or the substrate 1111, thereby expanding the heat dissipation channel and heat dissipation path of the first electric chip 1112.

[0161] Fig.11 A partial exploded view of a coherent optical component provided according to some embodiments of the present disclosure. Fig.12 FIG. 1 is a schematic diagram of chip heat dissipation of a coherent optical component according to some embodiments of the present disclosure. Fig.11 and Fig.12 As shown, a portion of the heat generated by the first electric chip 1112 is transferred upward to the cover plate 1114 or the substrate 1111 via the first thermal interface material 1115, and then transferred to the outside; another portion of the heat generated by the first electric chip 1112 is transferred downward to the thermal conductive portion 1117, and then the heat is laterally transmitted along the inside of the thermal conductive portion 1117 to the side of the second electric chip 1113, and then transferred upward through the second thermal interface material 1116, the cover plate 1114 or the substrate 1111.

[0162] In the present disclosure, a thermal conductive portion is provided to achieve internal heat transfer within the package, thereby expanding the heat dissipation channels and heat dissipation paths of chips with higher heat dissipation requirements. This increases the effective heat dissipation area of ​​the cover plate or substrate, greatly improving the heat dissipation capacity, and thereby ensuring the working performance of chips with higher heat dissipation requirements.

[0163] The above is only a specific embodiment of the present disclosure, but the protection scope of the present disclosure is not limited thereto. Any changes or substitutions that can be thought of by any person skilled in the art within the technical scope disclosed in the present disclosure should be included in the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure should be based on the protection scope of the claims.

Claims

1. A chip package, characterized in that: include: substrate; A cover plate, connected to the base plate to form a cavity; A first chip is disposed in the cavity, and a portion of heat generated by the first chip is transferred to the outside via the cover plate or the substrate; a second chip, disposed in the cavity, wherein heat generated by the second chip is transferred to the outside via the cover plate or the substrate; wherein the power density of the second chip is less than the power density of the first chip, and the junction temperature allowed by the second chip is higher than the junction temperature allowed by the first chip; A heat conducting portion, the bottom surface of which is disposed on the surface of the substrate, and the top surface of which supports the first chip and the second chip respectively; Another part of the heat generated by the first chip is transferred to the second chip via the thermal conduction portion, and then transferred to the outside via the cover plate or the substrate.

2. The chip package according to claim 1, characterized in that: A first thermal interface material is disposed between the first chip and the cover plate, and a second thermal interface material is disposed between the second chip and the cover plate; A portion of the heat generated by the first chip is transferred upward to the outside via the first thermal interface material, the cover plate or the substrate; Another part of the heat generated by the first chip is transferred downward to the outside via the thermal conductive portion, the second chip, the second thermal interface material, the cover plate or the substrate in sequence.

3. The chip package according to claim 1, characterized in that: A recessed portion is formed on the surface of the substrate, and the heat conducting portion is embedded in the recessed portion.

4. The chip package according to claim 1, characterized in that: The substrate surface has a metal trace, and the metal trace is configured as the thermal conduction portion.

5. The chip package according to claim 1, characterized in that: The first chip is configured as an electrical chip or an optical chip, and the second chip is configured as an electrical chip or an optical chip.

6. An optical module, characterized in that: include: Circuit boards; A coherent optical component is electrically connected to the circuit board, and the coherent optical component comprises: A housing, wherein the housing is provided with: Optical chips, used to modulate and demodulate optical signals; A first electrical chip is disposed on one side of the optical chip, wherein the junction temperature allowed by the first electrical chip is lower than the junction temperature allowed by the optical chip; a part of the heat generated by the first electrical chip is transferred to the outside through the housing; a second electric chip disposed on one side of the optical chip, wherein the junction temperature allowed by the second electric chip is lower than the junction temperature allowed by the optical chip; the heat generated by the second electric chip is transferred to the outside via the housing; and the power density of the second electric chip is lower than the power density of the first electric chip; A thermal conductive portion, used for supporting the first electrical chip and the second electrical chip; Another part of the heat generated by the first electric chip is transferred to the second electric chip via the thermal conduction portion, and then transferred to the outside via the housing.

7. The optical module according to claim 6, characterized in that: A first thermal interface material is disposed between the first electric chip and the top surface of the housing, and a second thermal interface material is disposed between the second electric chip and the top surface of the housing; A portion of the heat generated by the first electric chip is transferred upward to the outside via the first thermal interface material and the top surface of the housing; Another part of the heat generated by the first electric chip is transferred downward to the outside via the thermal conductive portion, the second electric chip, the second thermal interface material, and the top surface of the housing in sequence.

8. The optical module according to claim 6, characterized in that: The housing comprises a cover plate and a base plate which are connected in a covering manner; A recessed portion is provided on the surface of the substrate, and the heat conducting portion is arranged in the recessed portion.

9. The optical module according to claim 6, characterized in that: The housing comprises a cover plate and a base plate which are connected in a covering manner; One end of the first electrical chip is electrically connected to the optical chip, and the other end is electrically connected to the substrate; One end of the second electrical chip is electrically connected to the optical chip, and the other end of the second electrical chip is electrically connected to the substrate.

10. The optical module according to claim 6, characterized in that: The first electric chip is a modulation driving chip, and the second electric chip is a transimpedance amplifier.

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