A frequency switchable oscillator circuit
By introducing charging current change, charging capacitor change and pulse width adjustment feedback circuit into the oscillator circuit, the control potential can be used to achieve switching and fine-tuning of the oscillator frequency, the problem of inflexibility of traditional oscillator frequency is solved, and the accuracy and integration of the circuit are improved.
Patent Information
- Application Number
- CN202421512849.2
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-06-28
- Publication Date
- 2025-04-08
- Estimated Expiration
- 2034-06-28
AI Technical Summary
Traditional oscillators can only achieve a single oscillation frequency and cannot switch frequency. The output frequency is unstable due to process fluctuations, which limits its flexibility and adjustability in practical applications.
A frequency switchable oscillator circuit is designed, including a charging current change circuit, a charging capacitor change circuit and a pulse width adjustment feedback circuit, and the oscillation frequency can be switched or fine-tuned by inputting control potential.
It realizes flexible switching and fine-tuning of the oscillation frequency, simplifies circuit design, reduces costs, and improves oscillation accuracy and circuit integration and reliability.
Smart Images
Figure CN222736121U_ABST
Abstract
Description
Technical Field
[0001] The utility model belongs to the technical field of electronic circuits, in particular to an oscillator circuit with switchable frequency. Background Art
[0002] An oscillator is a circuit or device used to generate a continuous periodic signal. In some special application scenarios, the operating frequency needs to be continuously switched to meet user needs. Traditional ordinary oscillators can usually only achieve a single oscillation frequency and cannot achieve frequency switching. In addition, when affected by factors such as process fluctuations, the output frequency will also change greatly and cannot be effectively calibrated. These problems limit the flexibility and adjustability of oscillators in practical applications. At present, in order to achieve the switching of oscillator frequency, a common solution is to adopt a multi-oscillator structure to change the output frequency by switching different oscillator circuits. This solution requires adding multiple independent oscillator units to the oscillator circuit, which not only increases the complexity and cost of the circuit, but also is not conducive to the trend of miniaturization of electronic products. Utility Model Content
[0003] The purpose of the utility model is to provide an oscillator circuit with switchable frequency, which can realize the switching of oscillation frequency or fine-tuning of oscillation frequency by inputting control potential, thereby ensuring oscillation accuracy and improving circuit integration and reliability.
[0004] In order to achieve the above-mentioned purpose, the technical methods adopted by the utility model are as follows:
[0005] A frequency-switchable oscillator circuit comprises a charging current changing circuit, a charging capacitance changing circuit and a pulse width modulation feedback circuit. The charging current changing circuit comprises a current adjustment branch. When the charging current needs to be reduced, the current adjustment branch shunts the constant current. When the charging current needs to be increased, the current adjustment branch is used to provide branch current, thereby increasing the charging current. The charging capacitance changing circuit comprises a main charging capacitor, which is connected in parallel with an auxiliary capacitor controlled by a controlled potential. The pulse width modulation feedback circuit comprises an inverter, a capacitor is provided at the output end of the inverter, and the pulse width is changed by changing the size of the capacitor. The output end of the charging current changing circuit is connected to the input end of the charging capacitance changing circuit, the output end of the charging capacitance changing circuit is connected to the input end of the pulse width modulation feedback circuit, the output end of the pulse width modulation feedback circuit outputs a clock signal, and the feedback output end of the pulse width modulation feedback circuit is connected to the feedback input end of the charging capacitance changing circuit.
[0006] As a limitation: the charging current changing circuit also includes a current source, a first MOS tube, a second MOS tube, a fifth MOS tube and a sixth MOS tube, one end of the current source is connected to the input voltage source, the other end of the current source is connected to the drain of the first MOS tube, the source of the first MOS tube is grounded, the gate of the first MOS tube is respectively connected to the drain of the first MOS tube and the gate of the second MOS tube, the source of the second MOS tube is grounded, the drain of the second MOS tube is connected to the drain of the fifth MOS tube, the gate of the fifth MOS tube is respectively connected to the drain of the fifth MOS tube and the gate of the sixth MOS tube, the source of the fifth MOS tube and the source of the sixth MOS tube are both connected to the input voltage source, and the drain of the sixth MOS tube is connected to the input end of the charging capacitance changing circuit; when it is necessary to reduce When the charging current is increased, the current adjustment branch includes a third MOS tube and a fourth MOS tube, the gate of the third MOS tube is a control potential input terminal, the source of the third MOS tube is connected to the input voltage source, the drain of the third MOS tube is connected to the source of the fourth MOS tube, and the drain of the fourth MOS tube is respectively connected to the gate of the fourth MOS tube and the drain of the fifth MOS tube; when the charging current needs to be increased, the current adjustment branch includes a twelfth MOS tube and a thirteenth MOS tube, the gate of the twelfth MOS tube is a control potential input terminal, the source of the twelfth MOS tube is grounded, the drain of the twelfth MOS tube is connected to the source of the thirteenth MOS tube, the drain of the thirteenth MOS tube is connected to the drain of the second MOS tube, and the gate of the thirteenth MOS tube is connected to the gate of the second MOS tube.
[0007] As a limitation: the charging capacitance changing circuit includes a seventh MOS tube, an eighth MOS tube, a ninth MOS tube, a tenth MOS tube, an eleventh MOS tube, a first capacitor and a second capacitor, the first capacitor serves as a main charging capacitor, the second capacitor serves as an auxiliary capacitor, the source of the seventh MOS tube is grounded, the gate of the seventh MOS tube is connected to the feedback output end of the pulse width modulation feedback circuit, the drain of the seventh MOS tube is respectively connected to the output end of the charging current changing circuit, one end of the first capacitor, the drain of the eighth MOS tube, the source of the tenth MOS tube and the gate of the eleventh MOS tube, the other end of the first capacitor is grounded, the source of the eighth MOS tube is respectively connected to the drain of the ninth MOS tube, the drain of the tenth MOS tube and one end of the second capacitor, the source of the ninth MOS tube is grounded, the gates of the eighth MOS tube, the ninth MOS tube and the tenth MOS tube are all control potential input ends, the drain of the tenth MOS tube is connected to one end of the second capacitor, the other end of the second capacitor is grounded, the source of the eleventh MOS tube is grounded, and the drain of the eleventh MOS tube is respectively connected to the input voltage source and the input end of the pulse width modulation feedback circuit.
[0008] As a limitation: the pulse width modulation feedback circuit includes a first inverter, a second inverter, a third inverter, a fourth inverter, a fifth inverter, a sixth inverter, a seventh inverter, an eighth inverter, a ninth inverter, a tenth inverter, an eleventh inverter, a first NAND gate, a second NAND gate and a third capacitor, the input end of the first inverter is respectively connected to the input voltage source and the output end of the charging capacitor changing circuit, the output end of the first inverter is connected to the input end of the second inverter, the output end of the second inverter is respectively connected to the input end of the third inverter and the second input end of the second NAND gate, the output end of the third inverter is connected to the first input end of the first NAND gate, the output end of the first NAND gate is respectively connected to the input end of the fourth inverter and the input end of the sixth inverter, and the fourth inverter The output end of the phase inverter is connected to the input end of the fifth inverter, the output end of the fifth inverter serves as the output end of the pulse width modulation feedback circuit to output the clock signal, the output end of the sixth inverter is connected to the input end of the seventh inverter, the output end of the seventh inverter is respectively connected to the input end of the eighth inverter and one end of the third capacitor, the output end of the eighth inverter is connected to the input end of the ninth inverter, the output end of the ninth inverter is connected to the first input end of the second NAND gate, the output end of the second NAND gate is respectively connected to the second input end of the first NAND gate and the input end of the tenth inverter, the output end of the tenth inverter is connected to the input end of the eleventh inverter, and the output end of the eleventh inverter is connected to the feedback input end of the charging capacitor changing circuit as the feedback output end of the pulse width modulation feedback circuit.
[0009] Due to the adoption of the above solution, the utility model has the following beneficial effects compared with the prior art:
[0010] The utility model provides a frequency-switchable oscillator circuit, which is provided with a charging current changing circuit, a charging capacitor changing circuit and a pulse width modulation feedback circuit. By inputting a control potential, the oscillation frequency can be switched or the oscillation frequency can be fine-tuned, which simplifies the circuit design and does not require an external redundant oscillator. While ensuring the oscillation accuracy, the cost is saved. The oscillator circuit of the utility model has a simple structure, does not require a comparator, has low power consumption, and reduces the chip area. It is used in scenarios where the oscillation frequency needs to be switched, which improves the integration of the circuit, can integrate more functions on the same chip, reduces the complexity of the system, and improves the integration and reliability of the circuit.
[0011] The utility model is suitable for switching or fine-tuning the oscillation frequency. BRIEF DESCRIPTION OF THE DRAWINGS
[0012] The present invention is described in further detail below in conjunction with the accompanying drawings and specific embodiments.
[0013] Figure 1 This is a structural block diagram of a frequency-switchable oscillator circuit according to an embodiment of the utility model;
[0014] Figure 2 A circuit schematic diagram of a charging current changing circuit when the charging current needs to be reduced in an embodiment of the utility model;
[0015] Figure 3 A circuit schematic diagram of a charging current changing circuit when the charging current needs to be increased in an embodiment of the utility model;
[0016] Figure 4 This is a circuit schematic diagram of a charging capacitor changing circuit according to an embodiment of the utility model;
[0017] Figure 5 This is a circuit schematic diagram of a pulse width modulation feedback circuit according to an embodiment of the utility model;
[0018] Figure 6 This is a circuit schematic diagram of a frequency-switchable oscillator circuit according to an embodiment of the utility model;
[0019] Figure 7 The clock signal output by the oscillator circuit when the control potential SWP is at a high level in the embodiment of the utility model;
[0020] Figure 8 It is the clock signal output by the oscillator circuit when the control potential SWP is at a low level in the embodiment of the utility model. DETAILED DESCRIPTION
[0021] The present invention is further described below in conjunction with embodiments. However, those skilled in the art should understand that the present invention is not limited to the following embodiments, and any improvements and equivalent changes made based on the specific embodiments of the present invention are within the scope of protection of the claims of the present invention.
[0022] Embodiment A frequency switchable oscillator circuit
[0023] A frequency switchable oscillator circuit, the structural block diagram of which is shown in FIG. Figure 1 As shown, it includes a charging current changing circuit, a charging capacitor changing circuit and a pulse width adjustment feedback circuit. The charging current changing circuit includes a current adjustment branch. When the charging current needs to be reduced, the current adjustment branch shunts the constant current. If the charging current needs to be further reduced, multiple current adjustment branches can be connected in parallel; when the charging current needs to be increased, the current adjustment branch is used to provide branch current, thereby increasing the charging current. If the charging current needs to be further increased, multiple current adjustment branches can be connected in parallel. The output end of the charging current changing circuit is connected to the input end of the charging capacitor changing circuit, the output end of the charging capacitor changing circuit is connected to the input end of the pulse width adjustment feedback circuit, the output end of the pulse width adjustment feedback circuit outputs a clock signal, and the feedback output end of the pulse width adjustment feedback circuit is connected to the feedback input end of the charging capacitor changing circuit.
[0024] The circuit schematic diagram of the charging current changing circuit in this embodiment is as follows: Figure 2 As shown, the charging current changing circuit also includes a current source, a first MOS tube M1, a second MOS tube M2, a fifth MOS tube M5, a sixth MOS tube M6 and a current adjustment branch. One end of the current source is connected to the input voltage source, and the other end of the current source is connected to the drain of the first MOS tube M1. The source of the first MOS tube M1 is grounded, and the gate of the first MOS tube M1 is respectively connected to the drain of the first MOS tube M1 and the gate of the second MOS tube M2. The source of the second MOS tube M2 is grounded, and the drain of the second MOS tube M2 is connected to the drain of the fifth MOS tube M5. The gate of the fifth MOS tube M5 is respectively connected to the drain of the fifth MOS tube M5 and the gate of the sixth MOS tube M6. The source of the fifth MOS tube M5 and the source of the sixth MOS tube M6 are both connected to the input voltage source, and the drain of the sixth MOS tube M6 is connected to the input end of the charging capacitance changing circuit; when the charging current needs to be reduced, the current adjustment branch includes the third MOS tube M3 and the fourth MOS tube M4, the gate of the third MOS tube M3 is the control potential input end, the source of the third MOS tube M3 is connected to the input voltage source, the drain of the third MOS tube M3 is connected to the source of the fourth MOS tube M4, and the drain of the fourth MOS tube M4 is respectively connected to the gate of the fourth MOS tube M4 and the drain of the fifth MOS tube M5; when the charging current needs to be increased, the circuit principle diagram of the charging current changing circuit is as shown in Figure 3 As shown, the current adjustment branch includes a twelfth MOS tube M12 and a thirteenth MOS tube M13, the gate of the twelfth MOS tube M12 is the control potential input terminal, the source of the twelfth MOS tube M12 is grounded, the drain of the twelfth MOS tube M12 is connected to the source of the thirteenth MOS tube M13, the drain of the thirteenth MOS tube M13 is connected to the drain of the second MOS tube M2, and the gate of the thirteenth MOS tube M13 is connected to the gate of the second MOS tube M2.
[0025] The working principle of the charging current changing circuit is as follows: when the charging current needs to be reduced, the current source provides the current IBIAS as the current source of the oscillator, first biases the first MOS tube M1, sets the second MOS tube M2 to have the same width-to-length ratio as the first MOS tube M1, the second MOS tube M2 mirrors the current of the first MOS tube M1, the current of the branch formed by the third MOS tube M3 and the fourth MOS tube M4 is I3, the current of the branch of the fifth MOS tube M5 is I5, the total current of the two branches is the current I2 of the second MOS tube M2, sets the sixth MOS tube M6 to have the same width-to-length ratio as the fifth MOS tube M5, the sixth MOS tube M6 mirrors the current of the fifth MOS tube M5, the current of the sixth MOS tube M6 is the charging current I6, so the current of the second MOS tube M2 is drawn away by introducing the branch formed by the third MOS tube M3 and the fourth MOS tube M4 to reduce the charging current I6, that is, I2=I3+I5=I3+I6. The control potential of the gate of the third MOS tube M3 is SWP. When SWP is at a high level, the branch formed by the third MOS tube M3 and the fourth MOS tube M4 does not draw the current of the second MOS tube M2. At this time, I3=0, I2=I5=I6; when SWP is at a low level, the third MOS tube M3 is turned on, and the branch formed by the third MOS tube M3 and the fourth MOS tube M4 draws the current of the second MOS tube M2. At this time, I3≠0, I2>I5, I5=I6, so the charging current I6 is reduced. The change of the charging current is achieved by introducing the control potential of the gate of the third MOS tube M3, so that the oscillation frequency of the oscillator can be changed. When it is necessary to further reduce the charging current, multiple control potentials can be added, that is, multiple branches formed by the third MOS tube M3 and the fourth MOS tube M4 are connected in parallel. When the charging current needs to be increased, the branch formed by the twelfth MOS tube M12 and the thirteenth MOS tube M13 provides the branch current, the current of the branch formed by the twelfth MOS tube M12 and the thirteenth MOS tube is I1, and the control potential of the gate of the thirteenth MOS tube M13 is SW. When SW is at a low level, the twelfth MOS tube M12 is turned off, at this time, I1=0, I2=I5=I6; when SW is at a high level, the twelfth MOS tube M12 is turned on, at this time, I5=I6=I2+I1, so the charging current increases. When the charging current needs to be further increased, multiple control potentials can be added, that is, multiple branches formed by the twelfth MOS tube M12 and the thirteenth MOS tube M13 are connected in parallel.
[0026] The circuit diagram of the charging capacitor changing circuit is as follows Figure 4As shown, the charging capacitance changing circuit includes a seventh MOS tube M7, an eighth MOS tube M8, a ninth MOS tube M9, a tenth MOS tube M10, an eleventh MOS tube M11, a first capacitor C1 and a second capacitor C2, the first capacitor C1 is used as a main charging capacitor, the second capacitor C2 is used as an auxiliary capacitor, the source of the seventh MOS tube M7 is grounded, the gate of the seventh MOS tube M7 is connected to the feedback output end of the pulse width modulation feedback circuit, and the drain of the seventh MOS tube M7 is respectively connected to the output end of the charging current changing circuit, one end of the first capacitor C1, the drain of the eighth MOS tube M8, the source of the tenth MOS tube M10 and the gate of the eleventh MOS tube M11. The gate of the eighth MOS tube M8, the gate of the ninth MOS tube M9 and the gate of the tenth MOS tube M10 are all control potential input terminals, the drain of the tenth MOS tube M10 is connected to one end of the second capacitor C2, the other end of the second capacitor C2 is grounded, the source of the eleventh MOS tube M11 is grounded, and the drain of the eleventh MOS tube M11 is respectively connected to the input voltage source and the input terminal of the pulse width modulation feedback circuit.
[0027] The working principle of the charging capacitor change circuit is as follows: the first capacitor C1 is used as the main charging capacitor, and the second capacitor C2 controlled by the control potential is connected in parallel. The second capacitor C2 is used as an auxiliary capacitor to achieve the change of capacitance. When the oscillation frequency needs to be changed, the charging path of the auxiliary capacitor can be opened. In order to ensure the charging consistency under different voltages VCAP, the control of the auxiliary capacitor adopts a transmission gate. At the same time, the control potential of the ninth MOS tube M9 is added to reduce the influence of the auxiliary capacitor on the main charging capacitor when it is turned off. The charging current charges the first capacitor C1, and the voltage VCAP increases. VEB is the feedback voltage output by the pulse width regulation feedback circuit. When the feedback voltage VFB is less than the turn-on voltage of the seventh MOS tube M7, the voltage VCAP is charged; when the feedback voltage VFB is greater than the turn-on voltage of the seventh MOS tube M7, the voltage VCAP is discharged. When the voltage VCAP is greater than the turn-on voltage of the eleventh MOS tube M11, the eleventh MOS tube M11 is turned on, the drain voltage of the eleventh MOS tube M11 is pulled down, and the input of the pulse width modulation feedback circuit is low level; when the voltage VCAP is less than the turn-on voltage of the eleventh MOS tube M11, the eleventh MOS tube M11 is turned off, the drain voltage of the eleventh MOS tube M11 is the voltage VIN of the input voltage source, and the input of the pulse width modulation feedback circuit is high level. The eighth MOS tube M8 and the tenth MOS tube M10 form a transmission gate, the control potential of the gate of the eighth MOS tube M8 is SWN, the control potential of the gate of the tenth MOS tube M10 is SWP, SWN is the negation of SWP, so when SWP is low level, the transmission gate is turned on, and the charging capacitance C of the entire charging capacitance changing circuit is C=C1+C2; when SWP is high level, the transmission gate is turned off, and the charging capacitance C of the entire charging capacitance changing circuit is C=C1. The transmission gate is selected as the control switch of the second capacitor C2 here because the resistance of the transmission gate when it is turned on is almost a constant value under different voltages VCAP, which can ensure the charging performance of the second capacitor C2. When SWP is at a high level, the transmission gate is turned off. In order for the second capacitor C2 not to act on the charging capacitor of the entire charging capacitor change circuit, the ninth MOS tube M9 is added to further short-circuit the second capacitor C2. The control potential of the gate of the ninth MOS tube M9 is SWP. When SWP is at a high level, the charging capacitor C of the entire charging capacitor change circuit is C=C1; when SWP is at a low level, the charging capacitor C of the entire charging capacitor change circuit is C=C1+C2. When the opposite control logic needs to be implemented, the control potential of the gate of the eighth MOS tube M8 can be changed to SWP, and the control potential of the gates of the ninth MOS tube M9 and the tenth MOS tube M10 can be changed to SWN.
[0028] The circuit diagram of the pulse width modulation feedback circuit is as follows Figure 5As shown, the pulse width modulation feedback circuit includes a first inverter INV1, a second inverter INV2, a third inverter INV3, a fourth inverter INV4, a fifth inverter INV5, a sixth inverter INV6, a seventh inverter INV7, an eighth inverter INV8, a ninth inverter INV9, a tenth inverter INV10, an eleventh inverter INV11, a first NAND gate NAND1, a second NAND gate NAND2 and a third capacitor C3, and the input terminals of the first inverter INV1 are respectively connected to the input terminals of the first inverter INV1. The input voltage source is connected to the output end of the charging capacitor changing circuit, the output end of the first inverter INV1 is connected to the input end of the second inverter INV2, the output end of the second inverter INV2 is respectively connected to the input end of the third inverter INV3 and the second input end of the second NAND gate NAND2, the output end of the third inverter INV3 is connected to the first input end of the first NAND gate NAND1, the output end of the first NAND gate NAND1 is respectively connected to the input end of the fourth inverter INV4 and the input end of the sixth inverter INV 6, the output end of the fourth inverter INV4 is connected to the input end of the fifth inverter INV5, the output end of the fifth inverter INV5 serves as the output end of the pulse width modulation feedback circuit to output the clock signal CLK, the output end of the sixth inverter INV6 is connected to the input end of the seventh inverter INV7, the output end of the seventh inverter INV7 is respectively connected to the input end of the eighth inverter INV8 and one end of the third capacitor C3, the output end of the eighth inverter INV8 is connected to the input end of the ninth inverter INV9, the output end of the ninth inverter INV9 is connected to the first input end of the second NAND gate NAND2, the output end of the second NAND gate NAND2 is respectively connected to the second input end of the first NAND gate NAND1 and the input end of the tenth inverter INV10, the output end of the tenth inverter INV10 is connected to the input end of the eleventh inverter INV11, and the output end of the eleventh inverter INV11 is connected to the feedback input end of the charging capacitor changing circuit as the feedback output end of the pulse width modulation feedback circuit.
[0029] The working principle of the pulse width modulation feedback circuit is: when the inverter is in level reversal, it is necessary to charge the capacitor at its output end. According to this principle, a third capacitor C3 is set at the output end of the seventh inverter INV7, and the pulse width is changed by changing the size of the third capacitor C3. In order to achieve oscillation, it is necessary to feed back the high and low levels of the output to the charging capacitor changing circuit, and charge or discharge the charging capacitor to change the voltage thereon. When the input end of the first inverter INV1 is high level, the output of the second inverter INV2 is high level, that is, the input of the second input end of the second NAND gate NAND2 is high level, and the input of the first input end of the first NAND gate NAND1 is low level, so the output of the first NAND gate NAND1 is high level, at this time, the clock signal output by the fifth inverter INV5 is high level, and the input of the first input end of the second NAND gate NAND2 is high level, so the output of the second NAND gate NAND2 is low level, and the feedback voltage VFB output by the eleventh inverter INV11 is low level. The feedback voltage VFB is fed back to the charging capacitor changing circuit, and the capacitor continues to be charged, and the voltage VCAP continues to rise. When the voltage VCAP is greater than the turn-on voltage of the eleventh MOS tube M11, the drain voltage of the eleventh MOS tube M11 is pulled down to a low level, so the input of the first inverter INV1 is a low level, and the output of the second inverter INV2 is a low level, that is, the input of the second input end of the second NAND gate NAND2 is a low level, the output of the second NAND gate NAND2 is a high level, the input of the second input end of the first NAND gate NAND1 is a high level, the input of the first input end of the first NAND gate NAND1 is a high level, and the output of the first NAND gate NAND1 is a low level. At this time, the clock signal output by the fifth inverter INV5 is a low level. Because the output of the second NAND gate NAND2 is a high level, the feedback voltage VFB is a high level, and the feedback voltage VFB is fed back to the charging capacitor changing circuit, so that the capacitor is discharged, and the voltage VCAP drops until the voltage VCAP is less than the turn-on voltage of the eleventh MOS tube M11.
[0030] The circuit schematic diagram of the frequency switchable oscillator circuit of this embodiment is as follows: Figure 6 As shown, the current adjustment branch is the current adjustment branch when the charging current needs to be reduced, and the relationship between the voltage VCAP on the capacitor, the current I and the capacitance value C is: ：
[0031]
[0032] When SWP is high and SWN is low, the charging current I6 = I2 = IBIAS, the charging capacitor C = C1, and the output clock signal CLK is as follows: Figure 7As shown in the figure, when SWP is low and SWN is high, the charging current I6<I2=IBIAS, the charging capacitor C=C1+C2, and the output clock signal CLK is as follows: Figure 8 As shown in the figure, the comparison of the clock signal CLK output when the control SWP is set to high level and low level, it can be seen that the output frequency of the oscillator is different when the control potential is different. When SWP is high level and SWN is low level, the output clock signal CLK frequency is faster, and when SWP is low level and SWN is high level, the output clock signal CLK frequency is slower. If the oscillation frequency of the oscillator needs to be fine-tuned, only a slight change in the charging current and charging capacitance is required.
Claims
1. A frequency switchable oscillator circuit, characterized in that: It includes a charging current changing circuit, a charging capacitance changing circuit and a pulse width adjustment feedback circuit. The charging current changing circuit includes a current adjustment branch. When the charging current needs to be reduced, the current adjustment branch shunts the constant current. When the charging current needs to be increased, the current adjustment branch is used to provide branch current, thereby increasing the charging current. The charging capacitance changing circuit includes a main charging capacitor, and the main charging capacitor is connected in parallel with an auxiliary capacitor controlled by a control potential. The pulse width adjustment feedback circuit includes an inverter, and a capacitor is provided at the output end of the inverter. The pulse width is changed by changing the size of the capacitor. The output end of the charging current changing circuit is connected to the input end of the charging capacitor changing circuit, the output end of the charging capacitor changing circuit is connected to the input end of the pulse width modulation feedback circuit, the output end of the pulse width modulation feedback circuit outputs a clock signal, and the feedback output end of the pulse width modulation feedback circuit is connected to the feedback input end of the charging capacitor changing circuit.
2. A frequency switchable oscillator circuit according to claim 1, characterized in that: The charging current changing circuit also includes a current source, a first MOS tube, a second MOS tube, a fifth MOS tube and a sixth MOS tube, one end of the current source is connected to the input voltage source, the other end of the current source is connected to the drain of the first MOS tube, the source of the first MOS tube is grounded, the gate of the first MOS tube is respectively connected to the drain of the first MOS tube and the gate of the second MOS tube, the source of the second MOS tube is grounded, the drain of the second MOS tube is connected to the drain of the fifth MOS tube, the gate of the fifth MOS tube is respectively connected to the drain of the fifth MOS tube and the gate of the sixth MOS tube, the source of the fifth MOS tube and the source of the sixth MOS tube are both connected to the input voltage source, and the drain of the sixth MOS tube is connected to the input end of the charging capacitance changing circuit; when the charging current needs to be reduced When the charging current needs to be increased, the current adjustment branch includes a third MOS tube and a fourth MOS tube, the gate of the third MOS tube is the control potential input terminal, the source of the third MOS tube is connected to the input voltage source, the drain of the third MOS tube is connected to the source of the fourth MOS tube, and the drain of the fourth MOS tube is respectively connected to the gate of the fourth MOS tube and the drain of the fifth MOS tube; when the charging current needs to be increased, the current adjustment branch includes a twelfth MOS tube and a thirteenth MOS tube, the gate of the twelfth MOS tube is the control potential input terminal, the source of the twelfth MOS tube is grounded, the drain of the twelfth MOS tube is connected to the source of the thirteenth MOS tube, the drain of the thirteenth MOS tube is connected to the drain of the second MOS tube, and the gate of the thirteenth MOS tube is connected to the gate of the second MOS tube.
3. The frequency switchable oscillator circuit according to claim 1, characterized in that: The charging capacitor changing circuit comprises a seventh MOS tube, an eighth MOS tube, a ninth MOS tube, a tenth MOS tube, an eleventh MOS tube, a first capacitor and a second capacitor. The first capacitor is used as a main charging capacitor, and the second capacitor is used as an auxiliary capacitor. The source of the seventh MOS tube is grounded, and the gate of the seventh MOS tube is connected to the feedback output end of the pulse width modulation feedback circuit. The drain of the seventh MOS tube is respectively connected to the output end of the charging current changing circuit, one end of the first capacitor, the drain of the eighth MOS tube, the source of the tenth MOS tube and the gate of the eleventh MOS tube. The other end of the first capacitor is grounded. The source of the eighth MOS tube is respectively connected to the drain of the ninth MOS tube, the drain of the tenth MOS tube and one end of the second capacitor. The source of the ninth MOS tube is grounded. The gates of the eighth MOS tube, the ninth MOS tube and the tenth MOS tube are all control potential input ends. The drain of the tenth MOS tube is connected to one end of the second capacitor, and the other end of the second capacitor is grounded. The source of the eleventh MOS tube is grounded, and the drain of the eleventh MOS tube is respectively connected to the input voltage source and the input end of the pulse width modulation feedback circuit.
4. The frequency switchable oscillator circuit according to claim 1, characterized in that: The pulse width modulation feedback circuit includes a first inverter, a second inverter, a third inverter, a fourth inverter, a fifth inverter, a sixth inverter, a seventh inverter, an eighth inverter, a ninth inverter, a tenth inverter, an eleventh inverter, a first NAND gate, a second NAND gate and a third capacitor. The input end of the first inverter is respectively connected to the input voltage source and the output end of the charging capacitor changing circuit, the output end of the first inverter is respectively connected to the input end of the second inverter, the output end of the second inverter is respectively connected to the input end of the third inverter and the second input end of the second NAND gate, the output end of the third inverter is connected to the first input end of the first NAND gate, the output end of the first NAND gate is respectively connected to the input end of the fourth inverter and the input end of the sixth inverter, and the output end of the fourth inverter is respectively connected to the input end of the fourth inverter and the input end of the sixth inverter. The output end is connected to the input end of the fifth inverter, the output end of the fifth inverter serves as the output end of the pulse width modulation feedback circuit to output the clock signal, the output end of the sixth inverter is connected to the input end of the seventh inverter, the output end of the seventh inverter is respectively connected to the input end of the eighth inverter and one end of the third capacitor, the output end of the eighth inverter is connected to the input end of the ninth inverter, the output end of the ninth inverter is connected to the first input end of the second NAND gate, the output end of the second NAND gate is respectively connected to the second input end of the first NAND gate and the input end of the tenth inverter, the output end of the tenth inverter is connected to the input end of the eleventh inverter, and the output end of the eleventh inverter is connected to the feedback input end of the charging capacitor changing circuit as the feedback output end of the pulse width modulation feedback circuit.