High voltage diode

Abstract

The utility model provides a high-voltage diode. The high-voltage diode comprises a substrate; the epitaxial layer is located on the substrate; the first doped region extends into the epitaxial layer from one surface, far away from the substrate, of the epitaxial layer, and the doping type of the epitaxial layer is opposite to that of the first doped region; the first electrode is located on the surface, far away from the substrate, of the first doped region; the passivation layer is located on the surface, away from the substrate, of the epitaxial layer, the passivation layer wraps the first electrode and exposes the surface, away from the substrate, of the first electrode, and the passivation layer comprises an oxidation passivation layer, a semi-insulating polycrystalline silicon passivation layer, a glass passivation layer and a polyimide passivation layer which are stacked from bottom to top; and the second electrode is positioned on the surface, far away from the epitaxial layer, of the substrate. According to the utility model, the breakdown voltage of the high-voltage diode is greatly improved.

Description

Technical Field

[0001] The utility model relates to the technical field of semiconductors, in particular to a high-voltage diode. Background Art

[0002] Rectifier diodes are used to convert alternating current into direct current. The most important characteristic of a diode is its unidirectional conductivity. In a circuit, current can only flow into the positive electrode of the diode and out of the negative electrode. A traditional diode contains a PN junction. As power electronics technology continues to develop towards high power and high voltage, higher requirements are also placed on rectifier diodes, such as higher breakdown voltage, lower reverse leakage current, and higher power capacity. In traditional diodes based on PN junctions, the breakdown voltage is mainly borne by the depletion layer in the PN junction. The ideal device breakdown voltage refers to the case where the PN junction is a parallel plane junction. However, due to certain factors in the actual device production process (such as contamination of metal ions on the surface of the substrate), the breakdown voltage of the actual device is lower than the breakdown voltage of the ideal parallel plane junction, and it is difficult to achieve the demand for high breakdown voltage.

[0003] Therefore, how to make the device have a high breakdown voltage is an urgent problem to be solved. Utility Model Content

[0004] The utility model aims to provide a high-voltage diode, which greatly improves the breakdown voltage of the high-voltage diode.

[0005] To achieve the above object, the utility model provides a high voltage diode, comprising:

[0006] substrate;

[0007] an epitaxial layer, located on the substrate;

[0008] A first doped region extending from a side of the epitaxial layer away from the substrate into the epitaxial layer, wherein the epitaxial layer and the first doped region have opposite doping types;

[0009] A first electrode is located on a surface of the first doped region away from the substrate;

[0010] A passivation layer, located on a surface of the epitaxial layer away from the substrate, the passivation layer wraps the first electrode and exposes a surface of the first electrode away from the substrate, the passivation layer comprising an oxide passivation layer, a semi-insulating polysilicon passivation layer, a glass passivation layer and a polyimide passivation layer stacked from bottom to top;

[0011] The second electrode is located on a surface of the substrate away from the epitaxial layer.

[0012] Optionally, the thickness of the oxidized passivation layer is The thickness of the semi-insulating polysilicon passivation layer is The thickness of the glass passivation layer is 10 μm to 50 μm, and the thickness of the polyimide passivation layer is 5 μm to 20 μm.

[0013] Optionally, the high voltage diode further includes:

[0014] At least one voltage divider ring extends from a side of the epitaxial layer away from the substrate into the epitaxial layer, the at least one voltage divider ring surrounds the first doping region and is separated from the first doping region, and the at least one voltage divider ring has the same doping type as the first doping region.

[0015] Optionally, the number of the voltage divider rings is at least two, and the distance between adjacent voltage divider rings is 2 μm to 100 μm.

[0016] Optionally, a distance between the voltage divider ring closest to the first doping region and the first doping region is 2 μm to 50 μm.

[0017] Optionally, the oxidation passivation layer includes a multi-layer stacked silicon oxide layer.

[0018] Optionally, the oxide passivation layer includes a first silicon oxide layer, a second silicon oxide layer, a third silicon oxide layer and a fourth silicon oxide layer stacked from bottom to top, openings are formed in the first silicon oxide layer and the second silicon oxide layer, the third silicon oxide layer and the fourth silicon oxide layer are also stacked in the openings in sequence, and the openings correspond to the position of the voltage divider ring.

[0019] Optionally, the high voltage diode further includes:

[0020] A cut-off ring extends from a side of the epitaxial layer away from the substrate into the epitaxial layer, the cut-off ring surrounds all the voltage divider rings, and the cut-off ring has the same doping type as the epitaxial layer.

[0021] Optionally, a distance between the voltage divider ring closest to the cut-off ring and the cut-off ring is 20 μm to 100 μm.

[0022] Optionally, a junction depth of the first doped region is greater than or equal to a junction depth of the voltage divider ring, and a junction depth of the first doped region is greater than a junction depth of the cut-off ring.

[0023] Optionally, the junction depth of the first doping region is 5 μm to 50 μm, the junction depth of the voltage divider ring is 2 μm to 50 μm, and the junction depth of the cut-off ring is 3 μm to 30 μm.

[0024] Optionally, the high voltage diode further includes:

[0025] The second doping region is located on the top of the first doping region, and the second doping region has the same doping type as the first doping region.

[0026] Optionally, the breakdown voltage of the high-voltage diode is greater than or equal to 1200V.

[0027] Compared with the prior art, the high-voltage diode of the utility model comprises: a substrate; an epitaxial layer located on the substrate; a first doped region extending from a side of the epitaxial layer away from the substrate to the inside of the epitaxial layer, the epitaxial layer and the first doped region having opposite doping types; a first electrode located on a surface of the first doped region away from the substrate; a passivation layer located on a surface of the epitaxial layer away from the substrate, the passivation layer wraps the first electrode and exposes the surface of the first electrode away from the substrate, the passivation layer comprises an oxide passivation layer, a semi-insulating polysilicon passivation layer, a glass passivation layer and a polyimide passivation layer stacked from bottom to top; and a second electrode located on a surface of the substrate away from the epitaxial layer, thereby greatly improving the breakdown voltage of the high-voltage diode. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] Figure 1 This is a schematic diagram of the structure of a high voltage diode according to an embodiment of the utility model;

[0029] Figure 2a to Figure 2p It is a schematic diagram of various steps of a method for manufacturing a high voltage diode according to an embodiment of the utility model.

[0030] Among them, Figure 1 to Figure 2p The reference numerals are described as follows:

[0031] 10-substrate; 101-second electrode; 11-epitaxial layer; 12-first doped region; 121-second doped region; 13-first electrode; 14-oxidation passivation layer; 141-first silicon oxide layer; 1411-first opening; 142-second silicon oxide layer; 1421-second opening; 143-third silicon oxide layer; 1431-third opening; 144-fourth silicon oxide layer; 15-semi-insulating polysilicon passivation layer; 151-fourth opening; 152-fifth opening; 16-glass passivation layer; 161-sixth opening; 162-seventh opening; 17-polyimide passivation layer; 18-voltage divider ring; 19-cut-off ring. DETAILED DESCRIPTION

[0032] In order to make the purpose, advantages and features of the present invention more clear, the high voltage diode proposed by the present invention is further described in detail below. It should be noted that the drawings are all in a very simplified form and use non-precise proportions, which are only used to conveniently and clearly assist in explaining the purpose of the embodiments of the present invention.

[0033] An embodiment of the utility model provides a high-voltage diode, comprising: a substrate; an epitaxial layer, located on the substrate; a first doped region, extending from a side of the epitaxial layer away from the substrate to the inside of the epitaxial layer, the epitaxial layer and the first doped region having a doping type opposite; a first electrode, located on a surface of the first doped region away from the substrate; a passivation layer, located on a surface of the epitaxial layer away from the substrate, the passivation layer wraps the first electrode and exposes the surface of the first electrode away from the substrate, the passivation layer comprising an oxide passivation layer, a semi-insulating polysilicon passivation layer, a glass passivation layer and a polyimide passivation layer stacked from bottom to top; a second electrode, located on a surface of the substrate away from the epitaxial layer.

[0034] See below Figure 1 to Figure 2p The high voltage diode provided in this embodiment is described in more detail. Figure 1 to Figure 2p It is also a schematic diagram of a longitudinal section.

[0035] The epitaxial layer 11 is located on the substrate 10 .

[0036] The substrate 10 and the epitaxial layer 11 may be made of at least one of semiconductor materials such as single crystal silicon, germanium, silicon carbide, and gallium arsenide, but are not limited thereto.

[0037] The thickness of the epitaxial layer 11 may be 10 μm to 100 μm, but is not limited thereto.

[0038] The resistivity of the epitaxial layer 11 may be 1 Ω·cm to 1000 Ω·cm, but is not limited thereto.

[0039] The substrate 10 and the epitaxial layer 11 have the same doping type.

[0040] The substrate 10 is heavily doped, and the epitaxial layer 11 is lightly doped.

[0041] The first doped region 12 extends from a side of the epitaxial layer 11 away from the substrate 10 into the epitaxial layer 11 . The epitaxial layer 11 and the first doped region 12 have opposite doping types, so that a PN junction is formed between the epitaxial layer 11 and the first doped region 12 .

[0042] Preferably, the high-voltage diode further includes: a second doping region 121 located on the top of the first doping region 12 , the doping concentration of the second doping region 121 is greater than the doping concentration of the first doping region 12 , and the second doping region 121 has the same doping type as the first doping region 12 .

[0043] The second doping region 121 is heavily doped.

[0044] The first electrode 13 is located on a surface of the first doping region 12 away from the substrate 10 .

[0045] The thickness of the first electrode 13 may be 2 μm to 10 μm, but is not limited thereto.

[0046] The second doping region 121 can make the first electrode 13 contact with the first doping region 12 better, thereby reducing contact resistance.

[0047] The passivation layer is located on the surface of the epitaxial layer 11 away from the substrate 10, the passivation layer wraps the first electrode 13 and exposes the surface of the first electrode 13 away from the substrate 10, and the passivation layer includes an oxide passivation layer 14, a semi-insulating polycrystalline silicon (SIPOS, Semi-Insulating Polycrystalline Silicon) passivation layer 15, a glass passivation layer 16 and a polyimide passivation layer 17 stacked from bottom to top.

[0048] In one embodiment, the first electrode 13 may be located on a portion of the surface of the first doping region 12 away from the substrate 10 , and the passivation layer may extend from the surface of the epitaxial layer 11 outside the first doping region 12 to a portion of the first doping region 12 .

[0049] The semi-insulating polysilicon passivation layer 15 may be located only on the surface of the oxidized passivation layer 14 away from the substrate 10 (eg Figure 1 As shown), or, the semi-insulating polysilicon passivation layer 15 can be located simultaneously on the surface of the oxidized passivation layer 14 away from the substrate 10 and on the sidewalls of the oxidized passivation layer 14; the glass passivation layer 16 can be located only on the surface of the semi-insulating polysilicon passivation layer 15 away from the substrate 10, or, the glass passivation layer 16 can wrap the semi-insulating polysilicon passivation layer 15 and the oxidized passivation layer 14 (as shown). Figure 1 The polyimide passivation layer 17 may be located only on the surface of the glass passivation layer 16 away from the substrate 10, or the polyimide passivation layer 17 may extend from the surface of the glass passivation layer 16 away from the substrate 10 to the first electrode 13.

[0050] In one embodiment, the oxide passivation layer 14 may include a multi-layer stacked silicon oxide layer. Figure 1 As shown, the oxidized passivation layer 14 includes a first silicon oxide layer 141, a second silicon oxide layer 142, a third silicon oxide layer 143 and a fourth silicon oxide layer 144 stacked from bottom to top. In other embodiments, the oxidized passivation layer 14 may also include a multi-layer stacked silicon oxynitride layer, or a multi-layer stacked silicon oxide layer and a silicon oxynitride layer.

[0051] The thickness of the oxidation passivation layer 14 can be But not limited to this. The thickness of the first silicon oxide layer 141 can be But it is not limited to this.

[0052] The thickness of the semi-insulating polysilicon passivation layer 15 can be The glass passivation layer 16 may have a thickness of 10 μm to 50 μm, and the polyimide passivation layer 17 may have a thickness of 5 μm to 20 μm, but are not limited thereto.

[0053] The second electrode 101 is located on a surface of the substrate 10 away from the epitaxial layer 11 .

[0054] The first electrode 13 is used for wire bonding in the packaging process, and the second electrode 101 is used for electrically connecting to a substrate through a conductive material such as a die-bonding adhesive or solder paste in the packaging process.

[0055] The first electrode 13 and the second electrode 101 may be made of a suitable material according to the requirements of the packaging process, for example, they may include at least one of Al, Ag, Au, Cu and Ni.

[0056] The thickness of the second electrode 101 may be 1 μm to 5 μm, but is not limited thereto.

[0057] The high-voltage diode also includes: at least one voltage divider ring 18, extending from a side of the epitaxial layer 11 away from the substrate 10 to the inside of the epitaxial layer 11, the at least one voltage divider ring 18 surrounds the first doping region 12 and is separated from the first doping region 12, and the at least one voltage divider ring 18 has the same doping type as the first doping region 12.

[0058] The voltage divider ring 18 can help widen the width of the depletion layer in the PN junction formed between the epitaxial layer 11 and the first doping region 12 .

[0059] exist Figure 1 In the embodiment shown, the first silicon oxide layer 141 and the second silicon oxide layer 142 have at least one second opening 1421 (i.e. Figure 2e The second opening 1421 penetrates the first silicon oxide layer 141 and the second silicon oxide layer 142 to expose the epitaxial layer 11, and the voltage divider ring 18 is formed by ion implantation into the epitaxial layer 11 exposed by the second opening 1421, that is, the second opening 1421 corresponds to the position of the voltage divider ring 18; the third silicon oxide layer 143 and the fourth silicon oxide layer 144 are also stacked in the second opening 1421 in sequence, and the semi-insulating polysilicon passivation layer 15 fills the second opening 1421.

[0060] The number of the voltage divider rings 18 is selected according to the actual breakdown voltage of the high voltage diode.

[0061] Preferably, the width of the voltage divider ring 18 is 2 μm to 20 μm, but is not limited thereto.

[0062] When the number of the voltage divider rings 18 is at least two, the distance between adjacent voltage divider rings 18 is preferably 2 μm to 100 μm, but is not limited thereto.

[0063] Preferably, the distance between the voltage divider ring 18 closest to the first doping region 12 and the first doping region 12 is 2 μm to 50 μm, but is not limited thereto.

[0064] Preferably, the high-voltage diode also includes: a cut-off ring 19, extending from a side of the epitaxial layer 11 away from the substrate 10 to the inside of the epitaxial layer 11, the cut-off ring 19 surrounds all of the voltage divider rings 18, the doping concentration of the cut-off ring 19 is greater than the doping concentration of the epitaxial layer 11, and the cut-off ring 19 has the same doping type as the epitaxial layer 11.

[0065] Since the doping concentration of the epitaxial layer 11 is relatively low, the epitaxial layer 11 may be inverted due to external influences. By providing the cut-off ring 19 with a doping concentration greater than that of the epitaxial layer 11 , the epitaxial layer 11 can be prevented from being inverted.

[0066] The passivation layer may or may not extend onto the stop ring 19 .

[0067] Preferably, the distance between the voltage divider ring 18 closest to the cut-off ring 19 and the cut-off ring 19 is 20 μm to 100 μm, but is not limited thereto.

[0068] The junction depth of the first doping region 12 is greater than or equal to the junction depth of the voltage divider ring 18 , and the junction depth of the first doping region 12 is greater than the junction depth of the cut-off ring 19 .

[0069] Preferably, the junction depth of the first doping region 12 is 5 μm to 50 μm, the junction depth of the voltage divider ring 18 is 2 μm to 50 μm, the junction depth of the cut-off ring 19 is 3 μm to 30 μm, and the junction depth of the second doping region 121 is 1 μm to 10 μm, but not limited thereto.

[0070] When the doping type of the substrate 10, the epitaxial layer 11 and the cut-off ring 19 is N-type, the doping type of the first doping region 12, the second doping region 121 and the voltage divider ring 18 is P-type; when the doping type of the substrate 10, the epitaxial layer 11 and the cut-off ring 19 is P-type, the doping type of the first doping region 12, the second doping region 121 and the voltage divider ring 18 is N-type.

[0071] See below Figure 1 to Figure 2p The manufacturing method of the high voltage diode is described as follows:

[0072] First, if Figure 2a As shown, a substrate 10 is provided, and an epitaxial layer 11 is epitaxially grown on the substrate 10;

[0073] Then, if Figure 2b As shown, a first silicon oxide layer 141 is grown on the epitaxial layer 11;

[0074] Then, if Figure 2c As shown, the first silicon oxide layer 141 is etched to form a first opening 1411 in the first silicon oxide layer 141 to expose a portion of the surface of the epitaxial layer 11;

[0075] Then, if Figure 2d As shown, with the first silicon oxide layer 141 as a masking layer, ion implantation is performed into the epitaxial layer 11 exposed by the first opening 1411, and a high-temperature annealing process is performed to form a first doped region 12 in the epitaxial layer 11; and, under the action of the high-temperature annealing process, a second silicon oxide layer 142 is formed on the surface of the epitaxial layer 11 exposed by the first opening 1411 and the surface of the first silicon oxide layer 141, and the thickness of the second silicon oxide layer 142 formed on the surface of the epitaxial layer 11 exposed by the first opening 1411 is greater than the thickness of the second silicon oxide layer 142 formed on the surface of the first silicon oxide layer 141;

[0076] Then, if Figure 2e As shown, the second silicon oxide layer 142 and the first silicon oxide layer 141 on the epitaxial layer 11 outside the first doped region 12 are etched to form at least one second opening 1421 in the second silicon oxide layer 142 and the first silicon oxide layer 141 to expose a portion of the surface of the epitaxial layer 11;

[0077] Then, if Figure 2fAs shown, with the second silicon oxide layer 142 and the first silicon oxide layer 141 as masking layers, ion implantation is performed into the epitaxial layer 11 exposed by the second opening 1421, and a high-temperature annealing process is performed to form at least one voltage divider ring 18 in the epitaxial layer 11, and the voltage divider ring 18 surrounds the first doped region 12; and, under the action of the high-temperature annealing process, a third silicon oxide layer 143 is formed on the surface of the epitaxial layer 11 exposed by the second opening 1421 and on the surfaces of the first silicon oxide layer 141 and the second silicon oxide layer 142, and the thickness of the third silicon oxide layer 143 formed on the surface of the epitaxial layer 11 exposed by the second opening 1421 is greater than the thickness of the third silicon oxide layer 143 formed on the surfaces of the first silicon oxide layer 141 and the second silicon oxide layer 142;

[0078] Then, if Figure 2g As shown, the third silicon oxide layer 143, the second silicon oxide layer 142 and the first silicon oxide layer 141 on the epitaxial layer 11 at the periphery of all the voltage divider rings 18 are etched to form a third opening 1431 in the third silicon oxide layer 143, the second silicon oxide layer 142 and the first silicon oxide layer 141 to expose a portion of the surface of the epitaxial layer 11;

[0079] Then, if Figure 2h As shown, the third silicon oxide layer 143, the second silicon oxide layer 142 and the first silicon oxide layer 141 are used as masking layers, ion implantation is performed into the epitaxial layer 11 exposed by the third opening 1431, and a high-temperature annealing process is performed to form a cut-off ring 19 in the epitaxial layer 11, and the cut-off ring 19 surrounds all the voltage divider rings 18; and under the action of the high-temperature annealing process, the surface of the epitaxial layer 11 exposed by the third opening 1431 and the surfaces of the first silicon oxide layer 141, the second silicon oxide layer 142 and the third silicon oxide layer 143 form a fourth The silicon oxide layer 144, the fourth silicon oxide layer 144 formed on the surface of the epitaxial layer 11 exposed by the third opening 1431 has a thickness greater than the fourth silicon oxide layer 144 formed on the surfaces of the first silicon oxide layer 141, the second silicon oxide layer 142 and the third silicon oxide layer 143, and the first silicon oxide layer 141, the second silicon oxide layer 142, the third silicon oxide layer 143 and the fourth silicon oxide layer 144 constitute an oxidized passivation layer 14; in other embodiments, if the oxidized passivation layer 14 also includes a silicon oxynitride layer, a silicon oxynitride layer is formed on the fourth silicon oxide layer 144;

[0080] Then, if Figure 2i As shown, a semi-insulating polysilicon passivation layer 15 is grown to cover the fourth silicon oxide layer 144;

[0081] Then, if Figure 2j As shown, the semi-insulating polysilicon passivation layer 15 and the oxidized passivation layer 14 above the first doped region 12 are etched to form a fourth opening 151 exposing the first doped region 12; and the semi-insulating polysilicon passivation layer 15 and the oxidized passivation layer 14 above the stop ring 19 are etched to form a fifth opening 152 exposing the stop ring 19;

[0082] Then, if Figure 2k As shown, ion implantation is performed into the first doping region 12 exposed by the fourth opening 151 to form a second doping region 121 on the top of the first doping region 12;

[0083] Then, if Figure 2l As shown, a glass passivation layer 16 is grown, the glass passivation layer 16 covers the semi-insulating polysilicon passivation layer 15, the oxidized passivation layer 14, the second doped region 121 and the stop ring 19, and the glass passivation layer 16 fills the fourth opening 151 and the fifth opening 152;

[0084] Then, if Figure 2m As shown, the glass passivation layer 16 on the second doping region 121 is etched to form a sixth opening 161 exposing the second doping region 121; and the glass passivation layer 16 on the stop ring 19 is etched to form a seventh opening 162 exposing the stop ring 19;

[0085] Then, if Figure 2n As shown, the first electrode 13 is grown in the sixth opening 161;

[0086] Then, if Figure 2o As shown, a polyimide passivation layer 17 is grown on the glass passivation layer 16, and the polyimide passivation layer 17 can also extend to a portion of the first electrode 13;

[0087] Then, if Figure 2p As shown, the second electrode 101 is grown on the surface of the substrate 10 away from the epitaxial layer 11 .

[0088] In general high-voltage diodes, there are traditional diodes based on PN junctions. For example, a PN junction composed of an N-type substrate and a P-type epitaxial layer located on the N-type substrate is used. In order to increase the breakdown voltage, a groove is usually dug at the edge of the P-type epitaxial layer to form a table structure. The groove is used to remove the location where the electric field is concentrated at the edge of the PN junction space charge region, and then the groove is filled with a semi-insulating polysilicon passivation layer and a glass passivation layer, which mainly plays a role in protecting the groove. However, the semi-insulating polysilicon passivation layer and the glass passivation layer are not formed on the device surface (the surface of the epitaxial layer) outside the groove, so that the uniformity of the high-voltage diode voltage is greatly affected by the morphology of the groove, and it is difficult to obtain a high-voltage diode with good performance; or, there are some planar structures, the surface of which uses one of the semi-insulating polysilicon passivation layer, silicon oxide passivation layer and polyimide passivation layer as a passivation structure, but such a structure cannot effectively widen the PN junction space charge region, and it is difficult to achieve an ultra-high breakdown voltage of more than 1200V.

[0089] In the high-voltage diode of the utility model, the passivation layer is located on the surface of the epitaxial layer 11 away from the substrate 10, and the passivation layer is a multi-layer composite passivation structure, and the passivation layer includes the oxidized passivation layer 14, the semi-insulating polycrystalline silicon passivation layer 15, the glass passivation layer 16 and the polyimide passivation layer 17 stacked from bottom to top; wherein the oxidized passivation layer 14 plays the role of a masking layer and an insulating layer, and the structure of the oxidized passivation layer 14 is dense, and has good buffering performance, which can prevent stress from generating silicon defects; the semi-insulating polycrystalline silicon passivation layer 15 has defect energy levels, which can effectively shield the external electric field, so that the surface effect of the device can be greatly reduced; the glass passivation layer 16 contains fixed charges, which can change the expansion range of the reverse biased PN junction space charge region, and effectively widen the depletion layer width of the PN junction; the polyimide passivation layer 17 has strong mechanical properties and chemical corrosion resistance, and can effectively suppress the positive charge introduced from the outside.

[0090] Furthermore, since the oxidized passivation layer 14 has good masking properties, it is convenient to produce various photolithography patterns. Therefore, designing the oxidized passivation layer 14 as the bottom layer of the passivation layer is more conducive to the processing of the entire device process. The semi-insulating polysilicon passivation layer 15 itself has a certain moisture absorption property, which is beneficial to the Na +The barrier capability of the semi-insulating polysilicon passivation layer 15 between the oxide passivation layer 14 and the glass passivation layer 16 is very weak, and the moisture absorption problem can be effectively avoided by designing the semi-insulating polysilicon passivation layer 15 between the oxide passivation layer 14 and the glass passivation layer 16; in order to ensure a better PN junction space charge region expansion effect, the thickness of the glass passivation layer 16 is relatively thick (e.g., 10 μm to 50 μm), resulting in the introduction of a larger step after the patterning of the glass passivation layer 16, and the polyimide passivation layer 17 has good step coverage, therefore, the glass passivation layer 16 is formed before the polyimide passivation layer 17, and the step coverage of the glass passivation layer 16 can be ensured; since the polyimide passivation layer 17 cannot be subjected to a temperature above 600°C after coating, therefore, the polyimide passivation layer 17 is designed as the last layer in the passivation layer, so that the high-temperature process in the process of manufacturing the high-voltage diode is completed before the polyimide passivation layer 17, and the polyimide passivation layer 17 is avoided from being damaged.

[0091] Therefore, near the interface between the substrate 10 and the oxidized passivation layer 14, the above-mentioned properties between the dielectric layers in the passivation layer with a multi-layer composite passivation structure can greatly reduce the electric field strength on the device surface after being effectively matched with each other, so that the breakdown position of the PN junction occurs inside the device rather than on the surface of the device, thereby obtaining better breakdown voltage characteristics; and having lower reverse leakage current performance.

[0092] When the high-voltage diode also includes at least one voltage divider ring 18, that is, the high-voltage diode adopts a composite design of a multi-layer composite passivation structure and the voltage divider ring 18, so that under the joint action of the multi-layer composite passivation structure and the voltage divider ring 18, the depletion layer width of the PN junction is fully widened, thereby further improving the breakdown voltage of the high-voltage diode.

[0093] The breakdown voltage of the high-voltage diode is greater than or equal to 1200V, so that the high-voltage diode is more suitable for application in high-voltage rectification circuits.

[0094] In summary, the high-voltage diode of the utility model comprises: a substrate; an epitaxial layer located on the substrate; a first doped region extending from a side of the epitaxial layer away from the substrate to the inside of the epitaxial layer, the epitaxial layer and the first doped region having opposite doping types; a first electrode located on a surface of the first doped region away from the substrate; a passivation layer located on a surface of the epitaxial layer away from the substrate, the passivation layer wraps the first electrode and exposes a surface of the first electrode away from the substrate, the passivation layer comprises an oxide passivation layer, a semi-insulating polysilicon passivation layer, a glass passivation layer and a polyimide passivation layer stacked from bottom to top; and a second electrode located on a surface of the substrate away from the epitaxial layer. The utility model greatly improves the breakdown voltage of the high-voltage diode.

[0095] The above description is only a description of the preferred embodiment of the utility model, and is not any limitation on the scope of the utility model. Any changes and modifications made by ordinary technicians in the field of the utility model based on the above disclosure shall fall within the scope of protection of the claims.

Claims

1. A high voltage diode, characterized in that: include: substrate; an epitaxial layer, located on the substrate; A first doped region extending from a side of the epitaxial layer away from the substrate into the epitaxial layer, wherein the epitaxial layer and the first doped region have opposite doping types; A first electrode is located on a surface of the first doped region away from the substrate; A passivation layer, located on a surface of the epitaxial layer away from the substrate, the passivation layer wraps the first electrode and exposes a surface of the first electrode away from the substrate, the passivation layer comprising an oxide passivation layer, a semi-insulating polysilicon passivation layer, a glass passivation layer and a polyimide passivation layer stacked from bottom to top; The second electrode is located on a surface of the substrate away from the epitaxial layer.

2. The high voltage diode according to claim 1, characterized in that: The thickness of the oxide passivation layer is The thickness of the semi-insulating polysilicon passivation layer is The thickness of the glass passivation layer is 10 μm to 50 μm, and the thickness of the polyimide passivation layer is 5 μm to 20 μm.

3. The high voltage diode according to claim 1, characterized in that: The high voltage diode further comprises: At least one voltage divider ring extends from a side of the epitaxial layer away from the substrate into the epitaxial layer, the at least one voltage divider ring surrounds the first doping region and is separated from the first doping region, and the at least one voltage divider ring has the same doping type as the first doping region.

4. The high voltage diode according to claim 3, characterized in that: The number of the voltage divider rings is at least two, and the distance between adjacent voltage divider rings is 2 μm to 100 μm.

5. The high voltage diode according to claim 3, characterized in that: The distance between the voltage divider ring closest to the first doping region and the first doping region is 2 μm to 50 μm.

6. The high voltage diode according to claim 3, characterized in that: The oxidation passivation layer includes a multi-layer stacked silicon oxide layer.

7. The high voltage diode according to claim 6, characterized in that: The oxidation passivation layer includes a first silicon oxide layer, a second silicon oxide layer, a third silicon oxide layer and a fourth silicon oxide layer stacked from bottom to top, openings are formed in the first silicon oxide layer and the second silicon oxide layer, the third silicon oxide layer and the fourth silicon oxide layer are also stacked in the openings in sequence, and the openings correspond to the position of the voltage divider ring.

8. The high voltage diode according to claim 3, characterized in that: The high voltage diode further comprises: A cut-off ring extends from a side of the epitaxial layer away from the substrate into the epitaxial layer, the cut-off ring surrounds all the voltage divider rings, and the cut-off ring has the same doping type as the epitaxial layer.

9. The high voltage diode according to claim 8, characterized in that: The distance between the voltage divider ring closest to the cut-off ring and the cut-off ring is 20 μm to 100 μm.

10. The high voltage diode according to claim 8, characterized in that: The junction depth of the first doped region is greater than or equal to the junction depth of the voltage divider ring, and the junction depth of the first doped region is greater than the junction depth of the cut-off ring.

11. The high voltage diode according to claim 10, characterized in that: The junction depth of the first doping region is 5 μm to 50 μm, the junction depth of the voltage divider ring is 2 μm to 50 μm, and the junction depth of the cut-off ring is 3 μm to 30 μm.

12. The high voltage diode according to claim 1, characterized in that: The high voltage diode further comprises: The second doping region is located on the top of the first doping region, and the second doping region has the same doping type as the first doping region.

13. The high voltage diode according to claim 1, characterized in that: The breakdown voltage of the high voltage diode is greater than or equal to 1200V.

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