A high-speed acquisition processing module

Abstract

The utility model provides a high-speed acquisition processing module, including a power module, a signal processing module, a transceiver module, a clock module, a communication module, a bus interface and an Ethernet module; the signal processing module, the transceiver module and the clock module are internally connected for communication; the communication module and the bus interface are externally connected for communication; the signal processing module is composed of 2 FPGA chips and 1 DSP chip, which are FPGA1, FPGA2 and DSP, and the FPGA1 is connected to FPGA2 and DSP respectively; the transceiver module is composed of 4 dual-channel RF transceiver chips, which realizes 2-way intermediate frequency signal generation function and 2-way intermediate frequency signal reception function. Through the highly integrated broadband RF transceiver used in the module, 4-way AD acquisition and DA output are realized. The output of 2 highly integrated broadband RF transceiver channels with different frequency points and 2-way signal sampling are realized, and its operating frequency can be configured within the range of 300MHz to 6GHz.

Description

Technical Field

[0001] The utility model belongs to the technical field of signal processing, and in particular relates to a high-speed acquisition processing module. Background Art

[0002] In the field of communications and electronics, high-speed signals usually refer to electrical signals or data signals with high frequencies, which are usually between tens of megahertz and several gigahertz. The characteristics of high-speed signals include short signal cycles, complex waveforms, large transmission losses and signal distortion in the signal transmission path, etc. Due to their high frequency and complexity, the transmission and processing of high-speed signals requires special design and technology to ensure the stability, accuracy and reliability of the signals.

[0003] At present, the acquisition and generation of high-speed intermediate frequency signals have become a key design requirement in radar and electronic countermeasure equipment. It mainly realizes the acquisition of relevant intermediate frequency signals in radar and electronic countermeasure, and generates the intermediate frequency signals required by the equipment, which can provide important technical support for the interception, analysis, identification, interference and other means of the overall equipment. At present, with the expansion of the application scope of the whole system, high integration, multi-channel input and output, configurability and other aspects show a greater development trend. Therefore, the utility model proposes a high-speed acquisition and processing module. Utility Model Content

[0004] The technical problem to be solved by the utility model is to provide a high-speed signal acquisition and processing module to meet the requirements of high integration, multi-channel input and output, high resolution and configurability.

[0005] In order to solve the above technical problems, the technical solution provided by the utility model is: a high-speed acquisition and processing module, including a power module, a signal processing module, a transceiver module, a clock module, a communication module, a bus interface and an Ethernet module; the signal processing module, the transceiver module and the clock module are internally communicated and connected; the communication module and the bus interface are externally communicated and connected; the signal processing module is composed of 2 FPGA chips and 1 DSP chip, which are FPGA1, FPGA2 and DSP respectively, and the FPGA1 is connected to FPGA2 and DSP respectively; the transceiver module is composed of 4 dual-channel RF transceiver chips, realizing the function of generating 2 intermediate frequency signals and receiving 2 intermediate frequency signals.

[0006] As an improvement, the dual-channel RF transceiver chip is an AD9371 chip.

[0007] As an improvement, the FPGA1 is an XC7VX690T chip, the FPGA2 is an XC7Z045 chip; and the DSP is a TMS320C6748 chip.

[0008] As an improvement, the FPGA1 is connected to a transceiver module for processing the AD signal and the DA signal.

[0009] As an improvement, the FPGA2 is connected to the bus interface via SRIO, GPIO, RS422 and RGMII interfaces.

[0010] As an improvement, the FPGA2 is configured with a NOR FLASH chip, and the chip model is S29GL01, which is used to store MCS files; the FPGA2 is configured with a QSPI FLASH chip, and the chip model is S29GL01S25FL128, which is used to implement the storage of uboot files; the FPGA2 is configured with an EMMC memory, and the memory model is MTFC32GA, which is used to store the file system.

[0011] As an improvement, the DSP chip is connected to FPGA2 via an SPI interface; and the DSP chip is connected to FPGA1 via an EMIF interface; the DSP chip is connected to a bus interface via RGMII to achieve relevant data communication.

[0012] As an improvement, both the FPGA1 and FPGA2 are configured with a cache DDR3 chip, and the chip model is MT41K512M16HA; the DSP is configured with a cache DDR2 chip, and the chip model is MT47H128M16RT.

[0013] As an improvement, the Ethernet module is a 2-way 1000M, which is connected to FPGA2 and DSP. The connection with FPGA2 mainly completes the module's program dynamic loading function, and the connection with DSP mainly completes the control and management functions of the main control platform.

[0014] The advantages of the utility model compared with the prior art are:

[0015] (1) The module uses a highly integrated broadband RF transceiver to achieve 4-way AD acquisition and DA output. It also achieves 2-way frequency output and 2-way signal sampling. Its operating frequency can be configured in the range of 300MHz to 6GHz.

[0016] (2) In the signal processing part, the FPGA and DSP architecture are used to give full play to the parallel data processing capability of FPGA and the computing capability of DSP, realizing multi-channel sampling data synchronization, pulse compression, beam forming and other functions, effectively sharing the data processing work of the main control platform.

[0017] (3) The design adopts dynamic loading, which dynamically updates the FPGA and DSP programs through the network port, improving the flexibility of the module functions. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Figure 1 The utility model is a circuit block diagram of a high-speed acquisition and processing module.

[0019] Figure 2 The utility model is a power rail block diagram of a high-speed acquisition and processing module.

[0020] Figure 3 The figure is a dynamic loading schematic diagram of a high-speed acquisition and processing module of the utility model. DETAILED DESCRIPTION

[0021] The following will be combined with the drawings in the embodiments of the utility model to clearly and completely describe the technical solutions in the embodiments of the utility model. Obviously, the described embodiments are only part of the embodiments of the utility model, not all of the embodiments. Based on the embodiments in the utility model, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the utility model.

[0022] In the description of the utility model, it should be noted that, unless otherwise clearly specified and limited, the terms "installed", "provided with", "connected", etc. should be understood in a broad sense. For example, "connected" can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection, or it can be indirectly connected through an intermediate medium, or it can be the internal communication of two components. For ordinary technicians in this field, the specific meanings of the above terms in the utility model can be understood according to specific circumstances.

[0023] Embodiment 1:

[0024] As the instruction manual Figure 1 As shown, the utility model provides a high-speed acquisition processing module, including a power module, a signal processing module, a transceiver module, a clock module, a communication module, a bus interface and an Ethernet module.

[0025] In order to meet the requirements of high integration, multi-channel input and output, and configurability, the embodiment of the utility model adopts a design scheme of FPGA and DSP architecture, including 2 FPGA chips and 1 DSP chip, wherein the FPGA chip cooperates with the peripheral clock module, configuration chip, cache chip, high-speed and low-speed interfaces to form an FPGA module, and the DSP chip also cooperates with its peripheral clock, configuration chip, cache chip, and high-speed and low-speed interfaces to form a DSP module, which jointly provide functions such as signal acquisition, generation control, signal preprocessing and data exchange, and realize data interaction with other boards through the external SRIO interface.

[0026] Specifically, FPGA1 is connected to FPGA2 and DSP in communication respectively; FPGA2 is connected to the bus interface through SRIO, GPIO, RS422 and RGMII interfaces; FPGA1 is connected to the transceiver module in communication to process AD signals and DA signals.

[0027] FPGA1 is used to configure the broadband RF transceiver and data exchange, and completes data communication through the JESD204B communication protocol; FPGA1 and FPGA2 have 10 LVDS signals for data exchange and load configuration through the CFG Bus signal; FPGA1 and DSP have 1 EMIFA and 6 GPIOs for data exchange; in addition, FPGA1 exchanges data with the sensors in the module through GPIO to complete status monitoring.

[0028] FPGA2 provides 1 RS422 interface, 3 X1 SRIO, 8 GPIO and 1 network signal to communicate with external boards, dynamically load Zynq's MCS file, FPGA's MCS file and DSP program through the network port, realize sampling, data generation interaction, and module status reporting.

[0029] DSP and FPGA2 exchange data through the SPI interface, and also provide a network signal to achieve communication with external boards.

[0030] FPGA2 in the embodiment of the utility model is configured with a NOR FLASH chip, and the chip model is S29GL01, which is used to store MCS files; FPGA2 is configured with a QSPI FLASH chip, and the chip model is S29GL01S25FL128, which is used to implement the storage of uboot files; FPGA2 is configured with an EMMC memory, and the memory model is MTFC32GA, which is used to store the file system.

[0031] In addition, FPGA1 and FPGA2 are both equipped with cache DDR3 chips, and the chip model is MT41K512M16HA; DSP is equipped with cache DDR2 chips, and the chip model is MT47H128M16RT.

[0032] The AD9371 is a highly integrated wideband RF transceiver that replaces up to 20 high-performance discrete components, covers a frequency range of 300MHz to 6GHz, supports up to 100MHz receiver and transmit large signal instantaneous bandwidth, up to 250MHz observation receiver and transmit synthesis bandwidth, fully integrated LO and clock functions, and highly advanced on-chip calibration and correction algorithms.

[0033] As the instruction manual Figure 2 As shown, each chip in the high-speed acquisition and processing module is powered accordingly as shown in the figure to ensure that the high-speed acquisition and processing module can work normally.

[0034] As the instruction manual Figure 3 As shown, FPGA2 first runs FSBL, initializes relevant configurations, loads the uboot code in the external flash, and loads the device tree, kernel image and file system, etc. into the emmc partition according to the uboot settings; after the kernel is started, it loads the program with the DSP module through the AIS protocol, and starts the DSP after the loading is completed; FPGA1 loads relevant codes, configures relevant pins to connect to corresponding peripherals, and converts corresponding level signals; at this time, FPGA1 configures the AD9371 module through relevant pins to initialize the module; after the initialization is completed, it waits for subsequent work instructions to complete signal acquisition and signal generation.

[0035] The above describes the utility model and its implementation methods, which are not restrictive. The specific implementation method is only one of the implementation methods of the utility model, and the actual structure is not limited thereto. In short, if ordinary technicians in this field are inspired by it, without departing from the purpose of the invention of the utility model, they can design a structure and embodiment similar to the technical solution without creativity, which should belong to the protection scope of the utility model.

Claims

1. A high-speed acquisition processing module, characterized in that: It includes a power module, a signal processing module, a transceiver module, a clock module, a communication module, a bus interface and an Ethernet module; the signal processing module, the transceiver module and the clock module are internally connected for communication; the communication module and the bus interface are externally connected for communication; the signal processing module is composed of 2 FPGA chips and 1 DSP chip, which are FPGA1, FPGA2 and DSP respectively, and the FPGA1 is connected to FPGA2 and DSP respectively; the transceiver module is composed of 4 dual-channel RF transceiver chips, realizing the function of generating 2 intermediate frequency signals and receiving 2 intermediate frequency signals.

2. A high-speed acquisition processing module according to claim 1, characterized in that: The dual-channel RF transceiver chip is an AD9371 chip.

3. A high-speed acquisition processing module according to claim 1, characterized in that: The FPGA1 is an XC7VX690T chip, the FPGA2 is an XC7Z045 chip; and the DSP is a TMS320C6748 chip.

4. A high-speed acquisition processing module according to claim 1, characterized in that: The FPGA1 is connected to the transceiver module and is used to process AD signals and DA signals.

5. The high-speed acquisition processing module according to claim 1, characterized in that: The FPGA2 is connected to the bus interface via SRIO, GPIO, RS422 and RGMII interfaces.

6. A high-speed acquisition processing module according to claim 1, characterized in that: The FPGA2 is configured with a NORFLASH chip, and the chip model is S29GL01, which is used to store MCS files; the FPGA2 is configured with a QSPI FLASH chip, and the chip model is S29GL01S25FL128, which is used to implement the storage of uboot files; the FPGA2 is configured with an EMMC memory, and the memory model is MTFC32GA, which is used to store the file system.

7. A high-speed acquisition processing module according to claim 1, characterized in that: The DSP chip is connected to FPGA2 via an SPI interface; and the DSP chip is connected to FPGA1 via an EMIF interface; the DSP chip is connected to a bus interface via RGMII to achieve relevant data communication.

8. A high-speed acquisition processing module according to claim 1, characterized in that: The FPGA1 and FPGA2 are both configured with a cache DDR3 chip, and the chip model is MT41K512M16HA; the DSP is configured with a cache DDR2 chip, and the chip model is MT47H128M16RT.

9. A high-speed acquisition processing module according to claim 1, characterized in that: The Ethernet module is a 2-way 1000M module connected to FPGA2 and DSP. The Ethernet module is connected to FPGA2 to mainly complete the program dynamic loading function of the module, and is connected to DSP to complete the control and management functions of the main control platform.

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