Semiconductor device

Abstract

A semiconductor device is provided, and a method is provided for implementing heat dissipation multilayer and reducing thermal boundary resistance for a high power consumption semiconductor device. The semiconductor device includes a first transistor, a second transistor over the first transistor, and a heat dissipation multilayer between the first transistor and the second transistor. The heat dissipation multilayer comprises a first layer, a second layer and a third layer located between the first layer and the second layer, the first layer and the second layer comprise crystalline structures, and the third layer comprises an amorphous structure.

Description

Technical Field

[0001] The present disclosure relates to a semiconductor device. Background Art

[0002] As the semiconductor industry moves further toward sub-10 nanometer (nm) technology process nodes in search of higher device density, higher performance, and lower cost, challenges from manufacturing and design issues have resulted in stacked device structure configurations, such as complementary field effect transistors (C-FETs), in which an n-type multi-gate transistor and a p-type multi-gate transistor are vertically stacked, one above the other. While existing C-FET structures are generally adequate, they are not satisfactory in all aspects. Utility Model Content

[0003] A semiconductor device includes a first transistor, a second transistor located above the first transistor, and a heat dissipation multilayer located between the first transistor and the second transistor. The first transistor includes a first semiconductor layer; a first gate structure surrounding the first semiconductor layer; and a first source / drain epitaxial structure located at opposite ends of the first semiconductor layer. The second transistor includes a second semiconductor layer; a second gate structure surrounding the second semiconductor layer; and a second source / drain epitaxial structure located at opposite ends of the second semiconductor layer. The heat dissipation multilayer is located between the first transistor and the second transistor, wherein the heat dissipation multilayer includes a first layer, a second layer, and a third layer located between the first layer and the second layer, and wherein the first layer and the second layer include crystalline structures, and the third layer includes an amorphous structure.

[0004] A semiconductor device includes a first transistor, a second transistor located on the front side of the first transistor, a backside interconnect structure located on the back side of the first transistor, and a heat dissipation multilayer located between the backside interconnect structure and the first transistor. The first transistor includes a first semiconductor layer; a first gate structure surrounding the first semiconductor layer; and a first source / drain epitaxial structure located on opposite ends of the first semiconductor layer. The second transistor includes a second semiconductor layer; a second gate structure surrounding the second semiconductor layer; and a second source / drain epitaxial structure located on opposite ends of the second semiconductor layer. The heat dissipation multilayer includes a first heat dissipation layer, a second heat dissipation layer, and a dielectric layer located between the first heat dissipation layer and the second heat dissipation layer.

[0005] In some embodiments of the present disclosure, a semiconductor device includes a first transistor, a second transistor located above the first transistor, and a heat dissipation multilayer located between the first transistor and the second transistor. The first transistor includes a first semiconductor layer; a first gate structure surrounding the first semiconductor layer; and a first source / drain epitaxial structure located at opposite ends of the first semiconductor layer. The second transistor includes a second semiconductor layer; a second gate structure surrounding the second semiconductor layer; and a second source / drain epitaxial structure located at opposite ends of the second semiconductor layer. The heat dissipation multilayer is located between the first transistor and the second transistor, wherein the heat dissipation multilayer includes a first heat dissipation layer, a second heat dissipation layer, and a dielectric layer located between the first heat dissipation layer and the second heat dissipation layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] The various aspects of the present disclosure can be best understood when the following detailed description is read in conjunction with the accompanying drawings. It should be noted that, in accordance with standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of various features may be arbitrarily increased or reduced for clarity of discussion.

[0007] Figure 1 is a perspective view of a semiconductor device according to some embodiments of the present disclosure;

[0008] Figures 2 to 8B Describes methods in various stages of forming a semiconductor device according to some embodiments of the present disclosure;

[0009] Fig. 9 Describing semiconductor devices according to some embodiments of the present disclosure;

[0010] Figures 10 to 20 Describes methods in various stages of forming a semiconductor device according to some embodiments of the present disclosure;

[0011] Fig.21A and Fig. 21B is a schematic diagram of heat dissipation according to some embodiments of the present disclosure;

[0012] Fig.22A and Fig. 22B is a schematic diagram of heat dissipation according to some embodiments of the present disclosure;

[0013] Fig.23 is a cross-sectional view of a semiconductor device according to some embodiments of the present disclosure.

[0014]

Explanation of symbols

[0015] 10: CFET

[0016] 100, 200, 400, 500, 700: substrate

[0017] 100P:Semiconductor Strip

[0018] 102: semiconductor channel layer (semiconductor layer)

[0019] 104, 204, 402, 404, 405, 502, 504, 600: semiconductor layer

[0020] 106, 150, 250: Isolation structure

[0021] 107, 190, 207, 407, 730: high kappa layer

[0022] 108, 109, 208, 408, 710, 720, 735: dielectric layer

[0023] 110, 410: multi-layer heat dissipation

[0024] 115: Spacer

[0025] 116: Internal spacer

[0026] 117: Isolation layer

[0027] 130: dummy gate structure

[0028] 132: Dummy gate dielectric

[0029] 134: dummy gate electrode

[0030] 140: Source / drain epitaxial structure

[0031] 142: Epitaxial layer

[0032] 152, 252: interlayer dielectric layer

[0033] 155, 255: contact etching stop layer

[0034] 170: Gate structure

[0035] 172, 272: Interface layer

[0036] 174, 274: Gate dielectric layer

[0037] 176, 276: gate electrode

[0038] 202: semiconductor channel layer (semiconductor layer)

[0039] 240: Source / drain epitaxial structure

[0040] 270: Gate structure

[0041] 330: First hard mask

[0042] 332: Second hard mask

[0043] 602, 604: bonding layer

[0044] 610:Internal structure

[0045] 620: Dorsal internal connection structure

[0046] 715, 725: Etching stop layer

[0047] 740, 750: Conductive vias

[0048] AA, BB, CC: Line

[0049] FN: Fin-shaped structure

[0050] HM1: Hard Mask

[0051] MA1: Patterned Mask

[0052] M1: The first high kappa material

[0053] M2: The second highest kappa material

[0054] M3: Bridging material

[0055] ST: Stacking

[0056] ST1, ST3: First stack

[0057] ST2, ST4: Second stack

[0058] TR1, TR2: Transistor

[0059] ω D1 :First phonon frequency range

[0060] ω D2 : Second phonon frequency range DETAILED DESCRIPTION

[0061] The following disclosure provides many different embodiments or examples for realizing the different features of the provided subject matter. The specific examples of components and configurations described below are for simplifying the disclosure. Of course, these are only examples and are not intended to be limiting. For example, in the following description, forming a first feature above or on a second feature may include an embodiment in which the first feature and the second feature are directly contacted, and may also include an embodiment in which an additional feature may be formed between the first feature and the second feature so that the first feature and the second feature may not be directly in contact. In addition, the disclosure may repeat reference numerals and / or letters in various examples. This repetition is for the purpose of simplicity and clarity, and does not itself indicate the relationship between the various embodiments and / or configurations discussed.

[0062] Additionally, for ease of description, spatially relative terms such as "below," "beneath," "lower," "above," "upper," and the like may be used herein to describe the relationship of one element or feature to another element or feature as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein should be interpreted accordingly.

[0063] The gate all around (GAA) transistor structure may be patterned by any suitable method. For example, the structure may be patterned using one or more lithography processes, including double patterning or multi-patterning processes. In general, the double patterning or multi-patterning process combines lithography and self-alignment processes, thereby allowing the formation of patterns having, for example, a smaller pitch than that which can be obtained using a single direct lithography process. For example, in one embodiment, a sacrificial layer is formed over a substrate and a lithography process is used to pattern the sacrificial layer. A self-alignment process is used to form spacers next to the patterned sacrificial layer. The sacrificial layer is then removed, and the remaining spacers may then be used to pattern the GAA structure.

[0064] Figure 11 is a perspective view of a semiconductor device according to some embodiments of the present disclosure. In the present disclosure, a complementary FET (CFET) 10 is provided, and a method of manufacturing the same will be disclosed in the following discussion. In the CFET 10, a first transistor TR1 is disposed above a substrate (not shown), and a second transistor TR2 is disposed vertically above the first transistor TR1. In some embodiments, the first transistor TR1 and the second transistor TR2 may be field effect transistors (FETs), and both may include a gate-all-around (GAA) configuration, and thus the first transistor TR1 and the second transistor TR2 may also be referred to as GAA FETs. The first transistor TR1 includes first semiconductor channel layers 102 vertically stacked on each other, a first metal gate structure 170 surrounding each of the first semiconductor channel layers 102, and a first source / drain epitaxial structure 140 located at opposite ends of each of the first semiconductor channel layers 102. Similarly, the second transistor TR2 includes second semiconductor channel layers 202 vertically stacked on each other, a second metal gate structure 270 surrounding each of the second semiconductor channel layers 202, and a second source / drain epitaxial structure 240 located on opposite ends of each of the second semiconductor channel layers 202. The first metal gate structure 170 may include an interface layer 172, a gate dielectric layer 174, and a gate electrode 176. Similarly, the second metal gate structure 270 may include an interface layer 272, a gate dielectric layer 274, and a gate electrode 276. In some embodiments, the first transistor TR1 has a first conductivity type (e.g., p-type), and the second transistor TR2 has a second conductivity type different from the first conductivity type (e.g., n-type). In some embodiments, the first transistor TR1 may be referred to as a P-FET, and the second transistor TR2 may be referred to as an N-FET.

[0065] For CFET devices, heat dissipation becomes important, and high-kappa materials are often used in stacked devices such as CFETs. However, due to the phonon frequency mismatch, conventional high-kappa materials may suffer from high thermal boundary resistance between interfaces of different high-kappa materials. To address this problem, embodiments of the present disclosure provide a heat dissipation multilayer comprising a first high-kappa layer and a second high-kappa layer. The heat dissipation multilayer may also include a dielectric layer located between the first high-kappa layer and the second high-kappa layer. The dielectric layer may act as a bridging layer located between the first high-kappa layer and the second high-kappa layer so as to reduce the thermal boundary resistance between the first high-kappa layer and the second high-kappa layer. Thus, the heat dissipation of the device may be improved.

[0066] Figures 2 to 8BThe method of forming a semiconductor device in various stages according to some embodiments of the present disclosure is described. It should be noted that Figure 2 , Figure 3 , Figure 4 , Figure 5A , Fig. 6A , Fig. 7A and Fig. 8A Contains and along Figure 1 The cross-sectional view of line AA is the same as the cross-sectional view. Figure 5B , Figure 6B and Figure 7B Contains and along Figure 1 The cross-sectional view of line BB is the same as the cross-sectional view. Figure 8B Contains and along Figure 1 The cross-sectional view of line CC is the same as the cross-sectional view. Figures 2 to 8B Although described as a series of actions, it should be understood that these actions are not limiting, because the order of the actions can be changed in other embodiments, and the disclosed method is also applicable to other structures. In other embodiments, some of the actions illustrated and / or described can be omitted in whole or in part. It should be noted that Figures 2 to 8B Some elements of Figure 1 The elements described herein and therefore, for the sake of brevity, the relevant details will not be repeated.

[0067] refer to Figure 2 . Substrates 100 and 200 are shown. In general, substrates 100 and 200 may include bulk semiconductor substrates or silicon-on-insulator (SOI) substrates. The SOI substrate includes an insulator layer below a thin semiconductor layer, which is an active layer of the SOI substrate. The semiconductor of the active layer and the bulk semiconductor typically include crystalline semiconductor material silicon, but may include one or more other semiconductor materials, such as germanium, silicon-germanium alloys, compound semiconductors (e.g., GaAs, AlAs, InAs, GaN, AlN, and the like), or alloys thereof (e.g., Ga x Al 1-x As、Ga x Al 1-x N、In x Ga 1-x As and the like), oxide semiconductors (such as ZnO, SnO2, TiO2, Ga2O3 and the like), or combinations thereof. The semiconductor material may be doped or undoped. Other substrates that may be used include multilayer substrates, gradient substrates, or hybrid orientation substrates.

[0068] With respect to the substrate 100, a first stack ST1 of alternating semiconductor layers 102 and 104 is formed over the substrate 100. Next, a high-kappa layer 107 is formed over the first stack ST1, and a dielectric layer 108 is formed over the high-kappa layer 107. In more detail, the high-kappa layer 107 is in contact with the topmost semiconductor layer 102.

[0069] On the other hand, with respect to the substrate 200, a second stack ST2 of alternating semiconductor layers 202 and 204 is formed over the substrate 200. Next, a high-kappa layer 207 is formed over the second stack ST2, and a dielectric layer 208 is formed over the high-kappa layer 207. In more detail, the high-kappa layer 207 is in contact with the topmost semiconductor layer 202.

[0070] In some embodiments, semiconductor layers 102 and 202 may be made of pure silicon layers without germanium. In some embodiments, semiconductor layers 102 and 202 may also be substantially pure silicon layers, for example, with a germanium percentage less than about 1 percent. Semiconductor layers 104 and 204 may be made of silicon germanium. For example, the germanium percentage (atomic percentage concentration) of semiconductor layers 104 and 204 may be in the range of about 20 percent to about 60 percent. In some embodiments, semiconductor layers 102, 104, 202, and 204 may be deposited using a suitable deposition process such as selective epitaxial growth (SEG), chemical vapor deposition (CVD), molecular beam epitaxy (MBE), or other suitable processes. In some embodiments, semiconductor layers 104 and 204 may be removed during a replacement gate (RPG) process, and thus semiconductor layers 104 and 204 may also be referred to as sacrificial layers.

[0071] Here, the term "high kappa layer" may refer to a layer with a higher thermal conductivity (kappa; κ). For example, in some embodiments, the high kappa layers 107 and 207 may include a high kappa material having a thermal conductivity greater than about 10 W / m*K. The thermal conductivity of the high kappa material ranges from about 10 W / m*K to about 2000 W / m*K. The high kappa material may include a nitride, such as aluminum nitride (AlN), boron nitride (BN), or the like. The high kappa material may also include a metal oxide, such as yttrium oxide (Y2O3), yttrium aluminum garnet (yttrium aluminum garnet, YAG; Y3Al5O 12), aluminum oxide (Al2O3), beryllium oxide (BeO), or the like. The high-kappa material may also include carbides, such as silicon carbide (SiC) or the like. The high-kappa material may also include graphene, diamond-like carbon (DLC), diamond, or the like. In some embodiments, the high-kappa layers 107 and 207 may include a crystalline structure and may also be referred to as a crystalline layer. In some embodiments, the high-kappa layers 107 and 207 are made of different high-kappa materials.

[0072] In some embodiments, the dielectric layers 108 and 208 may be made of silicon oxide (SiO2), silicon nitride (SiN), silicon carbide (SiC), or the like. In some embodiments, the dielectric layers 108 and 208 have a lower thermal conductivity than the high kappa layers 107 and 207. For example, if the dielectric layers 108 and 208 are made of silicon oxide (SiO2), the thermal conductivity of SiO2 is about 1 W / m*K. In some embodiments, the dielectric layers 108 and 208 may be made of the same dielectric material or may be made of different dielectric materials. In some embodiments, the dielectric layers 108 and 208 may include an amorphous structure and may also be referred to as an amorphous layer. The dielectric layers 108 and 208 may reduce the thermal boundary resistance between the high kappa layers 107 and 207 after the bonding process (see Figure 3 ), which helps to improve the heat dissipation of the device.

[0073] In some embodiments, each of the high-kappa layers 107 and 207 may include a thickness in a range of about 0.5 nm to about 50 nm. If the thickness of the high-kappa layers 107 and 207 is too thin (e.g., much less than 0.5 nm), the high-kappa layers 107 and 207 may not provide sufficient heat dissipation capabilities. If the thickness of the high-kappa layers 107 and 207 is too thick (e.g., much greater than 50 nm), there is no additional benefit for heat dissipation. In some embodiments, each of the dielectric layers 108 and 208 may include a thickness in a range of about 10 nm to about 50 nm. to about If the thickness of dielectric layers 108 and 208 is too thin (e.g., much less than ), the dielectric layers 108 and 208 may not be able to sufficiently reduce the thermal boundary resistance between the high kappa layers 107 and 207. If the thickness of the dielectric layers 108 and 208 is too thick (e.g., much greater than ), the thermal conductivity may be reduced and will degrade the heat dissipation between the high-kappa layers 107 and 207. In some embodiments, the high-kappa layers 107 and 207 may be thicker than the dielectric layers 108 and 208.

[0074] refer to Figure 3The substrates 100 and 200 are bonded to each other. For example, Figure 3 In the embodiment, the substrate 200 is flipped 180 degrees, so that the dielectric layer 208 on the substrate 200 faces the dielectric layer 108 on the substrate 100 .

[0075] Next, the dielectric layers 108 and 208 are bonded to each other using a suitable technique. In some embodiments, the bonding process may further include applying a surface treatment to the surfaces of the dielectric layers 108 and 208, respectively. The surface treatment may include a plasma treatment. The plasma treatment may be performed in a vacuum environment. After the plasma treatment, the surface treatment may further include a cleaning process (e.g., rinsing with deionized water or the like), which may be applied to the dielectric layers 108 and 208. The dielectric layers 108 and 208 are pressed against each other to initiate pre-bonding of the substrates 100 and 200. The pre-bonding may be performed at room temperature (between about 21 degrees and about 25 degrees). After the pre-bonding, an annealing process may be applied to the dielectric layers 108 and 208 that have been pressed against each other. The annealing process causes the bonding force between the dielectric layers 108 and 208 to increase, so that even if the dielectric layers 108 and 208 are no longer subjected to the pressing force, they will not delaminate or peel off from each other. In some embodiments, the dielectric layers 108 and 208 may also be referred to as bonding layers in the bonding process. In some embodiments, high-kappa layers 107 and 207 and dielectric layers 108 and 208 may be collectively referred to as a bonding structure.

[0076] refer to Figure 4 The back side of the substrate 200 is subjected to a grinding process so as to reduce the thickness of the substrate 200 to a desired thickness. The remaining portion of the substrate 200 may also serve as a channel layer in a semiconductor device, and thus the remaining portion of the substrate 200 may also be referred to as a semiconductor layer 202. For example, the remaining portion of the substrate 200 has substantially the same thickness as the underlying semiconductor layer 202.

[0077] It should be noted that for simplicity, Figure 3 The dielectric layers 108 and 208 are Figure 4 1 and 2. The high kappa layers 107 and 207 are illustrated as a single dielectric layer 109. Here, the first stack ST1, the second stack ST2, the high kappa layers 107 and 207, and the dielectric layer 109 may be collectively referred to as a stack ST. Each of the high kappa layers 107 and 207 may be referred to as a heat dissipation layer. In addition, the high kappa layers 107 and 207 and the dielectric layer 109 may be collectively referred to as a heat dissipation multilayer 110, and will be discussed below.

[0078] refer to Figure 5A and Figure 5BThe stack ST and the substrate 100 are subjected to a patterning process to form a fin-shaped structure FN. In some embodiments, the patterning process may include forming a patterned photoresist layer over the stack ST, and then performing an etching process to remove the stack ST and the non-required portions of the substrate 100 exposed by the patterned photoresist layer. The fin-shaped structure FN may include the remaining portion of the stack ST and the semiconductor strip 100P protruding over the substrate 100. In some embodiments, the etching process may include wet etching, dry etching, or the like.

[0079] After forming the fin structure FN, an isolation structure 106 is formed above the substrate 100 and laterally surrounds the fin structure FN. In some embodiments, the isolation structure 106 may contact the sidewalls of the semiconductor strip 100P of the substrate 100. The isolation structure 106 may be a shallow trench isolation (STI) structure, a suitable isolation structure, a combination of the foregoing, or the like. In some embodiments, the isolation structure 106 may be made of oxide (e.g., silicon oxide), nitrogen (e.g., silicon nitride), or a combination thereof.

[0080] refer to Fig. 6A and Figure 6B . The dummy gate structures 130 are formed over the substrate 100 and across the fin structure FN. In some embodiments, each of the dummy gate structures 130 includes a dummy gate dielectric 132 and a dummy gate electrode 134 located over the dummy gate dielectric 132. The dummy gate dielectric 132 may be, for example, silicon oxide, silicon nitride, a combination thereof, or the like, and may be deposited or thermally grown according to acceptable techniques. The dummy gate electrode 134 may be a conductive or non-conductive material and may be selected from the group consisting of: amorphous silicon, polycrystalline silicon (poly-Si), polycrystalline silicon germanium (poly-SiGe), metal nitride, metal silicide, metal oxide, and metal.

[0081] The dummy gate electrode 134 and the dummy gate dielectric 132 may be formed by, for example, depositing a dummy dielectric layer and a dummy gate layer over the substrate 100, forming a patterned mask MA1 over the dummy gate layer, and then performing an etching process on the dummy dielectric layer and the dummy gate layer by using the patterned mask MA1 as an etching mask. In some embodiments, the dummy gate electrode 134 may be deposited by physical vapor deposition (PVD), chemical vapor deposition (CVD), sputtering deposition, or other techniques for depositing selected materials. In some embodiments, the dummy gate dielectric 132 may be formed by thermal oxidation.

[0082] In some embodiments, each of the patterned masks MA1 includes a first hard mask 330 and a second hard mask 332 located above the first hard mask 330. The first hard mask 330 and the second hard mask 332 may be made of different materials. In some embodiments, the first hard mask 330 may be formed of silicon nitride, and the second hard mask 332 may be formed of silicon oxide.

[0083] Spacers 115 are formed on opposite sidewalls of each of the dummy gate structures 130 (see Fig. 6A ) and formed on opposite sidewalls of the fin structure FN (see Figure 6B ). In some embodiments, the portion of the spacer 115 on the opposite sidewalls of each of the dummy gate structures 130 may be referred to as a gate spacer, and the portion of the spacer 115 on the opposite sidewalls of the fin structure FN may be referred to as a fin spacer. In some embodiments, the spacer 115 may be formed of silicon oxide, silicon nitride, silicon oxynitride, or a combination thereof. In some embodiments, the spacer 115 may be formed by, for example, blanket depositing a spacer layer over a substrate, and then performing an anisotropic etching process to remove a horizontal portion of the spacer layer, so that a vertical portion of the spacer layer remains on the sidewalls of the dummy gate structure 130 and on the sidewalls of the fin structure FN. In some embodiments, the remaining vertical portion of the spacer layer may be referred to as a spacer 115. The spacer layer may be deposited using techniques such as CVD, ALD, or the like.

[0084] refer to Fig. 7A and Figure 7B An etching process is performed by using the dummy gate structure 130 and the spacer 115 as an etching mask to remove a portion of the fin structure FN (or the stack ST), thereby forming a source / drain opening in the fin structure FN (or in the stack ST). In some embodiments, the etching process may be wet etching, dry etching, or a combination thereof.

[0085] The semiconductor layer 104 and the semiconductor layer 204 are laterally etched to form sidewall grooves. Similarly, the heat dissipation multilayer 110 is laterally etched to form sidewall grooves. In some embodiments, an isotropic etching process such as wet etching or the like may be used to etch the sidewalls of the semiconductor layers 104 and 204. In some embodiments where the semiconductor layers 104 and 204 include, for example, SiGe, and the semiconductor layers 102 and 202 include, for example, Si, an etching process performed via tetramethylammonium hydroxide (TMAH), ammonium hydroxide (NH4OH), or the like may be used to etch the sidewalls of the semiconductor layers 104 and 204. On the other hand, a suitable etchant may be used to etch the heat dissipation multilayer 110. In some embodiments, a first etching process is performed to etch the semiconductor layers 104 and 204, and a second etching process is performed to etch the heat dissipation multilayer 110. The first etching process may be performed before or after the second etching process.

[0086] Subsequently, internal spacers 116 are formed in the sidewall recesses on opposite ends of each of the semiconductor layer 104, the semiconductor layer 204, and the heat dissipation multilayer 110. The internal spacers 116 may be deposited by a conformal deposition process such as CVD, ALD, or the like. The dielectric layer may include materials such as SiN, SiOCN, SiCN, SIOC, but any suitable material may be utilized, such as a low dielectric constant (low-k) material having a k value of less than about 3.5. In some embodiments, opposite ends of the heat dissipation multilayer 110 are in contact with respective internal spacers 116.

[0087] The epitaxial layer 142 is formed at the bottom of the source / drain openings, and then the first source / drain epitaxial structure 140 is formed on the epitaxial layer 142, respectively. In some embodiments, forming the epitaxial layer 142 may include a plurality of deposition cycles, wherein each deposition cycle may include a selective epitaxial growth (SEG) process and an etching process. The first source / drain epitaxial structure 140 may be formed by a suitable deposition process such as a selective epitaxial growth (SEG) process. In some embodiments, the SEG process may selectively grow semiconductor materials on exposed semiconductor surfaces such as the exposed surface of the epitaxial layer 142 and the exposed surface of the semiconductor layer 102. In some embodiments, an implantation process may be performed on the first source / drain epitaxial structure 140. For example, the implantation process may include a p-type dopant, such as boron (B), gallium (Ga), indium (In), aluminum (Al), or the like, so that the first source / drain epitaxial structure 140 is a p-type epitaxial structure. In some embodiments, the epitaxial layer 142 may be formed without performing an implantation process, and thus the epitaxial layer 142 is undoped.

[0088] The contact etch stop layer 155 is formed to cover the first source / drain epitaxial structure 140. Subsequently, the interlayer dielectric layer 152 is formed over the contact etch stop layer 155. An etch-back process may be performed to lower the top surface of the contact etch stop layer 155 and the interlayer dielectric layer 152 so that the sidewall of the semiconductor layer 202 is exposed through the source / drain opening. In some embodiments, the contact etch stop layer 155 and the interlayer dielectric layer 152 may be collectively referred to as an isolation structure 150. In some embodiments, the topmost semiconductor layer 102 and the bottommost semiconductor layer 202 are in contact with the contact etch stop layer 155 of the isolation structure 150.

[0089] In some embodiments, the contact etch stop layer 155 may be a dielectric layer including silicon nitride, silicon oxynitride, or other suitable materials. In some embodiments, the interlayer dielectric layer 152 may include silicon oxide, silicon nitride, silicon oxynitride, tetraethoxysilane (TEOS), phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), low-k dielectric materials, and / or other suitable dielectric materials. Examples of low-k dielectric materials include, but are not limited to, fluorinated silica glass (FSG), carbon-doped silicon oxide, amorphous fluorinated carbon, polyparaxylene, bis-benzocyclobutene (BCB), or polyimide. The contact etch stop layer 155 and the interlayer dielectric layer 152 may be formed using, for example, CVD, ALD, or other suitable techniques.

[0090] The second source / drain epitaxial structure 240 is formed on opposite ends of each of the semiconductor layers 202. In some embodiments, the second source / drain epitaxial structure 240 may be formed by a selective epitaxial growth (SEG) process. The SEG process may selectively grow semiconductor material on an exposed semiconductor surface such as an exposed surface of the semiconductor layer 202. In some embodiments, an implantation process may be performed on the second source / drain epitaxial structure 240. For example, the implantation process may include an n-type dopant, such as phosphorus (P), arsenic (As), or antimony (Sb), or the like, so that the second source / drain epitaxial structure 240 is an n-type epitaxial structure.

[0091] The contact etch stop layer 255 is formed to cover the second source / drain epitaxial structure 240, and the interlayer dielectric layer 252 is formed above the contact etch stop layer 255. Then, a planarization process such as CMP is performed to remove excess material of the contact etch stop layer 255 and the interlayer dielectric layer 252 until the dummy gate structure 130 is exposed. In some embodiments, the patterned mask MA1 is removed during the planarization process. In some embodiments, the contact etch stop layer 255 and the interlayer dielectric layer 252 may be collectively referred to as an isolation structure 250. The materials of the contact etch stop layer 255 and the interlayer dielectric layer 252 may be similar to the materials of the contact etch stop layer 155 and the interlayer dielectric layer 152, respectively, and therefore, for the sake of brevity, the relevant details will not be repeated. In some embodiments, the isolation structures 150 and 250 may form a composite isolation structure together.

[0092] refer to Fig. 8A and Figure 8B The dummy gate structure 130 is removed to form a gate trench between each pair of spacers 115 . Next, an etching process is performed to remove the semiconductor layers 104 and 204 through the gate trenches, so that the semiconductor layers 102 and 202 are suspended above the substrate 100 .

[0093] Interfacial layers 172 and 272 are respectively formed on the exposed surfaces of semiconductor layers 102 and 202. Next, gate dielectric layers 174 and 274 are respectively formed over interfacial layers 172 and 272. In some embodiments, the interfacial layers 172 and 272 may be formed using the same deposition process, and the gate dielectric layers 174 and 274 may be formed using the same deposition process.

[0094] After forming the interface layers 172 and 272 and the gate dielectric layers 174 and 274, the gate electrode 176 is formed in the gate trench and over the gate dielectric layer 174. The gate electrode 176 is then etched back. In some embodiments, the top surface of the gate electrode 176 may be lower than the bottom surface of the heat dissipation multilayer 110.

[0095] Thus, the first metal gate structures 170 are formed. Each of the first metal gate structures 170 may include an interface layer 172, a gate dielectric layer 174 located above the interface layer 172, and a gate electrode 176 located above the gate dielectric layer 174. The first metal gate structures 170 may surround respective semiconductor layers 102.

[0096] In some embodiments, the interfacial layers 172 and 272 may be made of an oxide such as aluminum oxide (Al2O3), silicon oxide (SiO2), or the like. In some embodiments, the gate dielectric layers 174 and 274 may include a high-k dielectric. Examples of high-k dielectric materials include HfO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, zirconium oxide, aluminum oxide, titanium oxide, hafnium dioxide-aluminum oxide (HfO2-Al2O3) alloys, other suitable high-k dielectric materials, and / or combinations thereof.

[0097] The gate electrode 176 may include a work function metal layer and a fill metal. The work function metal layer may be an n-type or p-type work function layer. Exemplary p-type work function metals include TiN, TaN, Ru, Mo, Al, WN, ZrSi2, MoSi2, TaSi2, NiSi2, WN, other suitable p-type work function materials, or combinations thereof. Exemplary n-type work function metals include Ti, Ag, TaAl, TaAlC, TiAlN, TaC, TaCN, TaSiN, Mn, Zr, other suitable n-type work function materials, or combinations thereof. The work function layer may include multiple layers. The fill metal may include tungsten (W), aluminum (Al), copper (Cu), or another suitable conductive material.

[0098] like Figure 8B As shown in the cross-sectional view of , a high-kappa layer 190 is formed above the gate electrode 176. The high-kappa layer 190 may be in contact with the heat dissipation multilayer 110. In some embodiments, the high-kappa layer 190 may also be referred to as a heat dissipation layer. The high-kappa layer 190 may be formed by, for example, the following steps: a high-kappa material is deposited in the gate trench, and then the high-kappa material is etched back so that the top surface of the kappa material is lowered to a desired position. For example, the top surface of the high-kappa layer 190 is lower than the top surface of the bottommost semiconductor layer 202. In some embodiments, the high-kappa layer 190 may include a high-kappa material similar to the materials of the high-kappa layers 107 and 207 described above, and therefore, for the sake of brevity, the relevant details will not be repeated.

[0099] The gate electrode 276 is formed in the gate trench and is formed over the first metal gate structure 170. Thus, a second metal gate structure 270 is formed. Each of the second metal gate structures 270 may include an interface layer 272, a gate dielectric layer 274 over the interface layer 272, and a gate electrode 276 over the gate dielectric layer 274. The second metal gate structure 270 may surround a respective semiconductor layer 202. The material of the gate electrode 276 may be similar to that described with respect to the gate electrode 176, and therefore, for the sake of brevity, the relevant details will not be repeated.

[0100] like Figure 8B , gate electrode 276 is in contact with the top surface of high kappa layer 190. That is, gate electrode 176 is vertically separated from overlying gate electrode 276 by high kappa layer 190. High kappa layer 190 may serve as an isolation layer between gate electrodes 176 and 276, and may also serve as a heat dissipation layer between gate electrodes 176 and 276. In some embodiments, high kappa layer 190 may contact the sidewalls of heat dissipation multilayer 110.

[0101] The second metal gate structure 270 is then etched back so that the top surface of the second metal gate structure 270 is lower than the top surface of the gate spacer 115. Subsequently, hard masks HM1 are formed on the second metal gate structures 270, respectively. In some embodiments, the hard masks HM1 may include one or more layers of dielectric materials, such as silicon nitride-based materials, including SiN, SiCN, and SiOCN. The hard masks HM1 may be formed by, for example, the following steps: a dielectric layer is deposited on the etched back second metal gate structure 270, and then a planarization process such as CMP is performed on the dielectric layer until the isolation structure 250 is exposed.

[0102] The first metal gate structure 170, the first source / drain epitaxial structure 140 on the opposite side of the first metal gate structure 170, and the semiconductor layer 102 in contact with the first source / drain epitaxial structure 140 may be used together as Figure 1 In this case, the semiconductor layer 102 in contact with the first source / drain epitaxial structure 140 may also be referred to as the channel layer of the first transistor TR1. Similarly, the second metal gate structure 270, the second source / drain epitaxial structure 240 located on the opposite side of the second metal gate structure 270, and the semiconductor layer 202 in contact with the second source / drain epitaxial structure 240 may be used together as a transistor. Figure 1 In this case, the semiconductor layer 202 in contact with the second source / drain epitaxial structure 240 may also be referred to as a channel layer of the second transistor TR2. Fig. 8A , opposite ends of the topmost semiconductor layer 102 are in contact with the isolation structure 150, but are not in contact with the first source / drain epitaxial structure 140. Therefore, the topmost semiconductor layer 102 may not be used as a channel layer of the first transistor TR1. Similarly, opposite ends of the bottommost semiconductor layer 202 are in contact with the isolation structure 150, but are not in contact with the second source / drain epitaxial structure 240. Therefore, the bottommost semiconductor layer 202 may not be used as a channel layer of the second transistor TR2.

[0103] In some embodiments of the present disclosure, the heat dissipation multilayer 110 is integrated into the CFET structure, and the heat dissipation multilayer 110 includes the high kappa layer 107 and the high kappa layer 207. In more detail, the heat dissipation multilayer 110 is formed between the first transistor TR1 and the second transistor TR2, which is beneficial to the heat dissipation between the first transistor TR1 and the second transistor TR2 and will be discussed below.

[0104] In some embodiments where high-kappa layers 107 and 207 are made of different high-kappa materials, if high-kappa layers 107 and 207 are in contact with each other, high-kappa layers 107 and 207 may experience high thermal boundary resistance at the interface due to phonon frequency mismatch. In some embodiments, phonon frequency mismatch refers to a situation where the phonon frequencies of two adjacent materials in a device do not match, resulting in an interface mismatch or discontinuity between the two materials. Phonons are quantum mechanical vibrations in a lattice that are used to transport energy and heat between adjacent materials. When two adjacent materials have different phonon frequencies, a mismatch or discontinuity at the interface may result, which may cause a range of effects, including phonon scattering, reduced thermal conductivity, and increased thermal resistance.

[0105] For example, Fig.21A and Fig. 21B As shown in FIG. 1 , a first high kappa material M1 is in contact with a second high kappa material M2 (see Fig. 21B ). The first high-kappa material M1 and the second high-kappa material M2 are made of different high-kappa materials and may include different crystal structures, which allow phonons to be transmitted at a specific frequency. For example, Fig.21A As shown in FIG. , the first high kappa material M1 may allow phonons to travel in a first phonon frequency range ω D1 transmission, while the second high kappa material M2 allows phonons to travel in the same frequency range as the first phonon ω D1 Different second phonon frequency ranges ω D2 Therefore, if Fig. 21B As shown in FIG. 1 , in this case, due to the phonon frequency mismatch, phonon reflection may occur at the interface between the first high kappa material M1 and the second high kappa material M2. This will affect the heat dissipation from the second high kappa material M2 to the first high kappa material M1, and thus will increase the thermal boundary resistance at the interface between the first high kappa material M1 and the second high kappa material M2.

[0106] Therefore, embodiments of the present disclosure include inserting a dielectric layer 109 including an amorphous structure between high-kappa layers 107 and 207. Dielectric layer 109 may act as a bridge layer between high-kappa layers 107 and 207 and improve heat dissipation between high-kappa layers 107 and 207.

[0107] For example, Fig.22A and Fig. 22B As shown in FIG. 1 , the bridging material M3 is inserted between the first high kappa material M1 and the second high kappa material M2 (see FIG. 1 ). Fig. 22B ). The bridging material M3 is made of a dielectric material having an amorphous structure, which allows phonons to be transmitted in a wider bandwidth phonon frequency range. For example, Fig.22A As shown in FIG, the bridging material M3 allows phonons to be transmitted with a broadened bandwidth, which is consistent with the first phonon frequency range ω D1 and the second phonon frequency range ω D2 Overlap. Therefore, heat can be successfully transferred from the second high kappa material M2 to the first high kappa material M1 via the bridging material M3 without frequency mismatch issues. The phonon frequency range of a given material (e.g., the first high kappa material M1, the second high kappa material M2, or the bridging material M3) can be detected or measured by using various techniques such as Raman spectroscopy, Bridging scattering, inelastic neutron scattering, infrared spectroscopy, ultrasonic measurement, or other suitable techniques.

[0108] Therefore, by using the dielectric layer 109 , heat dissipation between the high-kappa layers 107 and 207 and between the first transistor TR1 and the second transistor TR2 can be improved.

[0109] Fig. 9 A semiconductor device according to some embodiments of the present disclosure is described. It should be noted that Fig. 9 With Fig. 8A Same cross-section view. Fig. 9 Some of the elements described in Figures 2 to 8B Elements described herein are labeled identically and the related details will not be repeated for the sake of brevity.

[0110] Fig. 9 Examples and Fig. 8A The difference between the embodiments is that the heat dissipation multilayer 110 is Fig. 7A and Figure 7B Therefore, opposite ends of the heat dissipation multilayer 110 may contact the isolation structure 150. In some embodiments, the sidewalls of the heat dissipation multilayer 110 may be vertically aligned with the sidewalls of the topmost semiconductor layer 102 and the sidewalls of the bottommost semiconductor layer 202.

[0111] Figures 10 to 20 The method of forming a semiconductor device in various stages according to some embodiments of the present disclosure is described. It should be noted that Fig.10 , Fig.11 , Fig.12 , Fig.13A , Fig.14A , Fig.15A , Fig.16A , Fig.17 , Fig.18 , Fig.19 , Fig. 20 Contains and along Figure 1 The cross-sectional view of line AA is the same as the cross-sectional view. Fig. 13B , Fig. 14B , Fig. 15B , Fig. 16B Contains and along Figure 1 The cross-sectional view of line BB is the same as the cross-sectional view. It should be noted that Figures 10 to 20 Some elements of Figure 1 and Figures 2 to 8B Elements described herein are labeled identically and the related details will not be repeated for the sake of brevity.

[0112] refer to Fig.10 . A substrate 400 and a substrate 500 are shown. The materials of the substrates 400 and 500 may be similar to the materials of the substrates 100 and 200 described above, and therefore, for the sake of brevity, the relevant details will not be repeated.

[0113] A semiconductor stack ST is formed over a substrate 400. The semiconductor stack ST includes a first stack ST3 of alternating semiconductor layers 402 and 404, a semiconductor layer 405 disposed over the first stack ST3, and a second stack ST4 of alternating semiconductor layers 502 and 504 over the semiconductor layer 405. In some embodiments, the semiconductor layers 402 and 502 may be made of pure silicon layers that do not contain germanium. The semiconductor layers 402 and 502 may also be substantially pure silicon layers having, for example, a germanium percentage lower than about 1 percent. The semiconductor layers 404, 405, and 504 may be made of silicon germanium, and the semiconductor layer 405 may include a higher germanium composition than the semiconductor layers 404 and 504. For example, the germanium percentage (atomic percentage concentration) of the semiconductor layer 405 is in the range of about 60 percent to about 80 percent, and the germanium percentage (atomic percentage concentration) of the semiconductor layers 404 and 504 is in the range of about 20 percent to about 40 percent. In some embodiments, semiconductor layers 402, 404, 405, 502, and 504 may be deposited using a suitable deposition process such as selective epitaxial growth (SEG), chemical vapor deposition (CVD), molecular beam epitaxy (MBE), or other suitable processes. In some embodiments, semiconductor layers 404 and 504 may be removed during a replacement gate (RPG) process, and thus semiconductor layers 404 and 504 may also be referred to as sacrificial layers.

[0114] A high-kappa layer 407 is formed over the stacked ST. In more detail, the high-kappa layer 407 is formed on the topmost semiconductor layer 502. A dielectric layer 408 is formed over the high-kappa layer 407. In some embodiments, a suitable deposition process such as PVD, CVD, ALD, or the like may be used to form the high-kappa layer 407 and the dielectric layer 408. The material of the high-kappa layer 407 may be similar to the material of the high-kappa layers 107 and 207 as discussed above, and thus, for the sake of brevity, the relevant details will not be repeated. The material of the dielectric layer 408 may be similar to the material of the dielectric layers 108 and 208 as discussed above, and thus, for the sake of brevity, the relevant details will not be repeated.

[0115] A semiconductor layer 600 is formed over the dielectric layer 408. In some embodiments, the semiconductor layer 600 may be made of amorphous silicon (a-Si). Next, a bonding layer 602 is formed over the semiconductor layer 600. In some embodiments, the semiconductor layer 600 and the bonding layer 602 may be formed using a suitable deposition process such as PVD, CVD, ALD, or the like.

[0116] With respect to substrate 500, bonding layer 604 is formed over substrate 500. In some embodiments, bonding layer 604 may be formed using a suitable deposition process such as PVD, CVD, ALD, or the like. Bonding layers 602 and 604 may include a dielectric material such as silicon oxide (SiO x ), silicon dioxide (SiO2) or other suitable materials. In some embodiments, the bonding layers 602 and 604 may include the same bonding material. In other embodiments, the bonding layers 602 and 604 may include different bonding materials.

[0117] refer to Fig.11 The substrate 400 is bonded to the substrate 500. For example, Fig.11 In the embodiment, the substrate 400 is flipped 180 degrees so that the bonding layer 602 on the substrate 400 faces the bonding layer 604 on the substrate 500. Then, the bonding layers 602 and 604 are bonded to each other using a suitable technique. The bonding process is similar to that shown in FIG. Figure 4 The bonding process discussed in , and for the sake of brevity, the relevant details will not be repeated.

[0118] refer to Fig.12 A grinding process is performed on the back side of the substrate 400 to remove the substrate 400 until the topmost semiconductor layer 402 is exposed.

[0119] refer to Fig.13A and Fig. 13B The stacked ST, the high-kappa layer 407, the dielectric layer 408, the semiconductor layer 600, and the bonding layer 602 are patterned to form a fin-shaped structure. In some embodiments, the patterning process may include forming a patterned photoresist layer over the stacked ST, and then performing an etching process to remove the undesired portions of the stacked ST, the high-kappa layer 407, the dielectric layer 408, the semiconductor layer 600, and the bonding layer 602 exposed by the patterned photoresist layer. The fin-shaped structure may include the remaining portions of the stacked ST, the high-kappa layer 407, the dielectric layer 408, the semiconductor layer 600, and the bonding layer 602. In some embodiments, the etching process may include wet etching, dry etching, or the like.

[0120] After forming the fin structure, an isolation structure 106 is formed over the substrate 500 and laterally surrounds the fin structure. In some embodiments, the isolation structure 106 may contact the sidewalls of the high-kappa layer 407 , the dielectric layer 408 , the semiconductor layer 600 , and the bonding layer 602 .

[0121] refer to Fig.14A and Fig. 14BThe dummy gate structures 130 are formed over the substrate 100 and across the fin structure. In some embodiments, each of the dummy gate structures 130 includes a dummy gate dielectric 132 and a dummy gate electrode 134 over the dummy gate dielectric 132. In some embodiments, a patterned mask MA1 is disposed over the dummy gate structures 130. Spacers 115 are formed on opposite sidewalls of each of the dummy gate structures 130.

[0122] refer to Fig.15A and Fig. 15B An etching process is performed by using the dummy gate structure 130 and the spacer 115 as an etching mask to remove a portion of the fin structure (or the stacked ST), thereby forming a source / drain opening in the fin structure (or in the stacked ST). In some embodiments, the etching process may be wet etching, dry etching, or a combination thereof.

[0123] After forming the source / drain openings, the semiconductor layer 404 and the semiconductor layer 504 are laterally etched to form sidewall recesses. Similarly, the semiconductor layer 405 is laterally etched to form sidewall recesses. Subsequently, the inner spacer 116 is formed in the sidewall recesses on opposite ends of each of the semiconductor layer 404, the semiconductor layer 504, and the semiconductor layer 405.

[0124] The first source / drain epitaxial structure 140 is formed on opposite ends of each of the semiconductor layers 502, respectively. A contact etch stop layer 155 is formed to cover the first source / drain epitaxial structure 140, and an interlayer dielectric layer 152 is formed above the contact etch stop layer 155. The second source / drain epitaxial structure 240 is formed on opposite ends of each of the semiconductor layers 402. The contact etch stop layer 255 is formed to cover the second source / drain epitaxial structure 240, and an interlayer dielectric layer 252 is formed above the contact etch stop layer 255. Then, a planarization process such as CMP is performed to remove excess material of the contact etch stop layer 255 and the interlayer dielectric layer 252 until the dummy gate structure 130 is exposed. In some embodiments, the patterned mask MA1 is removed during the planarization process. In some embodiments, the contact etch stop layer 255 and the interlayer dielectric layer 252 may be collectively referred to as an isolation structure 250.

[0125] refer to Fig.16A and Fig. 16B. The dummy gate structure 130 is removed to form a gate trench between each pair of spacers 115. Next, the semiconductor layer 405 is replaced with the isolation layer 117. For example, an etching process is performed to remove the semiconductor layer 405, thereby forming a gap vertically between the topmost semiconductor layer 502 and the bottommost semiconductor layer 402. As mentioned above, because the semiconductor layer 405 has a higher germanium concentration than the semiconductor layers 402, 404, 502 and 504, the etchant can be appropriately selected so that the semiconductor layer 405 is selectively removed while leaving the semiconductor layers 402, 404, 502 and 504 substantially intact. Subsequently, an isolation material is formed in the gate trench and fills the gap. An anisotropic etching process is performed to remove the isolation material outside the gap, and the remaining portion of the isolation material in the gap is referred to as the isolation layer 117. The material of the isolation layer 117 can be similar to the internal spacer 116, and therefore, for the sake of brevity, the relevant details will not be repeated.

[0126] Next, an etching process is performed to remove the semiconductor layers 404 and 504 through the gate trenches, so that the semiconductor layers 402 and 502 are suspended above the substrate 100 .

[0127] Therefore, the gate structure 170 and the gate structure 270 are formed in the gate trench. The formation method of the gate structure 170 and the gate structure 270 is similar to the above-mentioned formation method, and for the sake of brevity, it will not be repeated. Each of the first metal gate structures 170 includes an interface layer 172, a gate dielectric layer 174 located above the interface layer 172, and a gate electrode 176 located above the gate dielectric layer 174. Each of the second metal gate structures 270 includes an interface layer 272, a gate dielectric layer 274 located above the interface layer 272, and a gate electrode 276 located above the gate dielectric layer 274.

[0128] The second metal gate structure 270 is then etched back so that the top surface of the second metal gate structure 270 is lower than the top surface of the gate spacer 115. Subsequently, hard masks HM1 are formed on the second metal gate structures 270, respectively.

[0129] The first metal gate structure 170, the first source / drain epitaxial structure 140 on the opposite side of the first metal gate structure 170, and the semiconductor layer 502 in contact with the first source / drain epitaxial structure 140 may be used together as Figure 1 In this case, the semiconductor layer 502 in contact with the first source / drain epitaxial structure 140 may also be referred to as the channel layer of the first transistor TR1. Similarly, the second metal gate structure 270, the second source / drain epitaxial structure 240 located on the opposite side of the second metal gate structure 270, and the semiconductor layer 402 in contact with the second source / drain epitaxial structure 240 may be used together as a transistor. Figure 1 In this case, the semiconductor layer 402 in contact with the second source / drain epitaxial structure 240 may also be referred to as a channel layer of the second transistor TR2. Fig.16A , opposite ends of the topmost semiconductor layer 502 are in contact with the isolation structure 150, but not in contact with the first source / drain epitaxial structure 140. Therefore, the topmost semiconductor layer 502 may not be used as a channel layer of the first transistor TR1. Similarly, opposite ends of the bottommost semiconductor layer 402 are in contact with the isolation structure 150, but not in contact with the second source / drain epitaxial structure 240. Therefore, the bottommost semiconductor layer 402 may not be used as a channel layer of the second transistor TR2.

[0130] refer to Fig.17 The interconnect structure 610 is formed above the isolation structure 250. In some embodiments, the interconnect structure 610 may include one or more dielectric layers and metal layers (not shown), wherein the metal layers may be electrically connected to underlying structures, such as the second metal gate structure 270, the second source / drain epitaxial structure 240, the first metal gate structure 170, and / or the first source / drain epitaxial structure 140.

[0131] refer to Fig.18 . Fig.17 The structure shown in FIG. 5 is flipped 180 degrees. Next, a grinding process is performed on the back side of the substrate 500 until the dielectric layer 408 is exposed. In some embodiments, the substrate 500, the bonding layers 602 and 604, and the semiconductor layer 600 are removed during the grinding process.

[0132] On the other hand, a substrate 700 is provided. A dielectric layer 710 is formed on the substrate 700. An etch stop layer 715 is formed on the dielectric layer 710. A dielectric layer 720 is formed on the etch stop layer 715. An etch stop layer 725 is formed on the dielectric layer 720. The etch stop layers 715 and 725 may be dielectric layers including silicon nitride, silicon oxynitride, or other suitable materials. In some embodiments, the dielectric layers 710 and 720 may include silicon oxide, silicon nitride, silicon oxynitride, tetraethoxysilane (TEOS), phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), low-k dielectric materials, and / or other suitable dielectric materials. Examples of low-k dielectric materials include, but are not limited to, fluorinated silica glass (FSG), carbon-doped silicon oxide, amorphous fluorinated carbon, parylene, bis-benzocyclobutene (BCB), or polyimide. In some embodiments, dielectric layers 710 and 720 and etch stop layers 715 and 725 may be formed using, for example, CVD, ALD, or other suitable techniques.

[0133] A high-kappa layer 730 is formed over the etch stop layer 725. Next, a dielectric layer 735 is formed over the high-kappa layer 730. The material of the high-kappa layer 730 may be similar to the material of the high-kappa layers 107 and 207 as discussed above, and thus, for the sake of brevity, the relevant details will not be repeated. The material of the dielectric layer 735 may be similar to the material of the dielectric layers 108 and 208 as discussed above, and thus, for the sake of brevity, the relevant details will not be repeated.

[0134] refer to Fig.19 The substrate 700 is flipped 180 degrees so that the dielectric layer 735 on the substrate 700 faces the dielectric layer 408. Next, the dielectric layers 408 and 735 are bonded to each other using a suitable technique. The bonding process of the dielectric layers 408 and 735 can be similar to that described above with respect to Figure 3 The bonding process of dielectric layers 108 and 208 described above is not described, and therefore, for the sake of brevity, the relevant details will not be repeated. After the bonding process is completed, high kappa layers 407 and 730 and dielectric layers 408 and 735 can be collectively referred to as heat dissipation multilayer 410. Each of high kappa layers 407 and 730 can be referred to as a heat dissipation layer. In some embodiments, dielectric layers 408 and 735 can be collectively referred to as dielectric layers.

[0135] refer to Fig. 20A grinding process is performed on the back side of the substrate 700 until the dielectric layer 710 is exposed. In some embodiments, the substrate 700 is removed during the grinding process.

[0136] In some embodiments of the present disclosure, a heat dissipation multilayer 410 is integrated into the CFET structure, and the heat dissipation multilayer 410 includes a high-kappa layer 407 and a high-kappa layer 730. In more detail, the heat dissipation multilayer 410 is formed between the CFET structure and the back-side interconnect structure 620, which facilitates heat dissipation between the CFET structure and the back-side interconnect structure 620. In some embodiments where the high-kappa layers 407 and 730 are made of different high-kappa materials, if the high-kappa layers 407 and 730 are in contact with each other, the high-kappa layers 407 and 730 may experience high thermal boundary resistance at the interface due to phonon frequency mismatch. Therefore, dielectric layers 408 and 735 are inserted between the high-kappa layers 407 and 730. The dielectric layers 408 and 735 may allow phonon transmission between the high-kappa layers 407 and 730 without frequency mismatch issues. Therefore, the heat dissipation between the high kappa layers 407 and 730 and the heat dissipation between the CFET structure and the backside interconnect structure 620 can be improved. The detailed mechanism has been described above with respect to FIG. 21A to FIG. 22B For the sake of brevity, the relevant details will not be repeated.

[0137] In addition, regarding Figures 10 to 20 In the process of manufacturing the semiconductor layer 600, the semiconductor layer 600 can act as a heat sink for dissipating heat during the manufacturing process. Because the semiconductor layer 600 and the high-kappa layer 407 are also made of a crystalline structure, heat dissipation problems may also occur at the interface between the semiconductor layer 600 and the high-kappa layer 407. Therefore, the dielectric layer 408 can also act as a bridge layer between the semiconductor layer 600 and the high-kappa layer 407 to reduce the thermal boundary resistance between the semiconductor layer 600 and the high-kappa layer 407. Therefore, the heat dissipation from the high-kappa layer 407 to the semiconductor layer 600 can also be improved.

[0138] Fig.23 is a cross-sectional view of a semiconductor device according to some embodiments of the present disclosure. It should be noted that Fig.23 Some elements of the EMBODIMENT may be similar to those described above, such elements will be labeled the same, and the relevant details will not be repeated for the sake of brevity. Fig.23 Similar to Fig. 9 and Fig.19 The structure shown in Fig.23 The structure includes both the heat dissipation multilayer 110 and the heat dissipation multilayer 410 .

[0139] also, Fig.23The structure also includes conductive vias 740 and 750 passing through the dielectric layer 710, the etch stop layer 715, the dielectric layer 720, the etch stop layer 725, and the heat dissipation multilayer 410, so that the conductive vias 740 and 750 are respectively in contact with the first metal gate structure 170 and the first source / drain epitaxial structure 140 of the first transistor (e.g., the first transistor TR1). The conductive vias 740 and 750 may also be referred to as backside vias. In some embodiments, the conductive vias 740 and 750 may include TiN, TiAl, Mo, Ru, W, or other suitable conductive materials. In some embodiments, the conductive vias 740 and 750 may also be present in Fig. 20 in the structure.

[0140] According to the aforementioned embodiments, it can be seen that the present disclosure provides advantages in manufacturing integrated circuits. However, it should be understood that other embodiments may provide additional advantages, and not all advantages must be disclosed herein, and not all embodiments require specific advantages. The embodiments of the present disclosure provide a CFET that includes a heat dissipation multilayer. The heat dissipation multilayer may include a first high kappa layer and a second high kappa layer. The heat dissipation multilayer may also include a dielectric layer located between the first high kappa layer and the second high kappa layer. The dielectric layer may act as a bridging layer located between the first high kappa layer and the second high kappa layer so as to reduce the thermal boundary resistance between the first high kappa layer and the second high kappa layer. Therefore, the heat dissipation of the device can be improved.

[0141] In some embodiments of the present disclosure, a semiconductor device includes a first transistor, a second transistor located above the first transistor, and a heat dissipation multilayer located between the first transistor and the second transistor. The first transistor includes a first semiconductor layer; a first gate structure surrounding the first semiconductor layer; and a first source / drain epitaxial structure located on opposite ends of the first semiconductor layer. The second transistor includes a second semiconductor layer; a second gate structure surrounding the second semiconductor layer; and a second source / drain epitaxial structure located on opposite ends of the second semiconductor layer. The heat dissipation multilayer is located between the first transistor and the second transistor, wherein the heat dissipation multilayer includes a first layer having a first phonon frequency range, a second layer having a second phonon frequency range, and a third layer located between the first layer and the second layer, and wherein the third layer has a third phonon frequency range, and the third phonon frequency range overlaps with the first phonon frequency range and the second phonon frequency range.

[0142] In some embodiments, thermal conductivity of the first layer and the second layer is higher than thermal conductivity of the third layer.

[0143] In some embodiments, the first layer and the second layer include a crystalline structure, and the third layer includes an amorphous structure.

[0144] In some embodiments, the first layer and the second layer are made of different materials.

[0145] In some embodiments, the first layer and the second layer are separated by a third layer.

[0146] In some embodiments, the semiconductor device further includes internal spacers located on opposite ends of the heat dissipation multilayer.

[0147] In some embodiments, the semiconductor device further includes an isolation structure in contact with one of the first source / drain epitaxial structures and one of the second source / drain epitaxial structures, wherein the heat dissipation multilayer is in contact with the isolation structure.

[0148] In some embodiments of the present disclosure, a semiconductor device includes a first transistor, a second transistor located on the front side of the first transistor, a backside interconnect structure located on the back side of the first transistor, and a heat dissipation multilayer located between the backside interconnect structure and the first transistor. The first transistor includes a first semiconductor layer; a first gate structure surrounding the first semiconductor layer; and a first source / drain epitaxial structure located on opposite ends of the first semiconductor layer. The second transistor includes a second semiconductor layer; a second gate structure surrounding the second semiconductor layer; and a second source / drain epitaxial structure located on opposite ends of the second semiconductor layer. The heat dissipation multilayer includes a first heat dissipation layer, a second heat dissipation layer, and a dielectric layer located between the first heat dissipation layer and the second heat dissipation layer, wherein the thermal conductivity of the first heat dissipation layer and the second heat dissipation layer is higher than the thermal conductivity of the dielectric layer.

[0149] In some embodiments, the backside interconnect structure includes a backside via, and the backside via extends into the heat dissipation multilayer and is electrically connected to the first transistor.

[0150] In some embodiments, the heat dissipation multilayer contacts the first gate structure.

[0151] In some embodiments, the heat dissipation multilayer contacts one of the first source / drain epitaxial structures.

[0152] In some embodiments, the first heat dissipation layer and the second heat dissipation layer include aluminum nitride or boron nitride.

[0153] In some embodiments, the first heat dissipation layer and the second heat dissipation layer include yttrium oxide, yttrium aluminum garnet, aluminum oxide, or beryllium oxide.

[0154] In some embodiments, the first heat dissipation layer and the second heat dissipation layer include silicon carbide, graphene, diamond-like carbon, or diamond.

[0155] In some embodiments, the first heat dissipation layer and the second heat dissipation layer are made of different materials.

[0156] In some embodiments of the present disclosure, a method includes forming a first stack of alternating first semiconductor channel layers and first sacrificial layers and a second stack of alternating second semiconductor channel layers and second sacrificial layers over a first substrate; forming a first heat dissipation layer over the second stack of alternating second semiconductor channel layers and second sacrificial layers, the first heat dissipation layer having a first phonon frequency range; forming a first dielectric layer over the first heat dissipation layer; forming a first source / drain epitaxial structure on opposite ends of each of the first semiconductor channel layers; forming a second source / drain epitaxial structure on opposite ends of each of the second semiconductor channel layers; replacing the first sacrificial layer with a first gate structure, the first gate structure surrounding each of the first semiconductor channel layers; replacing the second sacrificial layer with a second gate structure, the second gate structure surrounding each of the second semiconductor channel layers; bonding the first dielectric layer to the second heat dissipation layer by using a second dielectric layer, wherein the second heat dissipation layer has a second phonon frequency range different from the first phonon frequency range; and forming a backside via extending through the first heat dissipation layer, the first dielectric layer, the second dielectric layer, and the second heat dissipation layer.

[0157] In some embodiments, the method further includes forming a second heat dissipation layer over the second substrate before forming a second dielectric layer over the second heat dissipation layer; and performing a grinding process on the back side of the second substrate to remove the second substrate before forming the back side through hole.

[0158] In some embodiments, the method further includes forming a dielectric material over the second substrate before forming the second heat dissipation layer, wherein the backside via is formed in the dielectric material.

[0159] In some embodiments, thermal conductivities of the first heat dissipation layer and the second heat dissipation layer are higher than thermal conductivities of the first dielectric layer and the second dielectric layer.

[0160] In some embodiments, the method further includes forming a semiconductor layer above the first dielectric layer; forming a first bonding layer above the semiconductor layer; forming a second bonding layer above the second substrate; bonding the first bonding layer to the second bonding layer; and before bonding the first dielectric layer to the second dielectric layer, performing a grinding process on the back side of the second substrate until the first dielectric layer is exposed.

[0161] In some embodiments of the present disclosure, a semiconductor device includes a first transistor, a second transistor located above the first transistor, and a heat dissipation multilayer located between the first transistor and the second transistor. The first transistor includes a first semiconductor layer; a first gate structure surrounding the first semiconductor layer; and a first source / drain epitaxial structure located at opposite ends of the first semiconductor layer. The second transistor includes a second semiconductor layer; a second gate structure surrounding the second semiconductor layer; and a second source / drain epitaxial structure located at opposite ends of the second semiconductor layer. The heat dissipation multilayer is located between the first transistor and the second transistor, wherein the heat dissipation multilayer includes a first heat dissipation layer, a second heat dissipation layer, and a dielectric layer located between the first heat dissipation layer and the second heat dissipation layer.

[0162] In some embodiments, the first heat dissipation layer and the second heat dissipation layer include a crystalline structure, and the dielectric layer includes an amorphous structure.

[0163] The foregoing summarizes the features of several embodiments so that those skilled in the art can better understand the various aspects of the present disclosure. Those skilled in the art should understand that they can easily use the present disclosure as a basis for designing or modifying other processes and structures for achieving the same purposes and / or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and various changes, substitutions and modifications can be made herein without departing from the spirit and scope of the present disclosure.

Claims

1. A semiconductor device, characterized in that: include: A first transistor comprising: a first semiconductor layer; a first gate structure surrounding the first semiconductor layer; and A plurality of first source / drain epitaxial structures are located at opposite ends of the first semiconductor layer; a second transistor, located above the first transistor, the second transistor comprising: a second semiconductor layer; a second gate structure surrounding the second semiconductor layer; and A plurality of second source / drain epitaxial structures are located at opposite ends of the second semiconductor layer; and A heat dissipation multilayer is located between the first transistor and the second transistor, wherein the heat dissipation multilayer includes a first layer, a second layer and a third layer located between the first layer and the second layer, wherein the first layer and the second layer include a crystalline structure, and the third layer includes an amorphous structure.

2. The semiconductor device according to claim 1, wherein The first layer and the second layer are separated by the third layer.

3. The semiconductor device according to claim 1, wherein: Further included are a plurality of internal spacers located on opposite ends of the heat dissipation multilayer.

4. The semiconductor device according to claim 1, wherein: The invention further comprises an isolation structure contacting one of the plurality of first source / drain epitaxial structures and one of the plurality of second source / drain epitaxial structures, wherein the heat dissipation multilayer contacts the isolation structure.

5. A semiconductor device, characterized in that: include: A first transistor comprising: a first semiconductor layer; a first gate structure surrounding the first semiconductor layer; and A plurality of first source / drain epitaxial structures are located at opposite ends of the first semiconductor layer; a second transistor located on a front side of the first transistor, the second transistor comprising: a second semiconductor layer; a second gate structure surrounding the second semiconductor layer; and A plurality of second source / drain epitaxial structures are located at opposite ends of the second semiconductor layer; a backside interconnect structure located on a backside of the first transistor; and A heat dissipation multilayer is located between the back-side interconnect structure and the first transistor, wherein the heat dissipation multilayer includes a first heat dissipation layer, a second heat dissipation layer and a dielectric layer located between the first heat dissipation layer and the second heat dissipation layer.

6. The semiconductor device according to claim 5, wherein: The back-side interconnect structure includes a back-side through hole, and the back-side through hole extends into the heat dissipation multilayer and is electrically connected to the first transistor.

7. The semiconductor device according to claim 5, wherein: The heat dissipation multilayer is in contact with the first grid structure.

8. The semiconductor device according to claim 5, wherein: The heat dissipation multilayer is in contact with one of the plurality of first source / drain epitaxial structures.

9. A semiconductor device, characterized in that: include: A first transistor comprising: a first semiconductor layer; a first gate structure surrounding the first semiconductor layer; and A plurality of first source / drain epitaxial structures are located at opposite ends of the first semiconductor layer; a second transistor, located above the first transistor, the second transistor comprising: a second semiconductor layer; a second gate structure surrounding the second semiconductor layer; and A plurality of second source / drain epitaxial structures are located at opposite ends of the second semiconductor layer; and A heat dissipation multilayer is located between the first transistor and the second transistor, wherein the heat dissipation multilayer includes a first heat dissipation layer, a second heat dissipation layer and a dielectric layer located between the first heat dissipation layer and the second heat dissipation layer.

10. The semiconductor device according to claim 9, wherein: The first heat dissipation layer and the second heat dissipation layer include a crystalline structure, and the dielectric layer includes an amorphous structure.

Images