Multi-channel multi-phase output circuit, load point power supply and electronic equipment

Abstract

The present application discloses a multi-channel multi-phase output circuit, a load point power supply and an electronic device, wherein the multi-channel multi-phase output circuit includes N chips of the same model. The chip includes a voltage input pin, a voltage output pin and a clock input pin. (i) The chip includes a clock output pin and a phase setting pin, and the clock output pin of the M-1th chip is connected to the clock input pin of the Mth chip. When the phase setting pin of the Kth chip inputs the Kth voltage signal, the clock signal output by the clock input pin of the Kth chip has the Kth phase difference with the clock signal of the Kth chip. (ii) The multi-channel multi-phase output circuit also includes a phase generator. The phase generator outputs N clock signals, and one clock signal is input to the clock input pin of one chip. In the above manner, multi-channel multi-phase output can be realized based on one model of chip, so as to be applicable to more application scenarios and improve practicality.

Description

Technical Field

[0001] The embodiments of the present application relate to the technical field of electronic circuits, and in particular to a multi-channel multi-phase output circuit, a point-of-load power supply, and an electronic device. Background Art

[0002] Point-of-Load (POL) power supply is the power supply next to the load. The point-of-load power supply refers to the place where the load is connected in the circuit, used to provide power to the load. The point-of-load power supply is usually implemented through a chip.

[0003] However, in current domestic chips, usually only single-channel single-phase output can be achieved, but multi-channel multi-phase output cannot be achieved. Utility Model Content

[0004] The embodiments of the present application provide a multi-channel multi-phase output circuit, a load point power supply and an electronic device, which can realize multi-channel multi-phase output based on a chip model to be suitable for more application scenarios and improve practicality.

[0005] In a first aspect, an embodiment of the present application provides a multi-channel multi-phase output circuit, comprising:

[0006] N chips, the N chips are of the same model, where N is an integer greater than or equal to 2;

[0007] Each of the N chips comprises a voltage input pin, a voltage output pin and a clock input pin, wherein the voltage input pin is configured to connect an input voltage, the voltage output pin is configured to provide an output voltage, and the clock input pin is configured to input a clock signal;

[0008] Do one of the following two options:

[0009] (i) Each chip in the N chips includes a clock output pin and a phase setting pin, and the clock output pin of the M-1th chip in the N chips is connected to the clock input pin of the Mth chip, where M is an integer less than or equal to N;

[0010] The clock output pin is configured to output a clock signal, and the phase setting pin is configured to input a voltage signal, wherein when the phase setting pin of the Kth chip among the N chips inputs the Kth voltage signal, the clock signal output by the clock output pin of the Kth chip has a Kth phase difference with the clock signal of the Kth chip, the clock signal output by the clock output pin of the N chips has N phase differences with the clock signals of the N chips, the sum of the N phase differences is 360°, and K is an integer less than or equal to N;

[0011] (ii) the multi-channel multi-phase output circuit further includes a phase generator;

[0012] The phase generator is connected to the clock input pin of each chip in the N chips, and the phase generator is configured to divide 360° into N phases and output N clock signals based on the N phases, and one clock signal among the N clock signals is input to the clock input pin of one chip in the N chips.

[0013] In one or more embodiments, when implementing solution (i), the multi-channel multi-phase output circuit further includes N voltage-dividing branches, one of the N voltage-dividing branches is connected to a phase setting pin of one of the N chips, and the N branches are connected to a power supply;

[0014] Based on the voltage division ratio between the power supply and each of the N voltage division branches, a corresponding voltage signal is output to a phase setting pin of each of the N chips.

[0015] In one or more embodiments, each of the N voltage-dividing branches is connected between the power supply and ground, and each voltage-dividing branch includes two resistors connected in series, and the connection point between the two resistors is connected to the phase setting pin of the corresponding chip.

[0016] In one or more embodiments, the N chips are all of the first model, the multi-channel multi-phase output circuit further includes N first auxiliary branches, and each chip in the N chips is connected to a first auxiliary branch in the N first auxiliary branches;

[0017] Each of the N chips further comprises a switch pin, a voltage output pin and a power ground pin, and each of the N first auxiliary branches further comprises a first inductor and a first capacitor;

[0018] The first inductor and the first capacitor are connected in series between the switch pin and the power ground pin, the power ground pin is grounded, the connection point between the first inductor and the first capacitor is connected to the voltage output pin, and the voltage at the connection point between the first inductor and the first capacitor is the positive pole of the output voltage.

[0019] In one or more embodiments, each of the N chips further includes an operating frequency setting pin, a feedback pin, a compensation pin, a regulator output pin, a signal ground pin, a regulator power supply input pin, a regulator signal power supply input pin and a bootstrap drive power supply pin, and each of the N first auxiliary branches further includes a first resistor, a second resistor, a third resistor, a fourth resistor, a second capacitor, a third capacitor, a fourth capacitor, a fifth capacitor and a sixth capacitor;

[0020] The first resistor is connected between the operating frequency setting pin and the ground, the second resistor is connected between the voltage output pin and the feedback pin, the third resistor and the second capacitor are connected in series between the compensation pin and the ground, the third capacitor is connected between the compensation pin and the ground, the fourth capacitor is connected between the regulator output pin and the signal ground pin, the signal ground pin is also connected to the ground, the fifth capacitor is connected between the positive pole of the input voltage and the ground, the fourth resistor is connected between the regulator power supply input pin and the regulator signal power supply input pin, the regulator power supply input pin is also connected to the positive pole of the input voltage, and the sixth capacitor is connected between the switch pin and the bootstrap drive power supply pin.

[0021] In one or more embodiments, the N chips are all of the second model, the multi-channel multi-phase output circuit further includes N second auxiliary branches, and each chip in the N chips is connected to one second auxiliary branch in the N second auxiliary branches;

[0022] Each of the N chips further includes a high-side gate driver output pin and a low-side gate driver output pin, and each of the N second auxiliary branches further includes a seventh capacitor, an eighth capacitor, a ninth capacitor, a tenth capacitor, an eleventh capacitor, a twelfth capacitor, a fifth resistor, a second inductor, a first switch tube, and a second switch tube;

[0023] The high-side gate driver output pin is connected to the first end of the first switch tube, the third end of the first switch tube is connected to the positive electrode of the input voltage, the second end of the first switch tube is connected to the third end of the second switch tube, the first end of the second switch tube is connected to the low-side gate driver output pin, the third end of the second switch tube is grounded, the seventh capacitor is connected between the positive electrode of the input voltage and the ground, the eighth capacitor is connected in parallel with the seventh capacitor, the ninth capacitor is connected between the third end of the second switch tube and the ground, the first end of the second inductor is connected to the third end of the second switch tube, the second end of the second inductor is the positive electrode of the output voltage, the fifth resistor and the tenth capacitor are connected in series between the first end and the second end of the second inductor, the eleventh capacitor is connected between the second end of the second inductor and the ground, and the twelfth capacitor is connected in parallel with the eleventh capacitor.

[0024] In one or more embodiments, each of the N chips further includes a gate driver power pin, a switch node pin, a regulator output pin, an analog ground pin, a feedback input pin, and a compensation pin, and each of the N second auxiliary branches further includes a thirteenth capacitor, a fourteenth capacitor, a fifteenth capacitor, a sixteenth capacitor, a seventeenth capacitor, a first diode, a sixth resistor, and a seventh resistor;

[0025] The anode of the first diode is connected to the second voltage, the cathode of the first diode is connected to the gate driver power pin, the thirteenth capacitor is connected between the gate driver power pin and the switch node pin, the switch node pin is also connected to the third end of the second switch tube, the fourteenth capacitor is connected to the regulator output pin and the analog ground pin, the analog ground pin is grounded, the sixth resistor and the fifteenth capacitor are connected in parallel between the second end of the second inductor and the feedback input pin, the sixteenth capacitor is connected between the compensation pin and the ground, and the seventh resistor is connected in series with the seventeenth capacitor and then connected in parallel with the sixteenth capacitor.

[0026] In a second aspect, an embodiment of the present application provides a point-of-load power supply, comprising the multi-channel multi-phase output circuit as described above.

[0027] In a third aspect, an embodiment of the present application provides an electronic device, comprising a multi-channel load and a load point power supply as described above, wherein the load point power supply is connected to the multi-channel load.

[0028] The beneficial effects of the present application are as follows: the multi-channel multi-phase output circuit of the embodiment of the present application includes N chips, the models of the N chips are the same, wherein N is an integer greater than or equal to 2. Each of the N chips includes a voltage input pin, a voltage output pin and a clock input pin, the voltage input pin is configured to connect an input voltage, the voltage output pin is configured to provide an output voltage, and the clock input pin is configured to input a clock signal. When implementing scheme (i), each chip in the N chips includes a clock output pin and a phase setting pin, and the clock output pin of the M-1th chip in the N chips is connected to the clock input pin of the Mth chip, wherein M is an integer less than or equal to N; the clock output pin is configured to output a clock signal, and the phase setting pin is configured to input a voltage signal, wherein when the phase setting pin of the Kth chip in the N chips inputs the Kth voltage signal, the clock signal output by the clock input pin of the Kth chip has a Kth phase difference with the clock signal of the Kth chip, and the clock signal output by the clock input pin of the N chips has N phase differences with the clock signals of the N chips, the sum of the N phase differences is 360°, and K is an integer less than or equal to N. Thus, the phase of the voltage output by each chip can be different to achieve multi-phase output, and the N chips can achieve N output voltages to achieve multi-channel output, and in summary, multi-channel multi-phase output is achieved. When scheme (ii) is executed, the multi-channel multi-phase output circuit also includes a phase generator; the phase generator is connected to the clock input pin of each chip in the N chips, and the phase generator is configured to divide 360° into N phases, and output N clock signals based on the N phases, and one of the N clock signals is input to the clock input pin of one of the N chips. Similarly, the phase of the voltage output by each chip can be made different to achieve multi-phase output, and the N chips can achieve N output voltages to achieve multi-channel output, so that multi-channel multi-phase output is achieved. Through the above process, whether scheme (i) or scheme (ii) is adopted, multi-channel multi-phase output can be achieved based on a chip of one model, which is conducive to being applicable to more application scenarios and improving practicality. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] One or more embodiments are exemplarily described by the figures in the corresponding drawings, and these exemplary descriptions are not intended to limit the embodiments. Elements with the same reference numerals in the drawings represent similar elements.

[0030] Figure 1 The structure of the multi-channel multi-phase output circuit provided in the embodiment of the present application is shown in FIG. Figure 1 ;

[0031] Figure 2 The structure of the multi-channel multi-phase output circuit provided in the embodiment of the present application is shown in FIG. Figure 2 ;

[0032] Figure 3 The structure of the multi-channel multi-phase output circuit provided in the embodiment of the present application is shown in FIG. Figure 3 ;

[0033] Figure 4 The structure of the multi-channel multi-phase output circuit provided in the embodiment of the present application is shown in FIG. Figure 4 ;

[0034] Figure 5 is a schematic diagram of a circuit structure in which a first chip provided in an embodiment of the present application is connected to a first auxiliary circuit;

[0035] Figure 6 It is a schematic diagram of the circuit structure in which the first chip provided in the embodiment of the present application is connected to the second auxiliary circuit. DETAILED DESCRIPTION

[0036] In order to make the purpose, technical scheme and advantages of the embodiments of the present application clearer, the technical scheme in the embodiments of the present application will be described clearly and in detail in combination with the drawings in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, rather than all the embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and are not used to limit the present application.

[0037] It should be noted that, when an element is described as being “connected to” another element, it may be directly connected to the other element, or one or more intervening elements may exist therebetween.

[0038] In addition, the technical features involved in the various embodiments of the present application described below can be combined with each other as long as there is no structural conflict between them.

[0039] Please refer to Figure 1 , Figure 1 This is a schematic diagram of the structure of a multi-channel multi-phase output circuit provided in an embodiment of the present application. Figure 1 As shown, the multi-channel multi-phase output circuit includes N chips, and the N chips are of the same model, where N is an integer greater than or equal to 2. The N chips include a first chip A1, a second chip A2, ..., and an Nth chip AN. ​​It can be understood that the chip in the embodiment of the present application is a chip of a load point power supply, and the voltage output by the chip is generally small, such as 1.5V, 2V, 3.3V, etc., and the connected load is also small, generally within 300W.

[0040] Each of the N chips includes a voltage input pin, a voltage output pin and a clock input pin. The voltage input pin is configured to connect to an input voltage VI N, the voltage output pin is configured to provide an output voltage, and the clock input pin is configured to input a clock signal. Specifically, the voltage input pin of the first chip A1 is connected to the input voltage VI N, and the voltage output pin provides an output voltage VO1; the voltage input pin of the second chip A2 is connected to the input voltage VI N, and the voltage output pin provides an output voltage VO2; ...; the voltage input pin of the Nth chip AN is connected to the input voltage VI N, and the voltage output pin provides an output voltage VON.

[0041] Each of the N chips includes a clock output pin and a phase setting pin. The clock output pin of the M-1th chip among the N chips is connected to the clock input pin of the Mth chip, where M is an integer less than or equal to N. That is, the clock output pin of the first chip A1 is connected to the clock input pin of the second chip A2, the clock output pin of the second chip A2 is connected to the clock input pin of the third chip A3, ..., the clock output pin of the N-1th chip AN-1 is connected to the clock input pin of the Nth chip AN. ​​The clock output pin is configured to output a clock signal, and the phase setting pin is configured to input a voltage signal. That is, the phase setting pin of the first chip A1 inputs a first voltage signal VL1, the phase setting pin of the second chip A2 inputs a second voltage signal VL2, ..., the phase setting pin of the Nth chip AN inputs an Nth voltage signal VLN. Among them, when the phase setting pin of the Kth chip among the N chips inputs the Kth voltage signal, the clock signal output by the clock output pin of the Kth chip has the Kth phase difference with the clock signal of the Kth chip, the clock signal output by the clock input pin of the N chips has N phase differences with the clock signals of the N chips, the sum of the N phase differences is 360°, and K is an integer less than or equal to N. Taking K=1 as an example, the first voltage signal VL1 is input to the phase setting pin of the first chip A1, so that the first chip A1 generates a phase offset corresponding to the first voltage signal VL1, and the first chip A1 shifts the phase of its current clock signal by the above phase offset, outputs it through the clock output pin, and inputs it to the clock input pin of the second chip A2, then the phase difference (i.e., the first phase difference) between the clock signal of the second chip A2 (i.e., the clock signal output by the clock output pin of the first chip A1) and the clock signal of the first chip A1 is the above phase offset. By analogy, we can obtain the second phase difference between the clock signal output by the clock output pin of the second chip A2 and the clock signal of the second chip A2, the third phase difference between the clock signal output by the clock output pin of the third chip A2 and the clock signal of the third chip A3, ..., the Nth phase difference between the clock signal output by the clock output pin of the Nth chip AN and the clock signal of the Nth chip AN. ​​In summary, we can obtain N phase differences, and the sum of these N phase differences is 360°.For example, assuming that N=4 and four-way four-phase output is implemented, in some embodiments, the first voltage signal VL1, the second voltage signal VL2, the third voltage signal VL3 and the fourth voltage signal VL4 can be configured so that the first phase difference, the second phase difference, the third phase difference and the fourth phase difference are all 90°, that is, the phase of the clock signal of the first chip A1 is 0°, the phase of the clock signal of the second chip A2 is 90° (that is, offset by 90° based on the clock signal of the first chip A1), the phase of the clock signal of the third chip A3 is 180° (that is, offset by 90° based on the clock signal of the second chip A2), the phase of the clock signal of the fourth chip A4 is 270° (that is, offset by 90° based on the clock signal of the third chip A3), and the phase of the clock signal output by the clock output pin of the fourth chip A4 is 360° (that is, 0°).

[0042] Through the above process, the phase of the voltage output by each chip can be different to achieve multi-phase output, and N chips can achieve N output voltages to achieve multi-channel output, thereby achieving multi-channel multi-phase output, which is conducive to being applicable to more application scenarios and improving practicality. Moreover, by setting each phase of the multi-channel output to be different, the pulsating current or ripple current of the front-stage circuit (i.e., providing the input voltage VI N) of the multi-channel multi-phase output circuit 100 can be reduced, interference can be reduced, and it is conducive to simplifying the design scheme.

[0043] It is understandable that when there are output voltages of the same magnitude, the output voltages of the same magnitude can be connected in parallel to power a larger load, so as to be applicable to more application scenarios and improve practicality. For example, assuming that the first output voltage VO1 is the same as the second output voltage VO2, the first output voltage VO1 and the second output voltage VO2 can be connected in parallel (corresponding to short-circuiting the voltage output pin in the first chip A1 and the voltage output pin in the second chip A2, and connecting them to the load) to power the same load.

[0044] In one embodiment, if Figure 2 As shown, the multi-channel multi-phase output circuit 100 also includes N voltage-dividing branches. The N voltage-dividing branches include a first voltage-dividing branch B1, a second voltage-dividing branch B2, ..., and an Nth voltage-dividing branch BN. One of the N voltage-dividing branches is connected to the phase setting pin of one of the N chips, and the N branches are connected to a power supply. That is, the first voltage-dividing branch B1 is connected between the power supply VC1 and the phase setting pin of the first chip A1, the second voltage-dividing branch B2 is connected between the power supply VC1 and the phase setting pin of the second chip A2, ..., and the Nth voltage-dividing branch BN is connected between the power supply VC1 and the phase setting pin of the Nth chip AN.

[0045] Wherein, based on the voltage division ratio between the power supply VC1 and each of the N voltage division branches, the corresponding voltage signal is output to the phase setting pin of each of the N chips. Specifically, based on the voltage division ratio between the power supply VC1 and the first voltage division branch B1, the first voltage division branch B1 outputs the first voltage signal VL1 to the phase setting pin of the first chip A1; based on the voltage division ratio between the power supply VC1 and the second voltage division branch B2, the second voltage division branch B2 outputs the second voltage signal VL2 to the phase setting pin of the second chip A2; ...; based on the voltage division ratio between the power supply VC1 and the Nth voltage division branch BN, the Nth voltage division branch BN outputs the Nth voltage signal VLN to the phase setting pin of the Nth chip AN.

[0046] In one embodiment, if Figure 3 As shown, each of the N voltage-dividing branches is connected between the power supply VC1 and the ground, and each voltage-dividing branch includes two resistors connected in series, and the connection point between the two resistors is connected to the phase setting pin of the corresponding chip.

[0047] Specifically, the first voltage-dividing branch B1, the second voltage-dividing branch B2, ..., and the Nth voltage-dividing branch BN are all connected between the power supply VC1 and the ground GND. The first voltage-dividing branch B1 includes a resistor R1 B1 and a resistor R2B1 connected in series, the second voltage-dividing branch B2 includes a resistor R1 B2 and a resistor R2B2 connected in series, ..., and the Nth voltage-dividing branch BN includes a resistor R1 BN and a resistor R2BN connected in series. The connection point between the resistor R1 B1 and the resistor R2B1 is connected to the phase setting pin of the first chip A1 to output the first voltage signal VL1 to the phase setting pin of the first chip A1; the connection point between the resistor R1 B2 and the resistor R2B2 is connected to the phase setting pin of the second chip A2 to output the second voltage signal VL2 to the phase setting pin of the second chip A2; ...; the connection point between the resistor R1 BN and the resistor R2BN is connected to the phase setting pin of the Nth chip AN to output the Nth voltage signal VLN to the phase setting pin of the Nth chip AN.

[0048] When the voltage division ratio between the two voltage division branches is the same, the phase offsets generated by the two chips connected to the two voltage division branches are the same; when the voltage division ratio between the two voltage division branches is different, the phase offsets generated by the two chips connected to the two voltage division branches are different. Taking the first voltage-dividing branch B1 and the second voltage-dividing branch B2 as an example, the resistance values ​​of the resistors R1 B1 and R1 B2 can be kept the same, and the resistance values ​​of the resistors R2B1 and R2B2 can be made different. Then, the voltage-dividing ratios of the first voltage-dividing branch B1 and the second voltage-dividing branch B2 are different, and the magnitudes of the first voltage signal VL1 and the second voltage signal VL2 are different. Then, the phase offset generated by the first chip A1 is different from the phase offset generated by the second chip A2. Conversely, if the resistance values ​​of the resistors R1 B1 and R1 B2 are kept the same, and the resistance values ​​of the resistors R2B1 and R2B2 are the same, then the voltage-dividing ratios of the first voltage-dividing branch B1 and the second voltage-dividing branch B2 are the same, and the magnitudes of the first voltage signal VL1 and the second voltage signal VL2 are the same. Then, the phase offset generated by the first chip A1 is the same as the phase offset generated by the second chip A2. It can be understood that the voltage division ratio of each voltage division branch can be the ratio between the resistance values ​​of two resistors in each voltage division branch. By adjusting the resistance value of the resistor in any voltage division branch among the N voltage division branches, the voltage division ratio of the voltage division branch can be adjusted.

[0049] Please refer to Figure 4 , Figure 4 FIG. 1 is a schematic diagram of a multi-channel multi-phase output circuit 100 provided in another embodiment of the present application. Figure 4 As shown, the multi-channel multi-phase output circuit includes N chips, and the N chips are of the same model, wherein N is an integer greater than or equal to 2. The N chips include a first chip A1, a second chip A2, ..., and an Nth chip AN.

[0050] Each of the N chips includes a voltage input pin, a voltage output pin and a clock input pin. The voltage input pin is configured to connect to an input voltage VI N, the voltage output pin is configured to provide an output voltage, and the clock input pin is configured to input a clock signal. Specifically, the voltage input pin of the first chip A1 is connected to the input voltage VI N, and the voltage output pin provides an output voltage VO1; the voltage input pin of the second chip A2 is connected to the input voltage VI N, and the voltage output pin provides an output voltage VO2; ...; the voltage input pin of the Nth chip AN is connected to the input voltage VI N, and the voltage output pin provides an output voltage VON.

[0051] The multi-channel multi-phase output circuit 100 also includes a phase generator 101. The phase generator 101 is connected to the clock input pin of each chip in the N chips. The phase generator 101 is configured to divide 360° into N phases and output N clock signals based on the N phases. One of the N clock signals is input to the clock input pin of one of the N chips. Specifically, the N clock signals include a first clock signal, a second clock signal, ..., and an Nth clock signal. The first clock signal is input to the clock input pin of the first chip A1, the second clock signal is input to the clock input pin of the second chip A2, ..., and the Nth clock signal is input to the clock input pin of the Nth chip AN. ​​Taking N=6 and dividing 360° into 6 equal parts as an example, the phases of the first clock signal, the second clock signal, the third clock signal, the fourth clock signal, the fifth clock signal, and the sixth clock signal are 0°, 60°, 120°, 180°, 240°, and 300°, respectively.

[0052] Through the above process, the phase of the voltage output by each chip can be different to achieve multi-phase output, and N chips can achieve N output voltages to achieve multi-channel output, thereby achieving multi-channel multi-phase output, which is conducive to being applicable to more application scenarios and improving practicality. Moreover, by setting each phase of the multi-channel output to be different, the pulsating current or ripple current of the front-stage circuit of the multi-channel multi-phase output circuit 100 can be reduced, interference can be reduced, and it is conducive to simplifying the design scheme.

[0053] In one embodiment, the N chips are all of the first model, and the multi-channel multi-phase output circuit 100 further includes N first auxiliary branches, and each chip in the N chips is connected to a first auxiliary branch in the N first auxiliary branches. The N first auxiliary branches include a first first auxiliary branch, a second first auxiliary branch, ..., and an Nth first auxiliary branch. The first chip A1 is connected to the first first auxiliary branch, the second chip A2 is connected to the second first auxiliary branch, ..., and the Nth chip AN is connected to the Nth first auxiliary branch. Among them, each chip in the N chips also includes a switch pin, a voltage output pin and a power ground pin, and each first auxiliary branch in the N first auxiliary branches also includes a first inductor and a first capacitor. The first inductor and the first capacitor are connected in series between the switch pin and the power ground pin, the power ground pin is grounded, the connection point between the first inductor and the first capacitor is connected to the voltage output pin, and the voltage at the connection point between the first inductor and the first capacitor is the positive pole of the output voltage, and the negative pole of the output voltage is the ground.

[0054] In one embodiment, each of the N chips further includes an operating frequency setting pin, a feedback pin, a compensation pin, a regulator output pin, a signal ground pin, a regulator power supply input pin, a regulator signal power supply input pin and a bootstrap drive power supply pin. Each of the N first auxiliary branches further includes a first resistor, a second resistor, a third resistor, a fourth resistor, a second capacitor, a third capacitor, a fourth capacitor, a fifth capacitor and a sixth capacitor. The first resistor is connected between the operating frequency setting pin and the ground, the second resistor is connected between the voltage output pin and the feedback pin, the third resistor and the second capacitor are connected in series between the compensation pin and the ground, the third capacitor is connected between the compensation pin and the ground, the fourth capacitor is connected between the regulator output pin and the signal ground pin, the signal ground pin is also connected to the ground, the fifth capacitor is connected between the positive pole of the input voltage and the ground, the fourth resistor is connected between the regulator power supply input pin and the regulator signal power supply input pin, the regulator power supply input pin is also connected to the positive pole of the input voltage, the negative pole of the input voltage is grounded, and the sixth capacitor is connected between the switch pin and the bootstrap drive power supply pin.

[0055] Please refer to Figure 5 , Figure 5 The circuit structure in which the first chip A1 is connected to the first first auxiliary circuit C1 is exemplarily shown. The first first auxiliary circuit C1 is a peripheral circuit of the first chip A1 to realize the basic functions of the first chip A1.

[0056] The first chip A1 is of the first model. In this embodiment, the second pin of the first chip A1 is a phase setting pin, the 23rd pin is a clock output pin, and the 24th pin is a clock input pin.

[0057] The first chip A1 further includes a switch pin (pins 11 to 16 of the first chip A1 are switch pins), a voltage output pin (i.e., pin 9 of the first chip A1) and a power ground pin (pins 10 and 25 of the first chip A1 are power ground pins). Each of the first auxiliary branches in the first auxiliary branch further includes a first inductor L1 and a first capacitor C1.

[0058] The first inductor L1 and the first capacitor C1 are connected in series between the switch pin and the power ground pin, the power ground pin is grounded GND, a connection point between the first inductor L1 and the first capacitor C1 is connected to the voltage output pin, and a voltage at the connection point between the first inductor L1 and the first capacitor C1 is a positive electrode of the output voltage VO1, and a negative electrode of the output voltage VO1 is the ground GND.

[0059] In this embodiment, the first chip A1 further includes an operating frequency setting pin (i.e., the first pin of the first chip A1), a feedback pin (i.e., the fourth pin of the first chip A1), a compensation pin (i.e., the sixth pin of the first chip A1), a regulator output pin (i.e., the twenty-first pin of the first chip A1, which is the output of the 3.3V regulator inside the first chip A1), a signal ground pin (i.e., the twenty-second pin of the first chip A1), a regulator power supply input pin (i.e., the seventeenth and eighteenth pins of the first chip A1, corresponding to Figure 1-Figure 4 The first auxiliary branch also includes a first resistor R1, a second resistor R2, a third resistor R3, a fourth resistor R4, a second capacitor C2, a third capacitor C3, a fourth capacitor C4, a fifth capacitor C5 and a sixth capacitor C6.

[0060] Among them, the first resistor R1 is connected between the operating frequency setting pin and the ground GND, the second resistor R2 is connected between the voltage output pin and the feedback pin, the third resistor R3 and the second capacitor C2 are connected in series between the compensation pin and the ground GND, the third capacitor C3 is connected between the compensation pin and the ground GND, the fourth capacitor C4 is connected between the regulator output pin and the signal ground pin, the regulator output pin outputs the voltage VC2, the signal ground pin is also connected to the ground GND, the fifth capacitor C5 is connected between the positive electrode of the input voltage and the ground GND, the fourth resistor R4 is connected between the regulator power supply input pin and the regulator signal power supply input pin, the regulator power supply input pin is also connected to the positive electrode of the input voltage VI N, the negative electrode of the input voltage VI N is connected to the ground GND, and the sixth capacitor C6 is connected between the switch pin and the bootstrap drive power supply pin.

[0061] It is understandable that, since the models of the chips are the same, in the embodiments where other chips are connected to the corresponding first auxiliary circuits, the specific processes are the same as those in the embodiments. Figure 5 The specific implementation process of connecting the first chip A1 and the first first auxiliary circuit C1 is the same, which is within the scope of easy understanding for those skilled in the art and will not be repeated here. For example, the specific implementation process of connecting the second chip A2 and the second first auxiliary circuit is the same as the specific implementation process of connecting the first chip A1 and the first first auxiliary circuit C1.

[0062] In one embodiment, the N chips are all of the second model, the multi-channel multi-phase output circuit further includes N second auxiliary branches, and each chip in the N chips is connected to one of the N second auxiliary branches. Each chip in the N chips also includes a high-side gate driver output pin and a low-side gate driver output pin, and each of the N second auxiliary branches also includes a seventh capacitor, an eighth capacitor, a ninth capacitor, a tenth capacitor, an eleventh capacitor, a twelfth capacitor, a fifth resistor, a second inductor, a first switch tube, and a second switch tube.

[0063] The high-side gate driver output pin is connected to the first end of the first switch tube, the third end of the first switch tube is connected to the positive electrode of the input voltage, the second end of the first switch tube is connected to the third end of the second switch tube, the first end of the second switch tube is connected to the low-side gate driver output pin, the third end of the second switch tube is grounded, the seventh capacitor is connected between the positive electrode of the input voltage and the ground, the eighth capacitor is connected in parallel with the seventh capacitor, the ninth capacitor is connected between the third end of the second switch tube and the ground, the first end of the second inductor is connected to the third end of the second switch tube, the second end of the second inductor is the positive electrode of the output voltage, the fifth resistor and the tenth capacitor are connected in series between the first end and the second end of the second inductor, the eleventh capacitor is connected between the second end of the second inductor and the ground, and the twelfth capacitor is connected in parallel with the eleventh capacitor.

[0064] In one embodiment, each of the N chips further includes a gate driver power pin, a switch node pin, a regulator output pin, an analog ground pin, a feedback input pin and a compensation pin, and each of the N second auxiliary branches further includes a thirteenth capacitor, a fourteenth capacitor, a fifteenth capacitor, a sixteenth capacitor, a seventeenth capacitor, a first diode, a sixth resistor and a seventh resistor.

[0065] The anode of the first diode is connected to the second voltage, the cathode of the first diode is connected to the gate driver power pin, the thirteenth capacitor is connected between the gate driver power pin and the switch node pin, the switch node pin is also connected to the third end of the second switch tube, the fourteenth capacitor is connected to the regulator output pin and the analog ground pin, the analog ground pin is grounded, the sixth resistor and the fifteenth capacitor are connected in parallel between the second end of the second inductor and the feedback input pin, the sixteenth capacitor is connected between the compensation pin and the ground, and the seventh resistor and the seventeenth capacitor are connected in series and then connected in parallel with the sixteenth capacitor.

[0066] Please refer to Figure 6 , Figure 6 The circuit structure in which the first chip A1 is connected to the first second auxiliary circuit D1 is exemplarily shown. The first second auxiliary circuit D1 is a peripheral circuit of the first chip A1 to realize the basic function of the first chip A1.

[0067] The first chip A1 is of the second model. In this embodiment, the fourth pin of the first chip A1 is a phase setting pin, the second pin is a clock output pin, and the third pin is a clock input pin.

[0068] The first chip A1 further includes a high-side gate driver output pin (i.e., the 11th pin of the first chip A1) and a low-side gate driver output pin (i.e., the 14th pin of the first chip A1). The first second auxiliary branch further includes a seventh capacitor C7, an eighth capacitor C8, a ninth capacitor C9, a tenth capacitor C10, an eleventh capacitor C11, a twelfth capacitor C12, a fifth resistor R5, a second inductor L2, a first switch tube Q1, and a second switch tube Q2.

[0069] The high-side gate driver output pin is connected to the first end of the first switch tube Q1, the third end of the first switch tube Q1 is connected to the positive electrode of the input voltage VIN, the second end of the first switch tube Q1 is connected to the third end of the second switch tube Q2, the first end of the second switch tube Q2 is connected to the low-side gate driver output pin, the third end of the second switch tube Q2 is grounded GND, the seventh capacitor C7 is connected between the positive electrode of the input voltage VIN and the ground GND, the eighth capacitor C8 is connected in parallel with the seventh capacitor C7, the ninth capacitor C9 is connected between the third end of the second switch tube Q2 and the ground GND, the first end of the second inductor L2 is connected to the third end of the second switch tube Q2, the second end of the second inductor L2 is the positive electrode of the output voltage VO1, the fifth resistor R5 and the tenth capacitor C10 are connected in series between the first end and the second end of the second inductor L2, the eleventh capacitor C11 is connected between the second end of the second inductor L2 and the ground GND, and the twelfth capacitor C12 is connected in parallel with the eleventh capacitor C11.

[0070] In this embodiment, the first chip A1 further includes a gate driver power pin (i.e., pin 12 of the first chip A1), a switch node pin (i.e., pin 13 of the first chip A1), a regulator output pin (i.e., pin 15 of the first chip A1), an analog ground pin (i.e., pin 18 of the first chip A1), a feedback input pin (i.e., pin 19 of the first chip A1), and a compensation pin (i.e., pin 20 of the first chip A1). The first second auxiliary branch further includes a thirteenth capacitor C13, a fourteenth capacitor C14, a fifteenth capacitor C15, a sixteenth capacitor C16, a seventeenth capacitor C17, a first diode D2, a sixth resistor R6, and a seventh resistor R7.

[0071] The anode of the first diode D1 is connected to the second voltage R2, the cathode of the first diode D1 is connected to the gate driver power pin, the thirteenth capacitor C13 is connected between the gate driver power pin and the switch node pin, the switch node pin is also connected to the third end of the second switch tube Q2, the fourteenth capacitor C14 is connected to the regulator output pin and the analog ground pin, the regulator output pin outputs the voltage VC3, the analog ground pin is grounded GND, the sixth resistor R6 and the fifteenth capacitor C15 are connected in parallel between the second end of the second inductor L2 and the feedback input pin, the sixteenth capacitor C16 is connected between the compensation pin and the ground GND, the seventh resistor R7 and the seventeenth capacitor C17 are connected in series and then connected in parallel with the sixteenth capacitor C16.

[0072] An embodiment of the present application further provides a point-of-load power supply, which includes the multi-channel multi-phase output circuit 100 in any embodiment of the present application.

[0073] An embodiment of the present application further provides an electronic device, which includes a multi-channel load and a load point power supply in any embodiment of the present application, wherein the load point power supply is connected to the multi-channel load.

[0074] The above descriptions are merely embodiments of the present application and are not intended to limit the patent scope of the present application. Any equivalent structure or equivalent process transformation made using the contents of the present application specification and drawings, or directly or indirectly applied in other related technical fields, are also included in the patent protection scope of the present application.

[0075] The above embodiments are only used to illustrate the technical solutions of the present application, but not to limit them. Under the idea of ​​the present application, the technical features in the above embodiments or different embodiments can also be combined, and the steps can be implemented in any order. It should be understood by ordinary technicians in this field that they can still modify the technical solutions recorded in the above embodiments, or replace some of the technical features by equivalents; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A multi-channel multi-phase output circuit, characterized in that: include: N chips, the N chips are of the same model, where N is an integer greater than or equal to 2; Each of the N chips comprises a voltage input pin, a voltage output pin and a clock input pin, wherein the voltage input pin is configured to connect an input voltage, the voltage output pin is configured to provide an output voltage, and the clock input pin is configured to input a clock signal; Do one of the following two options: (i) Each chip in the N chips includes a clock output pin and a phase setting pin, and the clock output pin of the M-1th chip in the N chips is connected to the clock input pin of the Mth chip, where M is an integer less than or equal to N; The clock output pin is configured to output a clock signal, and the phase setting pin is configured to input a voltage signal, wherein when the phase setting pin of the Kth chip among the N chips inputs the Kth voltage signal, the clock signal output by the clock output pin of the Kth chip has a Kth phase difference with the clock signal of the Kth chip, the clock signal output by the clock output pin of the N chips has N phase differences with the clock signals of the N chips, the sum of the N phase differences is 360°, and K is an integer less than or equal to N; (ii) the multi-channel multi-phase output circuit further includes a phase generator; The phase generator is connected to the clock input pin of each chip in the N chips, and the phase generator is configured to divide 360° into N phases and output N clock signals based on the N phases, and one clock signal among the N clock signals is input to the clock input pin of one chip in the N chips.

2. The multi-channel multi-phase output circuit according to claim 1, characterized in that: When implementing solution (i), the multi-channel multi-phase output circuit further includes N voltage-dividing branches, one of the N voltage-dividing branches is connected to a phase setting pin of one of the N chips, and the N branches are connected to a power supply; Based on the voltage division ratio between the power supply and each of the N voltage division branches, a corresponding voltage signal is output to a phase setting pin of each of the N chips.

3. The multi-channel multi-phase output circuit according to claim 2, characterized in that: Each of the N voltage-dividing branches is connected between the power supply and the ground, and each voltage-dividing branch includes two resistors connected in series, and a connection point between the two resistors is connected to a phase setting pin of a corresponding chip.

4. The multi-channel multi-phase output circuit according to any one of claims 1 to 3, characterized in that: The N chips are all of the first model, the multi-channel multi-phase output circuit further includes N first auxiliary branches, and each chip in the N chips is connected to a first auxiliary branch in the N first auxiliary branches; Each of the N chips further comprises a switch pin, a voltage output pin and a power ground pin, and each of the N first auxiliary branches further comprises a first inductor and a first capacitor; The first inductor and the first capacitor are connected in series between the switch pin and the power ground pin, the power ground pin is grounded, the connection point between the first inductor and the first capacitor is connected to the voltage output pin, and the voltage at the connection point between the first inductor and the first capacitor is the positive pole of the output voltage.

5. The multi-channel multi-phase output circuit according to claim 4, characterized in that: Each of the N chips further includes an operating frequency setting pin, a feedback pin, a compensation pin, a regulator output pin, a signal ground pin, a regulator power supply input pin, a regulator signal power supply input pin and a bootstrap drive power supply pin, and each of the N first auxiliary branches further includes a first resistor, a second resistor, a third resistor, a fourth resistor, a second capacitor, a third capacitor, a fourth capacitor, a fifth capacitor and a sixth capacitor; The first resistor is connected between the operating frequency setting pin and the ground, the second resistor is connected between the voltage output pin and the feedback pin, the third resistor and the second capacitor are connected in series between the compensation pin and the ground, the third capacitor is connected between the compensation pin and the ground, the fourth capacitor is connected between the regulator output pin and the signal ground pin, the signal ground pin is also connected to the ground, the fifth capacitor is connected between the positive pole of the input voltage and the ground, the fourth resistor is connected between the regulator power supply input pin and the regulator signal power supply input pin, the regulator power supply input pin is also connected to the positive pole of the input voltage, and the sixth capacitor is connected between the switch pin and the bootstrap drive power supply pin.

6. The multi-channel multi-phase output circuit according to any one of claims 1 to 3, characterized in that: The N chips are all of the second model, the multi-channel multi-phase output circuit further includes N second auxiliary branches, and each chip in the N chips is connected to one of the N second auxiliary branches; Each of the N chips further includes a high-side gate driver output pin and a low-side gate driver output pin, and each of the N second auxiliary branches further includes a seventh capacitor, an eighth capacitor, a ninth capacitor, a tenth capacitor, an eleventh capacitor, a twelfth capacitor, a fifth resistor, a second inductor, a first switch tube, and a second switch tube; The high-side gate driver output pin is connected to the first end of the first switch tube, the third end of the first switch tube is connected to the positive electrode of the input voltage, the second end of the first switch tube is connected to the third end of the second switch tube, the first end of the second switch tube is connected to the low-side gate driver output pin, the third end of the second switch tube is grounded, the seventh capacitor is connected between the positive electrode of the input voltage and the ground, the eighth capacitor is connected in parallel with the seventh capacitor, the ninth capacitor is connected between the third end of the second switch tube and the ground, the first end of the second inductor is connected to the third end of the second switch tube, the second end of the second inductor is the positive electrode of the output voltage, the fifth resistor and the tenth capacitor are connected in series between the first end and the second end of the second inductor, the eleventh capacitor is connected between the second end of the second inductor and the ground, and the twelfth capacitor is connected in parallel with the eleventh capacitor.

7. The multi-channel multi-phase output circuit according to claim 6, characterized in that: Each of the N chips further includes a gate driver power pin, a switch node pin, a regulator output pin, an analog ground pin, a feedback input pin, and a compensation pin, and each of the N second auxiliary branches further includes a thirteenth capacitor, a fourteenth capacitor, a fifteenth capacitor, a sixteenth capacitor, a seventeenth capacitor, a first diode, a sixth resistor, and a seventh resistor; The anode of the first diode is connected to the second voltage, the cathode of the first diode is connected to the gate driver power pin, the thirteenth capacitor is connected between the gate driver power pin and the switch node pin, the switch node pin is also connected to the third end of the second switch tube, the fourteenth capacitor is connected to the regulator output pin and the analog ground pin, the analog ground pin is grounded, the sixth resistor and the fifteenth capacitor are connected in parallel between the second end of the second inductor and the feedback input pin, the sixteenth capacitor is connected between the compensation pin and the ground, and the seventh resistor is connected in series with the seventeenth capacitor and then connected in parallel with the sixteenth capacitor.

8. A point-of-load power supply, characterized in that: It comprises the multi-channel multi-phase output circuit as described in any one of claims 1 to 7.

9. An electronic device, characterized in that: It comprises a multi-channel load and a load point power supply as claimed in claim 8, wherein the load point power supply is connected to the multi-channel load.

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