Single pole 72 throw absorptive switch

Abstract

The utility model relates to the technical field of radio frequency switches, and specifically to a single-pole 72-throw absorptive switch, including a single-pole 72-throw absorptive switch and a control module connected to the single-pole 72-throw absorptive switch, wherein the control module includes a controller and a control distribution circuit, wherein an address decoder is provided in the control distribution circuit, and the address decoder is responsible for outputting an enable signal so as to accurately start each control decoder to ensure that they accurately complete the switch switching, thereby realizing efficient management of a plurality of control terminals. The utility model solves the technical problem that the management is complicated and error-prone due to the large number of control terminals in the absorptive switch.

Description

Technical Field

[0001] The utility model relates to the technical field of radio frequency switches, in particular to a single-pole seventy-two-throw absorptive switch. Background Art

[0002] RF switches play a particularly important role in RF communication systems. They are responsible for switching between multiple signal paths to ensure accurate signal transmission. In RF systems that require low insertion loss, high isolation, and fast response, absorptive switches are generally used. Absorptive switches can ensure that energy loss is reduced during the switching process, improve the transmission quality of the signal, and its high isolation characteristics can effectively prevent signal interference and maintain the stability of the system. With the continuous development of communication technology, absorptive switches are no longer limited to single-pole single-throw or single-pole double-throw. For the radar system's demand for multi-channel signal switching, it faces increasingly complex control challenges. When there are many control terminals in an absorptive switch, how to effectively manage and control these control terminals has become an urgent problem to be solved.

[0003] A common solution is to use a decoder to output the corresponding control signal to drive the switching of the RF switch. However, when faced with an absorptive switch with many control terminals such as a single-pole 72-throw switch, simply using multiple decoders cumulatively will make the entire control system extremely complex and difficult to manage effectively. This complexity not only increases the difficulty of management and maintenance, but also easily leads to control errors, thus affecting the overall stability and reliability of the system. Therefore, it is extremely important to solve the problem of complex management and easy errors caused by the large number of control terminals in absorptive switches. Utility Model Content

[0004] The purpose of the present application is to provide a single-pole, seventy-two-throw absorptive switch, which solves the technical problems of complex management and high error-proneness caused by numerous control terminals in the absorptive switch.

[0005] In order to solve the above technical problems, the solution adopted by this application is as follows:

[0006] The utility model provides a single-pole 72-throw absorptive switch, comprising the single-pole 72-throw absorptive switch and a control module connected to the single-pole 72-throw absorptive switch, characterized in that: the control module comprises a controller and a control distribution circuit, the output end of the controller is connected to the input end of the control distribution circuit, the output end of the control distribution circuit is connected to the single-pole 72-throw absorptive switch; the control distribution circuit comprises a plurality of decoders and an enable judgment circuit;

[0007] The enabling judgment circuit comprises a first NOT gate, a second NOT gate, and a NAND gate, wherein one input end of the NAND gate is connected to an input end of the first NOT gate, and the input end is set here as one input end of the enabling judgment circuit; two input ends of the NAND gate are connected to an input end of the second NOT gate, and the input end is set here as two input ends of the enabling judgment circuit; one input end and two input ends of the enabling judgment circuit are respectively connected to an enabling output end of the controller;

[0008] The plurality of decoders include address decoders and control decoders, and the control decoders include one control decoder, two control decoders, three control decoders, four control decoders, five control decoders, six control decoders, seven control decoders, eight control decoders, and nine control decoders; data input terminals of the one control decoder, two control decoders, three control decoders, four control decoders, five control decoders, six control decoders, seven control decoders, eight control decoders, and nine control decoders are connected to a data output terminal of the controller; a signal input terminal of the address decoder is connected to an address output terminal of the controller;

[0009] The three enable terminals of the first control decoder, the three enable terminals of the address decoder, and the output terminal of the NAND gate are connected; the enable terminals of the second control decoder, the third control decoder, the fourth control decoder, the fifth control decoder, the sixth control decoder, the seventh control decoder, the eighth control decoder, and the ninth control decoder are respectively connected to the output terminal of the address decoder;

[0010] An enable terminal, a second enable terminal, and an output terminal of the first NOT gate of the address decoder are connected; an enable terminal, a second enable terminal, and an output terminal of the second NOT gate of the control decoder are connected.

[0011] In some embodiments, an enable terminal and a second enable terminal of the second control decoder are connected, an enable terminal and a second enable terminal of the third control decoder are connected, an enable terminal and a second enable terminal of the fourth control decoder are connected, an enable terminal and a second enable terminal of the fifth control decoder are connected, an enable terminal and a second enable terminal of the sixth control decoder are connected, an enable terminal and a second enable terminal of the seventh control decoder are connected, an enable terminal and a second enable terminal of the eighth control decoder are connected, and an enable terminal and a second enable terminal of the eighth control decoder are connected, and an enable terminal and a second enable terminal of the ninth control decoder are connected.

[0012] In some embodiments, the output ends of the one control decoder, the two control decoders, the three control decoders, the four control decoders, the five control decoders, the six control decoders, the seven control decoders, the eight control decoders, and the nine control decoders are respectively connected to the control ends of the single-pole seventy-two-throw absorptive switch.

[0013] In some embodiments, the single-pole seventy-two-throw absorptive switch includes seventy-two basic absorptive switches, the input ends of the seventy-two basic absorptive switches are all connected as the total input end of the single-pole seventy-two-throw absorptive switch, and the output ends of the seventy-two basic absorptive switches are respectively set as seventy-two output ends of the absorptive switch.

[0014] In some embodiments, the basic absorptive switch includes an LC filter circuit, which is arranged at a control end of the basic absorptive switch, and a signal received by the control end of the basic absorptive switch is transmitted to the basic absorptive switch through the LC filter circuit.

[0015] In some embodiments, the controller includes a main control chip, and the main control chip is a FPGA.

[0016] In some embodiments, the decoder is a model 74HC138D.

[0017] The technical solution of the present application has at least the following advantages and beneficial effects:

[0018] The utility model designs a control distribution circuit. Unlike the traditional single-pole multi-throw switch that only uses a decoder as a selection switch, the circuit adds an address decoder, which is responsible for outputting an enable signal to accurately start each control decoder to ensure that they accurately complete the switch switching, thereby achieving efficient management of multiple control terminals, reducing the number of wiring in the circuit, and reducing wiring complexity and cost. In addition, the utility model also adopts an absorption design to ensure that the switch has a low standing wave ratio and high isolation in the closed state, thereby improving the transmission quality of the radio frequency signal. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] Figure 1 It is a schematic diagram of the overall structure of the utility model;

[0020] Figure 2 This is the basic absorptive switch circuit diagram of the utility model;

[0021] Figure 3 This is a control distribution circuit diagram of the utility model. DETAILED DESCRIPTION

[0022] The following will be combined with the drawings in the embodiments of the utility model to clearly and completely describe the technical solutions in the embodiments of the utility model. Obviously, the described embodiments are only part of the embodiments of the utility model, not all of the embodiments. Based on the embodiments in the utility model, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the utility model.

[0023] It should be noted that similar numbers and letters represent similar items in the following figures, so once an item is defined in one figure, it does not need to be further defined and explained in the subsequent figures. If the terms "center", "upper", "lower", "inner", "outer", etc. indicate an orientation or position relationship based on the orientation or position relationship shown in the figure, or the orientation or position relationship in which the product of the application is usually placed when in use, it is only for the convenience of describing the present application and simplifying the description, and does not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation of the present application. It should also be noted that unless otherwise clearly specified and limited, if the terms "set", "install", and "connect" appear, they should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be directly connected, or indirectly connected through an intermediate medium, or it can be a connection between the two elements. For ordinary technicians in this field, the specific meanings of the above terms in this application can be understood according to specific circumstances.

[0024] Example 1

[0025] Please refer to Figure 1-Figure 3 The utility model provides a single-pole 72-throw absorptive switch, including an absorptive switch and a control module connected to the absorptive switch; the control module includes a controller and a control distribution circuit, the output end of the controller is connected to the input end of the control distribution circuit, and the output end of the control distribution circuit is connected to the absorptive switch.

[0026] The control distribution circuit includes a plurality of decoders and an enable judgment circuit;

[0027] The enable judgment circuit includes a first NOT gate, a second NOT gate, and a NAND gate. An input terminal of the NAND gate is connected to an input terminal of the first NOT gate, and the input terminal is set here as an input terminal of the enable judgment circuit; the second input terminal of the NAND gate is connected to an input terminal of the second NOT gate, and the input terminal is set here as the second input terminal of the enable judgment circuit; the first input terminal and the second input terminal of the enable judgment circuit are respectively connected to the enable output terminal of the controller;

[0028] The plurality of decoders include address decoders and control decoders, and the control decoders include a first control decoder, a second control decoder, a third control decoder, a fourth control decoder, a fifth control decoder, a sixth control decoder, a seventh control decoder, an eighth control decoder, and a ninth control decoder. The data input terminals of the first control decoder, the second control decoder, the third control decoder, the fourth control decoder, the fifth control decoder, the sixth control decoder, the seventh control decoder, the eighth control decoder, and the ninth control decoder are connected to the data output terminal of the controller; the signal input terminal of the address decoder is connected to the address output terminal of the controller;

[0029] The three enable terminals of the first control decoder, the three enable terminals of the address decoder, and the output terminal of the NAND gate are connected; the enable terminals of the second control decoder, the third control decoder, the fourth control decoder, the fifth control decoder, the sixth control decoder, the seventh control decoder, the eighth control decoder, and the ninth control decoder are respectively connected to the output terminal of the address decoder;

[0030] An enable terminal, a second enable terminal, and an output terminal of a NOT gate of an address decoder are connected; an enable terminal, a second enable terminal, and the output terminals of the two NOT gates of a control decoder are connected;

[0031] The second control decoder has an enable terminal, a second enable terminal, and an output terminal of the address decoder connected, the third control decoder has an enable terminal, a second enable terminal, and two output terminals of the address decoder connected, the fourth control decoder has an enable terminal, a second enable terminal, and three output terminals of the address decoder connected, the fifth control decoder has an enable terminal, a second enable terminal, and four output terminals of the address decoder connected, the sixth control decoder has an enable terminal, a second enable terminal, and five output terminals of the address decoder connected, the seventh control decoder has an enable terminal, a second enable terminal, and six output terminals of the address decoder connected, the eighth control decoder has an enable terminal, a second enable terminal, and seven output terminals of the address decoder connected, the ninth control decoder has an enable terminal, a second enable terminal, and eight output terminals of the address decoder connected;

[0032] The first control decoder, the second control decoder, the third control decoder, the fourth control decoder, the fifth control decoder, the sixth control decoder, the seventh control decoder, the eighth control decoder, and the ninth control decoder each have eight output terminals, and each output terminal of each control decoder is respectively connected to the control terminal of the absorptive switch;

[0033] It should be noted that the address decoder and the nine control decoders are all of model 74HC138D.

[0034] Specifically, Figure 3As shown, the enable judgment circuit includes a first NOT gate U11, a second NOT gate U13, and a NAND gate U12; the input end of the first NOT gate U11 is connected to the A input end of the NAND gate U12, and an input end is set here, which is called the IN1 input end, for receiving a signal transmitted from an enable output end of the controller; the input end of the second NOT gate U13 is connected to the B input end of the NAND gate U12, and an input end is set here, which is called the IN2 input end, for receiving a signal transmitted from the second enable output end of the controller; the output end of the first NOT gate U11 is set to the EN11 output end and The EN12 output terminal, the EN11 output terminal, and the EN12 output terminal are respectively connected to an enable terminal one and an enable terminal two of the address decoder; the output terminal of the second NOT gate U13 is set to the EN21 output terminal and the EN22 output terminal, and the EN21 output terminal and the EN22 output terminal are respectively connected to an enable terminal one and an enable terminal two of a control decoder; the Y output terminal of the NAND gate U12 is set to the EN13 output terminal and the EN23 output terminal, and the EN13 output terminal and the EN23 output terminal are respectively connected to three enable terminals of the address decoder and three enable terminals of a control decoder.

[0035] It should be noted that the purpose of setting the enable judgment circuit is to accurately manage and control the decoder, thereby accurately controlling the switch switching.

[0036] Specifically, in normal operation, only one of the IN input terminal and the IN2 input terminal in the enable judgment circuit can be high and the other can be low, or both input terminals can be low; when one of the two input terminals is high and the other is low, the output terminal of the enable judgment circuit outputs a signal to an address decoder and a control decoder to select the decoder that needs to work; when both input terminals are low, it means that the single-pole 72-throw absorptive switch does not work; when both input terminals are high, it means that the controller enables the output terminal to output an error signal, and at this time, the NAND gate U12 outputs a low level, and the address decoder and the control decoder stop working.

[0037] Specifically, Figure 2As shown, the basic absorption switch circuit includes diodes D1, D2, D3, D4, D5, D6, inductors L1, L2, L3, resistors R1, R2, R3, capacitors C1, C2; the anode of the diode D1 is set as the RF_in input terminal, the cathode of the diode D1, the anode of the diode D2, the anode of the diode D3, and one end of the capacitor C1 are connected, the cathode of the diode D2 is grounded, and the cathode of the diode D3 is grounded; the other end of the capacitor C1, the anode of the diode D4, the anode of the diode D5, and the cathode of the diode D6 are connected, and the diode The cathode of D4 is grounded, and the cathode of diode D5 is grounded; the anode of diode D5, one end of inductor L3, one end of resistor R3, one end of resistor R2, and one end of inductor L2 are connected, and the other end of inductor L3 is grounded, and the other end of resistor R3 is grounded; the other end of inductor L2, one end of resistor R1, one end of capacitor C2, and one end of inductor L1 are connected, and the other end of inductor L1 is grounded, and the other end of capacitor C2 is grounded, and the other end of inductor L1 is set as a control end, which is called E1 input end; the other end of resistor R2 is set as RF_out output end.

[0038] It should be noted that the single-pole seventy-two-throw absorptive switch includes seventy-two basic absorptive switches, the input ends of these seventy-two basic absorptive switches are all connected as the total input end of the single-pole seventy-two-throw absorptive switch, and the output ends of the seventy-two basic absorptive switches are respectively set as the seventy-two output ends of the single-pole seventy-two-throw absorptive switch.

[0039] An LC filter circuit is also provided in the absorption switch, which includes an inductor L1 and a capacitor C2; the LC filter circuit is provided at the control end of the absorption switch, and a signal received by the control end of the absorption switch is transmitted to the absorption switch through the LC filter circuit.

[0040] It should be noted that the RF_in input terminal to the RF_out output terminal are channels controlled by the absorptive switch, which include seventy-two channels in this embodiment; the RF_in input terminals of the seventy-two channels are all connected as the total input terminal of the single-pole seventy-two-throw absorptive switch, and the RF_out output terminals of the seventy-two channels are respectively set as the seventy-two output terminals of the single-pole seventy-two-throw absorptive switch; the control terminals of the absorptive switches are respectively connected to the output terminals of the control distribution circuit, and the control distribution circuit outputs a control signal to switch the switch, thereby achieving the purpose of switching channels.

[0041] For ease of understanding, the overall structure of the utility model is described below:

[0042] like Figure 1As shown, decoder 10 is an address decoder, and decoders 1 to 9 correspond to control decoders 1 to 9 respectively; FPGA is the main control chip of the controller, and through the control distribution circuit, FPGA transmits control signals to the enable terminals of decoder 10 and decoder 1;

[0043] FPGA transmits the address signal to decoder 10. If decoder 10 receives the enable signal, decoder 10 starts working and distributes the control signal to decoder 2 to decoder 9. According to the data signal provided by the controller, only one decoder among decoder 2 to decoder 9 receives the enable signal and starts decoding. If the enable end of decoder 1 receives a signal, decoder 1 starts decoding according to the data signal provided by the controller.

[0044] The control decoder, i.e. decoder 1 to decoder 9, starts working after receiving the enable signal, and outputs the control signal to the control end of the single-pole 72-throw absorptive switch connected to the output end of decoder 1 to decoder 9 according to the data signal provided by the controller, thereby controlling the switch switching.

[0045] So far, various embodiments of the present invention have been described in detail. In order to avoid obscuring the concept of the present invention, some details known in the art are not described. Based on the above description, those skilled in the art can fully understand how to implement the technical solution of the present invention, and the scope of the present invention is defined by the attached claims.

Claims

1. A single-pole 72-throw absorptive switch, comprising a single-pole 72-throw absorptive switch and a control module connected to the single-pole 72-throw absorptive switch, characterized in that: The control module includes a controller and a control distribution circuit, the output end of the controller is connected to the input end of the control distribution circuit, and the output end of the control distribution circuit is connected to the single-pole 72-throw absorptive switch; the control distribution circuit includes a plurality of decoders and an enable judgment circuit; The enabling judgment circuit comprises a first NOT gate, a second NOT gate, and a NAND gate, wherein one input end of the NAND gate is connected to an input end of the first NOT gate, and the input end is set here as one input end of the enabling judgment circuit; two input ends of the NAND gate are connected to an input end of the second NOT gate, and the input end is set here as two input ends of the enabling judgment circuit; one input end and two input ends of the enabling judgment circuit are respectively connected to an enabling output end of the controller; The plurality of decoders include address decoders and control decoders, and the control decoders include one control decoder, two control decoders, three control decoders, four control decoders, five control decoders, six control decoders, seven control decoders, eight control decoders, and nine control decoders; data input terminals of the one control decoder, two control decoders, three control decoders, four control decoders, five control decoders, six control decoders, seven control decoders, eight control decoders, and nine control decoders are connected to a data output terminal of the controller; a signal input terminal of the address decoder is connected to an address output terminal of the controller; The three enable terminals of the first control decoder, the three enable terminals of the address decoder, and the output terminal of the NAND gate are connected; the enable terminals of the second control decoder, the third control decoder, the fourth control decoder, the fifth control decoder, the sixth control decoder, the seventh control decoder, the eighth control decoder, and the ninth control decoder are respectively connected to the output terminal of the address decoder; An enable terminal, a second enable terminal, and an output terminal of the first NOT gate of the address decoder are connected; an enable terminal, a second enable terminal, and an output terminal of the second NOT gate of the control decoder are connected.

2. The single-pole 72-throw absorptive switch according to claim 1, characterized in that: An enable terminal and a second enable terminal of the second control decoder are connected to an output terminal of the address decoder; an enable terminal and a second enable terminal of the third control decoder are connected to two output terminals of the address decoder; an enable terminal and a second enable terminal of the fourth control decoder are connected to three output terminals of the address decoder; an enable terminal and a second enable terminal of the fifth control decoder are connected to four output terminals of the address decoder; an enable terminal and a second enable terminal of the sixth control decoder are connected to five output terminals of the address decoder; an enable terminal and a second enable terminal of the seventh control decoder are connected to six output terminals of the address decoder; an enable terminal and a second enable terminal of the eighth control decoder are connected to seven output terminals of the address decoder; an enable terminal and a second enable terminal of the ninth control decoder are connected to eight output terminals of the address decoder.

3. The single-pole 72-throw absorptive switch according to claim 1, characterized in that: The output ends of the first control decoder, the second control decoder, the third control decoder, the fourth control decoder, the fifth control decoder, the sixth control decoder, the seventh control decoder, the eighth control decoder and the ninth control decoder are respectively connected to the control end of the single-pole seventy-two-throw absorptive switch.

4. The single-pole 72-throw absorptive switch according to claim 1, characterized in that: The single-pole 72-throw absorptive switch includes 72 basic absorptive switches, the input ends of the 72 basic absorptive switches are all connected as the total input end of the single-pole 72-throw absorptive switch, and the output ends of the 72 basic absorptive switches are respectively set as the 72 output ends of the absorptive switch.

5. The single-pole 72-throw absorptive switch according to claim 4, characterized in that: The basic absorptive switch comprises an LC filter circuit, which is arranged at a control end of the basic absorptive switch. A signal received by the control end of the basic absorptive switch is transmitted to the basic absorptive switch through the LC filter circuit.

6. The single-pole 72-throw absorptive switch according to claim 1, characterized in that: The controller includes a main control chip, and the main control chip is a FPGA.

7. The single-pole 72-throw absorptive switch according to claim 1, characterized in that: The model of the decoder is 74HC138D.

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