Control circuit, LED drive circuit, lighting device

Abstract

The utility model relates to a control circuit, an LED driving circuit and an lighting device, and is applied to control an LED array, including: a control unit, an operational amplifier and a MOS tube. The control unit can collect voltage signals that characterize the input voltage of the LED array, and its output terminal is connected to the in-phase input terminal of the operational amplifier, the output terminal of the operational amplifier is connected to the gate of the MOS tube, the inverting input terminal of the operational amplifier is connected to the source of the MOS tube, and the drain of the MOS tube is configured to be used to connect to the LED array; the control unit can quantize the voltage signal into a digital signal and generate corresponding output signals based on the digital signal, so as to adjust the current of the LED array through the operational amplifier and the MOS tube to achieve the constant power of the LED array. By quantizing the sampled voltage into a digital signal, the current of the LED array is adjusted accordingly based on the input voltage of the LED array to achieve constant power without a large chip area and power consumption can be reduced.

Description

Technical Field

[0001] The utility model relates to the technical field of lighting, and in particular to a control circuit, an LED drive circuit and a lighting device. Background Art

[0002] Normally, LED lighting systems are powered by direct access to the mains, and the input power of the LED is equal to the output power of the mains. However, when the input drive voltage of the LED changes, the input power of the LED drive circuit will also change due to the lack of constant power control. This power fluctuation may have an adverse effect on the stability of the power supply network.

[0003] At present, the LED driving constant power control method on the market mainly adopts analog control scheme. One method is to achieve constant power control by connecting more components, such as sampling resistors and compensation capacitors, on the periphery of the chip. However, this solution will increase the overall cost of the product. Another method is to integrate more analog processing circuits, such as amplifiers, inside the chip. However, doing so will increase the chip area and increase power consumption.

[0004] Therefore, it is necessary to improve the existing control circuit. Utility Model Content

[0005] In view of the above problems, the utility model provides a control circuit for controlling an LED array, comprising: a control unit, an operational amplifier and a MOS tube, wherein the control unit can collect a voltage signal representing the input voltage of the LED array, and its output end is connected to the non-inverting input end of the operational amplifier, the output end of the operational amplifier is connected to the gate of the MOS tube, the inverting input end of the operational amplifier is connected to the source of the MOS tube, and the drain of the MOS tube is configured to be connected to the LED array; the control unit can quantize the voltage signal into a digital signal, and generate a corresponding output signal based on the digital signal, so as to adjust the current of the LED array through the operational amplifier and the MOS tube, so as to achieve a constant power of the LED array.

[0006] The present application quantizes the sampled voltage into a digital signal, and accordingly adjusts the current of the LED array based on the input voltage of the LED array to achieve constant power. Such a setting does not require a large chip area and can reduce power consumption.

[0007] Optionally, the control unit includes: a sampling module connected to the LED array, used to obtain a voltage value representing the input voltage of the LED array; an ADC module connected to the output end of the sampling module, which can convert the voltage value into a corresponding digital signal and output it; an algorithm module connected to the output end of the ADC module, which can save and output the maximum value of the digital signal within a preset period; and a mapping module connected to the output end of the algorithm module, which can generate a corresponding current control codeword based on the maximum value of the digital signal to output it to the operational amplifier.

[0008] Optionally, the sampling module includes: a first resistor R1, a first MOS transistor M1, a second MOS transistor M2, a third MOS transistor M3, a fourth MOS transistor M4 and a second resistor R2, the first end of the first resistor R1 is configured to collect a voltage VIN_RECT representing the input voltage of the LED array, the second end of the first resistor R1 is connected to a first end of a first current mirror formed by the first MOS transistor M1 and the second MOS transistor M2, the second end of the first current mirror is connected to a first end of a second current mirror formed by the third MOS transistor M3 and the fourth MOS transistor M4, the second end of the second current mirror is connected to a first end of the second resistor R2, the second end of the second resistor R2 is connected to a common ground, and the first end of the second resistor R2 forms the output end of the sampling module.

[0009] Optionally, the ADC module comprises: a sampling circuit, whose input end is configured to receive the voltage output by the sampling module and sample it as a fixed voltage;

[0010] a comparison circuit, wherein the non-inverting input terminal thereof is configured to receive the fixed voltage, and the inverting input terminal thereof is configured to be connected to a preset voltage; and

[0011] A logic circuit, whose input end is connected to the output end of the comparison circuit, and whose output end can control the preset voltage.

[0012] Optionally, the mapping module includes: a mapping circuit, a fifth MOS tube M5, a sixth MOS tube M6 and a third resistor R3. The mapping circuit is connected to the output end of the ADC module, and can generate a corresponding drive current control codeword based on a preset quantization result and a corresponding current control codeword relationship in response to a received quantization result. The drive current control codeword is input to a first end of a third current mirror composed of the fifth MOS tube M5 and the sixth MOS tube M6. The first end of the third resistor R3 is connected to the second end of the third current mirror to form the output end of the mapping module, and the second end of the third resistor R3 is connected to a common ground.

[0013] In order to achieve the above-mentioned utility model purpose, the present application provides an LED driving circuit, including a rectifier circuit, an LED array, a resistor and the control circuit described above, wherein the rectifier circuit is used to rectify the AC input voltage, and its output end is connected to the first end of the LED array, the second end of the LED array is connected to the first end of the control circuit, the second end of the control circuit is connected to the first end of the resistor, and the second end of the resistor is connected to a common ground.

[0014] In order to achieve the above-mentioned utility model purpose, the present application provides a lighting device, which uses the LED driving circuit described above.

[0015] In order to achieve the above-mentioned utility model purpose, the present application provides a control circuit, which applies the LED array control method described above.

[0016] In summary, the present application quantizes the sampled voltage into a digital signal, and adjusts the current of the LED array accordingly based on the input voltage of the LED array to achieve constant power. Such a setting does not require a large chip area and can reduce power consumption. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Figure 1 It is a circuit structure diagram of the LED driving circuit provided in the implementation mode of the utility model.

[0018] Figure 2 It is a schematic diagram of a partial circuit structure of a control circuit provided in an embodiment of the utility model.

[0019] Figure 3 It is a schematic diagram of the circuit structure of the ADC module provided in the implementation mode of the utility model.

[0020] Figure 4 It is a logical schematic diagram of the algorithm module provided in the implementation mode of the present utility model.

[0021] Figure 5 It is a timing logic diagram of the algorithm module provided in the implementation mode of the utility model.

[0022] Figure 6 It is a flowchart of the steps of the control method of the LED array provided in the embodiment of the present utility model. DETAILED DESCRIPTION

[0023] The following will be combined with the drawings in the embodiments of the utility model to clearly and completely describe the technical solutions in the embodiments of the utility model. Obviously, the described embodiments are only part of the embodiments of the utility model, not all of the embodiments. Based on the embodiments of the utility model, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the utility model.

[0024] Figure 1 It is a circuit structure diagram of a control circuit provided in an embodiment of the utility model.

[0025] like Figure 1 As shown, in an embodiment of the present invention, a control circuit is provided for controlling an LED array to achieve constant power of the LED array during operation, specifically including: a sampling module 01, an ADC module 02, an algorithm module 03, a mapping module 04, an operational amplifier OP and a MOS tube.

[0026] In some embodiments, the sampling module 01, the ADC module 02, the algorithm module 03, and the mapping module 04 can be integrated into a control unit. Specifically, the control unit can collect a voltage signal representing the input voltage of the LED array, and its output end is connected to the non-inverting input end of the operational amplifier OP, the output end of the operational amplifier OP is connected to the gate of the MOS tube, the inverting input end of the operational amplifier OP is connected to the source of the MOS tube, and the drain of the MOS tube is configured to be connected to the LED array; the control unit can quantize the voltage signal into a digital signal, and generate a corresponding output signal based on the digital signal, so as to adjust the current of the LED array through the operational amplifier and the MOS tube, so as to achieve a constant power of the LED array.

[0027] It should be noted that the present embodiment realizes constant power control of the LED array by combining digital circuits and analog circuits, by sampling analog quantities and then conducting quantization control. Those skilled in the art can make equivalent changes or replacements to the relevant technical features, and the technical solutions after these changes or replacements will fall within the protection scope of the present utility model.

[0028] Specifically, the sampling module 01 is configured to obtain a voltage value VIN_RECT representing an input voltage of the LED array, and output a sampled voltage VIN_ADC corresponding to VIN_RECT.

[0029] Specifically, Figure 2As shown, the sampling module 01 includes a first resistor R1, a first MOS transistor M1, a second MOS transistor M2, a third MOS transistor M3, a fourth MOS transistor M4 and a second resistor R2. The first resistor R1, the first MOS transistor M1, the second MOS transistor M2, the third MOS transistor M3, the fourth MOS transistor M4 and the second resistor R2, the first end of the first resistor R1 is configured to collect a voltage VIN_RECT representing the input voltage of the LED array, the second end of the first resistor R1 is connected to a first end of a first current mirror formed by the first MOS transistor M1 and the second MOS transistor M2, the second end of the first current mirror is connected to a first end of a second current mirror formed by the third MOS transistor M3 and the fourth MOS transistor M4, the second end of the second current mirror is connected to a first end of the second resistor R2, the second end of the second resistor R2 is connected to a common ground, and the first end of the second resistor R2 forms an output end of the sampling module 01.

[0030] The first resistor R1 converts the input voltage VIN_RECT into a current, passes through an NMOS current mirror composed of the first MOS transistor M1 and the second MOS transistor M2, and then passes through a PMOS current mirror composed of the third MOS transistor M3 and the fourth MOS transistor M4, and then is converted into a ground voltage through the second resistor R2, that is, an input sampling voltage VIN_ADC, for quantization by the ADC module 02.

[0031] The input end of the ADC module 02 is connected to the output end of the sampling module 01 to quantize VIN_ADC to obtain a quantization code word DO corresponding to the voltage value. <n:0>.

[0032] Specifically, Figure 3 As shown, the ADC module 02 includes:

[0033] A sampling circuit, whose input end is configured to receive the voltage output by the sampling module 01 and sample it as a fixed voltage;

[0034] a comparison circuit, wherein a non-inverting input terminal thereof is configured to receive a fixed voltage, and an inverting input terminal thereof is configured to be connected to a preset voltage; and

[0035] The logic circuit has an input end connected to the output end of the comparison circuit, and an output end capable of controlling a preset voltage.

[0036] After the input voltage is sampled, it works in the low-voltage circuit. First, the voltage is sampled into a fixed voltage. With the help of the logic circuit, the sampled voltage is compared with VREF_ADC / 2 for the first time. If the sampled voltage is greater than VREF_ADC / 2, FB <n>is 1, otherwise FB <n>is 0, thus completing the first quantization; if FB <n>If it is 1, the sample voltage is compared with VREF_ADC*3 / 4. If the sample voltage is greater than VREF_ADC*3 / 4, FB <n-1>is 1, otherwise FB <n-1>is 0; if FB <n>If it is 0, the sample voltage is compared with VREF_ADC*1 / 4. If the sample voltage is greater than VREF_ADC*1 / 4, FB <n-1>is 1, otherwise FB <n-1>is 0, thus completing the second quantization; quantization is continued step by step until the comparison timing controlled by the logic module is completed, and the quantization codeword DO is output. <n:0>Since only a comparator is used in the ADC module 02 in this embodiment, and no amplifier is used, a smaller area and lower power consumption can be obtained.

[0037] The algorithm module 03 has its input end connected to the output end of the ADC module 02 , and can update corresponding data to the mapping module based on the quantization result of the ADC module 02 within a preset period.

[0038] Specifically, Figure 4 As shown, the algorithm logic is:

[0039] After the module is initialized, it is determined whether the quantization result of the ADC module 02 is greater than the previous one. If so, the data is updated. If not, the original data is retained. This comparison is repeated until the preset cycle (in this embodiment, the preset cycle is half a cycle) is completed, and the updated data is output to the mapping module 04. In order to avoid possible glitches in the input voltage and thus cause misjudgment, in this embodiment, the algorithm considers the data comparison of four consecutive input sinusoidal wave voltage cycles. If the data of four consecutive input sinusoidal wave voltage cycles are consistent, it means that the maximum value of the input sinusoidal wave voltage has indeed changed. The algorithm module 03 then outputs the current control codeword to the mapping module 04 to update the LED drive current value to match the new input voltage, and initializes other memories inside the algorithm to prepare for the quantization of the next input cycle. Otherwise, the pre-stored data will remain unchanged.

[0040] The timing diagram is as follows Figure 5 As shown, the sine waveform input voltage is rectified to generate a rectified voltage, which is sampled and quantized with half a cycle as a preset cycle. If the maximum value of the quantization result is updated within the first preset cycle, the current control codeword is updated after four cycles to update the driving current of the LED array.

[0041] Specifically, the operation steps of the algorithm module 03 are:

[0042] A comparison step, within a preset period, determines whether the quantization result is greater than the previous one, if so, updates the data, if not, retains the original data;

[0043] The determination step is to confirm whether the maximum values ​​of the quantization results of the four preset cycles are the same. If so, the maximum value of the quantization result is updated to the mapping module 04. If not, the comparison step is returned.

[0044] The mapping module 04 has its input terminal connected to the output terminal of the algorithm module 03 , and can generate a corresponding control signal based on the output result of the algorithm module 03 to refresh the driving current of the LED array.

[0045] Specifically, when designing the system, based on the constant power requirement of the LED array, the mapping module 04 stores a driving current control codeword corresponding to the quantized output result of the ADC module 02. The driving current control codeword is stored in an on-chip lookup table. When the circuit is running, the driving current control codeword is obtained through the on-chip lookup table based on the quantized result of the ADC module 02 and output to the mapping module 04.

[0046] The mapping module 04 includes a mapping circuit, a fifth MOS tube M5, a sixth MOS tube M6 and a third resistor R3. The mapping circuit is connected to the output end of the ADC module. It can generate a corresponding current control codeword based on a preset quantization result and a corresponding current control codeword relationship in response to a received quantization result. The current control codeword is input to a first end of a third current mirror composed of the fifth MOS tube M5 and the sixth MOS tube M6. The first end of the third resistor R3 is connected to the second end of the third current mirror to form the output end of the mapping module 04. The second end of the third resistor R3 is connected to a common ground.

[0047] In the case of a virtual short at the operational amplifier OP input, the drive current of the LED array is VREFB / R CS , adjust the external setting resistor R CS The value of can adjust the driving current of the LED array. At the same time, the voltage phase of VREFB is the same as the input voltage phase, so the driving current phase of the LED array is also the same as the input voltage phase. Based on this, the control circuit provided in this embodiment can achieve a very high power factor.

[0048] This embodiment also provides an LED driving circuit, such as Figure 1 As shown, it includes a rectifier circuit 101, an LED array 102, a resistor 104 and a control circuit 103. The rectifier circuit 101 is used to rectify the AC input voltage, and its output end is connected to the first end of the LED array 102, the second end of the LED array 102 is connected to the first end of the control circuit 103, the second end of the control circuit 103 is connected to the first end of the resistor 104, and the second end of the resistor 104 is connected to the common ground.

[0049] Optionally, this embodiment further provides a lighting device, which uses the control circuit or LED driving circuit provided in this embodiment to control the LED array.

[0050] like Figure 6 As shown, this embodiment also provides a method for controlling an LED array, comprising the steps of:

[0051] A sampling step to obtain an electrical signal representing an input voltage of the LED array;

[0052] Quantization step, converting the electrical signal into a digital signal;

[0053] An updating step, updating and saving the maximum value of the digital signal within a preset period;

[0054] a mapping step, mapping the maximum value of the digital signal to a corresponding current control codeword based on a pre-stored on-chip lookup table; and

[0055] The regulating step is to regulate the current of the LED array based on the current control codeword so that the power thereof is kept constant.

[0056] This embodiment further provides a control circuit, which applies the control method of the LED array described above.

[0057] This embodiment further provides a computer-readable storage medium, on which a computer program is stored. When the computer program is executed by a processor, the steps of the LED array control method described above are implemented.

[0058] So far, the technical solution of the utility model has been described in conjunction with the accompanying drawings. However, it is easy for those skilled in the art to understand that the protection scope of the utility model is obviously not limited to the above-mentioned specific implementation methods. Without departing from the principle of the utility model, those skilled in the art can make equivalent changes or substitutions to the relevant technical features, and the technical solutions after these changes or substitutions will fall within the protection scope of the utility model. < / n> < / n> < / n> < / n>

Claims

1. A control circuit for controlling an LED array, characterized in that: include: A control unit, an operational amplifier and a MOS tube, wherein the control unit can obtain a voltage signal representing the input voltage of the LED array, and an output end of the control unit is connected to the non-inverting input end of the operational amplifier, the output end of the operational amplifier is connected to the gate of the MOS tube, the inverting input end of the operational amplifier is connected to the source of the MOS tube, and the drain of the MOS tube is configured to be connected to the LED array; the control unit can quantize the voltage signal into a digital signal, and generate a corresponding output signal based on the digital signal, so as to adjust the current of the LED array through the operational amplifier and the MOS tube, so as to achieve a constant power of the LED array.

2. The control circuit according to claim 1, characterized in that: The control unit comprises: A sampling module, connected to the LED array, for obtaining a voltage value representing an input voltage of the LED array; An ADC module, connected to the output end of the sampling module, capable of converting the voltage value into a corresponding digital signal and outputting the digital signal; an algorithm module, connected to the output end of the ADC module, capable of storing and outputting the maximum value of the digital signal within a preset period; and The mapping module is connected to the output end of the algorithm module and can generate a corresponding current control codeword based on the maximum value of the digital signal to output to the operational amplifier.

3. The control circuit according to claim 2, characterized in that: The sampling module includes: a first resistor R1, a first MOS transistor M1, a second MOS transistor M2, a third MOS transistor M3, a fourth MOS transistor M4 and a second resistor R2. The first end of the first resistor R1 is configured to collect a voltage VIN_RECT representing the input voltage of the LED array. The second end of the first resistor R1 is connected to a first end of a first current mirror formed by the first MOS transistor M1 and the second MOS transistor M2. The second end of the first current mirror is connected to a first end of a second current mirror formed by the third MOS transistor M3 and the fourth MOS transistor M4. The second end of the second current mirror is connected to a first end of the second resistor R2. The second end of the second resistor R2 is connected to a common ground. The first end of the second resistor R2 forms the output end of the sampling module.

4. The control circuit according to claim 2 or 3, characterized in that: The ADC module comprises: a sampling circuit, whose input end is configured to receive the voltage output by the sampling module and sample it into a fixed voltage; a comparison circuit, wherein the non-inverting input terminal thereof is configured to receive the fixed voltage, and the inverting input terminal thereof is configured to be connected to a preset voltage; and A logic circuit has an input terminal connected to an output terminal of the comparison circuit, and an output terminal capable of controlling the preset voltage to change based on a preset logic for comparison with the fixed voltage.

5. The control circuit according to claim 2 or 3, characterized in that: The mapping module includes: a mapping circuit, a fifth MOS tube M5, a sixth MOS tube M6 and a third resistor R3. The mapping circuit is connected to the output end of the ADC module. It can generate a corresponding driving current control codeword based on a preset quantization result and a corresponding current control codeword relationship in response to a received quantization result. The driving current control codeword is input to a first end of a third current mirror composed of the fifth MOS tube M5 and the sixth MOS tube M6. The first end of the third resistor R3 is connected to the second end of the third current mirror to form the output end of the mapping module, and the second end of the third resistor R3 is connected to a common ground.

6. An LED driving circuit, characterized in that: It comprises a rectifier circuit, an LED array, a resistor and a control circuit as described in any one of claims 1 to 5, wherein the rectifier circuit is used to rectify an AC input voltage, an output end of the rectifier circuit is connected to a first end of the LED array, a second end of the LED array is connected to a first end of the control circuit, a second end of the control circuit is connected to a first end of the resistor, and a second end of the resistor is connected to a common ground.

7. A lighting device, characterized in that: Apply the LED driving circuit described in claim 6.

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