Semiconductor packaging plate, semiconductor packaging unit and packaging mold

Abstract

According to the semiconductor packaging plate, the semiconductor packaging unit and the packaging mold provided by the utility model, cavity division electromagnetic shielding (CPS) can be realized through the first conductive structure, and conformal electromagnetic shielding (CFS) can be realized through the conductive layer, so that electromagnetic interference between devices in the packaging structure can be remarkably reduced, and the performance and the reliability of the packaging structure are improved.

Description

Technical Field

[0001] The utility model relates to the technical field of semiconductors, and in particular to a semiconductor packaging board, a semiconductor packaging unit and a packaging mold. Background Art

[0002] With the development of the market, the requirements for electronic products are increasing day by day, and chip packaging technology is gradually tending towards system-level packaging (System In Package, SIP), and further developed a double-sided SIP process to further improve product performance. In the system-level packaging structure, the spacing between chips and passive components is getting smaller and smaller, resulting in more prominent electromagnetic interference (Electro Magnetic Interference, EMI) problems between devices. How to reduce the electromagnetic interference between devices in the packaging structure and improve the performance and reliability of the packaging structure has become a major problem that technicians in this field need to solve. Utility Model Content

[0003] The utility model aims to provide a semiconductor packaging board, a semiconductor packaging unit and a packaging mold to solve the problem of serious electromagnetic interference between devices in the packaging structure in the prior art.

[0004] In order to solve the above technical problems, the utility model provides a semiconductor package board, the semiconductor package board comprising:

[0005] A substrate having a first surface and a second surface opposite to each other, the substrate comprising a plurality of device regions, and a plurality of pads formed on the second surface;

[0006] a plurality of first devices located on the first surface, with at least two first devices being arranged on each device area;

[0007] a plurality of second devices located on the second surface, with at least one second device being disposed on each of the device regions;

[0008] a first plastic encapsulation layer covering the first device and the first surface, wherein the first plastic encapsulation layer has a plurality of first openings penetrating therethrough, wherein the first opening is disposed between two adjacent first devices in the same device region, and wherein the first opening is filled with a first conductive structure;

[0009] a second plastic encapsulation layer covering the second device and the second surface, the second plastic encapsulation layer having a plurality of second openings penetrating therethrough, the second openings exposing the pads, and the second openings being filled with a second conductive structure;

[0010] a conductive layer covering the first plastic packaging layer and connected to the first conductive structure; and

[0011] A solder ball connected to the second conductive structure.

[0012] Optionally, in the semiconductor package board, the first plastic encapsulation layer further has at least one penetrating third opening, the third opening extends into the substrate, and the third opening is arranged between two adjacent device areas.

[0013] Optionally, in the semiconductor package board, the conductive layer extends to cover the inner wall of the third opening and the side surface of the substrate.

[0014] Optionally, in the semiconductor package board, the first conductive structure is solder paste, and the second conductive structure is solder paste, silver paste or copper paste.

[0015] Optionally, in the semiconductor package board, each of the first openings includes a plurality of first sub-openings, and the plurality of first sub-openings are arranged at intervals and in a ring shape; or, each of the first openings includes a plurality of first sub-openings, and the plurality of first sub-openings are arranged in a semi-enclosed shape.

[0016] Optionally, in the semiconductor package board, the conductive layer covers the first conductive structure; or, the first conductive structure covers the conductive layer.

[0017] The present invention also provides a semiconductor packaging unit, the semiconductor packaging unit comprising:

[0018] A substrate having a first surface and a second surface opposite to each other, wherein a welding pad is formed on the second surface;

[0019] a plurality of first devices located on the first surface;

[0020] a second device located on the second surface;

[0021] a first plastic encapsulation layer covering the first device and the first surface, wherein the first plastic encapsulation layer has a first opening penetrating therethrough, wherein the first opening is disposed between two adjacent first devices, and wherein the first opening is filled with a first conductive structure;

[0022] a second plastic encapsulation layer covering the second device and the second surface, the second plastic encapsulation layer having a second opening penetrating therein, the second opening exposing the pad, and the second opening being filled with a second conductive structure;

[0023] a conductive layer covering the first plastic packaging layer and connected to the first conductive structure; and

[0024] A solder ball connected to the second conductive structure.

[0025] Optionally, in the semiconductor packaging unit, the plurality of first devices include chips and passive components.

[0026] The present invention also provides a packaging mold, the packaging mold comprising:

[0027] Base plate;

[0028] a side plate disposed on the bottom plate, the side plate being arranged in a ring shape and forming a containing space; and,

[0029] A wall structure disposed on the bottom plate, wherein the wall structure is located in the accommodating space;

[0030] Wherein, the height difference between the wall structure and the side panels is within 10% of the height of the wall structure.

[0031] Optionally, in the packaging mold, the wall structure includes a plurality of sub-walls, which are arranged at intervals and in a ring shape; or, the wall structure includes a plurality of sub-walls, which are arranged in a semi-enclosed shape.

[0032] In the semiconductor packaging board, semiconductor packaging unit and packaging mold provided by the utility model, cavity electromagnetic shielding (CPS) can be achieved through the first conductive structure, and conformal electromagnetic shielding (CFS) can be achieved through the conductive layer, thereby significantly reducing electromagnetic interference between devices in the packaging structure and improving the performance and reliability of the packaging structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] Figures 1 to 8 It is a schematic diagram of the process of forming a semiconductor packaging unit according to the first embodiment of the present utility model.

[0034] Fig. 9 It is a top view schematic diagram of the first opening of the first embodiment of the utility model.

[0035] Figures 10 to 16 It is a schematic diagram of the process of forming a semiconductor packaging unit according to the second embodiment of the present utility model.

[0036] Fig.17 and Fig.18 It is a three-dimensional schematic diagram and a top view schematic diagram of a packaging mold of the third embodiment of the utility model.

[0037] Fig.19 and Fig. 20 It is a three-dimensional schematic diagram and a top view schematic diagram of another packaging mold of the third embodiment of the utility model.

[0038] Fig.21 and Fig. 22It is a three-dimensional schematic diagram and a top view schematic diagram of another packaging mold of the third embodiment of the utility model.

[0039] The reference numerals are described as follows:

[0040] 100-substrate; 101-first surface; 102-second surface; 103-device area; 104-solder pad; 110-first device; 120-first plastic layer; 121-first opening; 1210-first sub-opening; 130-second device; 140-second plastic layer; 141-second opening; 150-first conductive structure; 160-second conductive structure; 170-solder ball; 180-conductive layer.

[0041] 200-substrate; 201-first surface; 202-second surface; 203-device area; 204-solder pad; 210-first device; 220-first plastic layer; 221-first opening; 222-third opening; 230-second device; 240-second plastic layer; 241-second opening; 250-first conductive structure; 260-second conductive structure; 270-solder ball; 280-conductive layer.

[0042] 300 - packaging mold; 310 - bottom plate; 320 - side plate; 330 - accommodating space; 340 - wall structure; 341 - sub-wall. DETAILED DESCRIPTION

[0043] The semiconductor packaging board, semiconductor packaging unit and packaging mold proposed by the present invention are further described in detail below in combination with the accompanying drawings and specific embodiments. According to the following description, the advantages and features of the present invention will become clearer. It should be noted that the accompanying drawings are all in a very simplified form and are not in precise proportions, and are only used to conveniently and clearly assist in explaining the purpose of the embodiments of the present invention.

[0044] The terms used in the present invention are only for the purpose of describing specific embodiments and are not intended to limit the present invention. Unless otherwise defined in the present application document, the technical terms or scientific terms used in the present invention should be the common meanings understood by people with ordinary skills in the field to which the present invention belongs. The words "first", "second" and similar words used in the present invention specification and claims do not indicate any order, quantity or importance, but are only used to distinguish different components. Similarly, words such as "one" or "one" do not indicate a quantity limit, but indicate the existence of at least one. "Multiple" or "several" means two or more. Unless otherwise specified, words such as "upper / upper layer" and / or "lower / lower layer" are only for the convenience of explanation and are not limited to one position or one spatial orientation. Words such as "include" or "comprise" mean that the elements or structures appearing in front of "include" or "comprise" include the elements or structures listed after "include" or "comprise" and their equivalents, and do not exclude other elements or structures. Words such as "connect" or "connected" are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. The singular forms "a", "said" and "the" used in the present utility model specification and the appended claims are also intended to include plural forms, unless the context clearly indicates otherwise. It should also be understood that the term "and / or" used herein refers to and includes any or all possible combinations of one or more associated listed items.

[0045] [Example 1]

[0046] Please refer to Figures 1 to 8 , which is a schematic diagram of the process of forming a semiconductor packaging unit according to the first embodiment of the present utility model.

[0047] like Figure 1 As shown, a substrate 100 is provided, and the substrate 100 may be a circuit board such as a PCB board. The substrate 100 has a first surface 101 and a second surface 102 opposite to each other, and the first surface 101 and the second surface 102 are respectively an upper surface and a lower surface.

[0048] Furthermore, the substrate 100 includes a plurality of device regions 103 to form a plurality of semiconductor package units accordingly. Figure 1 As shown, three device regions 103 are schematically shown to form three semiconductor package units accordingly.

[0049] A plurality of pads 104 are formed on the second surface 102. Specifically, at least one pad 104 is formed on each device region 103. Figure 1 As shown, here, two bonding pads 104 are formed on each device region 103 .

[0050] Please continue to refer to Figure 1 In the embodiment of the present application, a plurality of first devices 110 are then mounted on the first surface 101, wherein at least two first devices 110 are disposed on each device area 103. The first devices 110 include chips, passive components, etc. Figure 1 As shown, here, three first devices 110 are disposed on each of the device regions 103 , wherein one of the first devices 110 is a chip, and the other two of the first devices 110 are passive components.

[0051] Furthermore, after mounting the first device 110 , reflow, cleaning, etc. may be performed to improve the connection quality and reliability of the first device 110 .

[0052] like Figure 2 As shown, then, a first molding process is performed to form a first molding layer 120 covering the first device 110 and the first surface 101. The material of the first molding layer 120 can be, for example, epoxy molding compound (EMC). Further, a grinding process is performed on the first molding layer 120 to thin the first molding layer 120, reduce the size of the formed semiconductor packaging unit, and at the same time, flatten the surface of the first molding layer 120, improve the film quality of the first molding layer 120, and also reduce the difficulty of subsequent processes.

[0053] like Figure 3 As shown, then, a plurality of second devices 130 are mounted on the second surface 102, wherein at least one second device 130 is disposed on each of the device regions 103. Figure 3 Here, a second device 130 is disposed on each of the device areas 103 , wherein the second device 130 may be a chip, a passive component, etc., for example, and this application does not limit this.

[0054] Next, please refer to Figure 4 , performing a second molding process to form a second molding layer 140 covering the second device 130 and the second surface 102. The material of the second molding layer 140 may be, for example, epoxy molding compound (EMC).

[0055] Please continue to refer to Figure 4Then, a plurality of first openings 121 are formed in the first plastic encapsulation layer 120, and the first openings 121 penetrate the first plastic encapsulation layer 120. The first openings 121 are provided between two adjacent first devices 110 in the same device area 103. The first openings 121 can be formed by a laser process or by using the encapsulation mold of the third embodiment of the present application. Figure 4 As shown, in each device region 103 , a first opening 121 is provided between the first device 110 located in the middle and the first devices 110 on both sides thereof.

[0056] In a plane perpendicular to the substrate 100 , the first opening 121 is small at the bottom and large at the top, that is, the diameter of the end close to the substrate 100 is smaller, while the diameter of the other end away from the substrate 100 is larger, thereby facilitating the formation of the first opening 121 and the subsequent formation of the first conductive structure in the first opening 121 .

[0057] The first opening 121 may be in a dot shape, a straight line shape, a folded line shape, or an arc shape on a plane parallel to the substrate 100. Fig. 9 , a shape of the first opening 121 on a plane parallel to the substrate 100 is schematically shown here, wherein each of the first openings 121 includes a plurality of first sub-openings 1210, and the plurality of first sub-openings 1210 are arranged in a semi-enclosed shape. Specifically, the plurality of first sub-openings 1210 are connected and form a rectangle with one side open. In other embodiments of the present application, the first opening 121 may also be in other shapes, for example, each of the first openings 121 includes a plurality of first sub-openings, and the plurality of first sub-openings are arranged at intervals and in a ring shape, which can be schematically referred to Fig.17 and Fig.18 The wall structure in the encapsulation mold is shown.

[0058] Then, if Figure 5 As shown, a grinding process is performed on the second plastic encapsulation layer 140 to thin the second plastic encapsulation layer 140 and reduce the size of the formed semiconductor packaging unit. At the same time, the surface of the second plastic encapsulation layer 140 is flattened to improve the film quality of the second plastic encapsulation layer 140 and reduce the difficulty of subsequent processes.

[0059] In the embodiment of the present application, then, a plurality of second openings 141 are formed in the second plastic encapsulation layer 140, and the second openings 141 penetrate the second plastic encapsulation layer 140 and expose the pads 104. Here, the plurality of second openings 141 correspond to the plurality of pads 104 one by one, and one second opening 141 can expose part or all of a corresponding pad 104. The second opening 141 can be formed by a laser process. Here, the diameter of one end of the second opening 141 close to the substrate 100 is smaller, and the diameter of the other end away from the substrate 100 is larger.

[0060] Please refer to Figure 6 , a first conductive structure 150 is formed in the first opening 121, and a second conductive structure 160 is formed in the second opening 141, wherein the second conductive structure 160 is connected to the pad 104. The materials of the first conductive structure 150 and the second conductive structure 160 can both be metals, such as tin, silver or copper, and further, the materials of the two can be the same or different. In an embodiment of the present application, the first conductive structure 150 and the second conductive structure 160 are both formed by printing solder paste, that is, the first conductive structure 150 and the second conductive structure 160 are both solder paste; in other embodiments of the present application, the second conductive structure 160 can also be conductive paste such as silver glue and copper glue.

[0061] like Figure 7 As shown, then, a solder ball 170 connected to the second conductive structure 160 is formed, wherein one second conductive structure 160 is correspondingly connected to one solder ball 170 to lead out the corresponding bonding pad 104 .

[0062] like Figure 8 As shown, then, a conductive layer 180 is formed to cover the first plastic encapsulation layer 120 and connected to the first conductive structure 150. That is, in the embodiment of the present application, the conductive layer 180 covers the first conductive structure 150; in other embodiments of the present application, the conductive layer 180 can also be formed before the first conductive structure 150, that is, the first conductive structure 150 covers the conductive layer 180. Specifically, the second plastic encapsulation layer 140 and the solder ball 170 can be firstly arranged on a tape (not shown in the figure), and then the conductive layer 180 is formed to protect the second plastic encapsulation layer 140 and the solder ball 170.

[0063] Here, conformal electromagnetic shielding can be achieved through the conductive layer 180, and at the same time, cavity electromagnetic shielding can be achieved through the first conductive structure 150, that is, the semiconductor packaging board and semiconductor packaging unit formed thereby can have both conformal electromagnetic shielding and cavity electromagnetic shielding, thereby significantly reducing electromagnetic interference between devices in the packaging structure and improving the performance and reliability of the packaging structure.

[0064] Please continue to refer to Figure 8 In the embodiment of the present application, before forming the conductive layer 180, the substrate 100 is firstly cut according to the device area 103 to form a plurality of monomer structures, and then a conductive layer 180 is formed on each of the monomer structures to cover the first plastic encapsulation layer 120 and connect to the first conductive structure 150, thereby forming a semiconductor package unit. Furthermore, the conductive layer 180 also extends to cover the sidewalls of the monomer structure, including the sidewalls of the first plastic encapsulation layer 120 and the sidewalls of the second plastic encapsulation layer 140, so as to simplify the electrical connection of the semiconductor package unit and improve the quality and reliability of the semiconductor package unit.

[0065] In other embodiments of the present application, the conductive layer 180 may be formed first to obtain a semiconductor package board, and then a cutting process may be performed on the semiconductor package board to form semiconductor package units.

[0066] Correspondingly, this embodiment also provides a semiconductor packaging board and a semiconductor packaging unit.

[0067] Specifically, the semiconductor package board includes: a substrate 100, the substrate 100 has a first surface 101 and a second surface 102 opposite to each other, the substrate 100 includes a plurality of device areas 103, and a plurality of solder pads 104 are formed on the second surface 102; a plurality of first devices 110 located on the first surface 101, and at least two of the first devices 110 are arranged on each of the device areas 103; a plurality of second devices 130 located on the second surface 102, and at least one of the second devices 130 is arranged on each of the device areas 103; a first plastic encapsulation layer 120 covering the first devices 110 and the first surface 101, and the first plastic encapsulation layer 120 has a plurality of solder pads 104; a first through opening 121, the first opening 121 is arranged between two adjacent first devices 110 in the same device area 103, and the first opening 121 is filled with a first conductive structure 150; a second plastic encapsulation layer 140 covering the second device 130 and the second surface 102, the second plastic encapsulation layer 140 has a plurality of through second openings 141, the second openings 141 expose the solder pad 104, and the second openings 141 are filled with a second conductive structure 160; a conductive layer 180 covering the first plastic encapsulation layer 120 and connected to the first conductive structure 150; and a solder ball 170 connected to the second conductive structure 160.

[0068] The semiconductor packaging unit includes: a substrate 100, the substrate 100 has a first surface 101 and a second surface 102 opposite to each other, a solder pad 104 is formed on the second surface 102; a plurality of first devices 110 located on the first surface 101; a second device 130 located on the second surface 102; a first plastic encapsulation layer 120 covering the first devices 110 and the first surface 101, the first plastic encapsulation layer 120 has a first opening 121 penetrating therein, the first opening 121 is arranged between two adjacent first devices 110, and the first opening 121 is filled with a first conductive structure 150; a second plastic encapsulation layer 140 covering the second device 130 and the second surface 102, the second plastic encapsulation layer 140 has a second opening 141 penetrating therein, the second opening 141 exposes the solder pad 104, and the second opening 141 is filled with a second conductive structure 160; a conductive layer 180 covering the first plastic encapsulation layer 120 and connected to the first conductive structure 150; and a solder ball 170 connected to the second conductive structure 160.

[0069] In the embodiment of the present application, the first conductive structure 150 is solder paste, and the second conductive structure 160 is solder paste, silver glue or copper glue. The first device 110 includes a chip and / or a passive component; the second device 130 includes a chip and / or a passive component.

[0070] like Fig. 9 As shown, each of the first openings 121 includes a plurality of first sub-openings 1210, and the plurality of first sub-openings 1210 are arranged at intervals and in a ring shape; or, each of the first openings 121 includes a plurality of first sub-openings 1210, and the plurality of first sub-openings 1210 are arranged in a semi-enclosed shape. One of the first devices 110 is located in the accommodation space of the first opening 121 in a ring shape or a semi-enclosed shape, and one or more of the first devices 110 are located outside the accommodation space of the first opening 121 in a ring shape or a semi-enclosed shape. The first conductive structure 150 formed in the first opening 121 can well realize electromagnetic shielding for the first device 110 inside and outside the accommodation space, thereby significantly reducing electromagnetic interference between devices in the packaging structure and improving the performance and reliability of the packaging structure.

[0071] [Example 2]

[0072] Please refer to Figures 10 to 16 , which is a schematic diagram of the process of forming a semiconductor packaging unit in the second embodiment of the present utility model.

[0073] like Fig.10 As shown, a substrate 200 is provided, and the substrate 200 can be, for example, a circuit board such as a PCB board. The substrate 200 has a first surface 201 and a second surface 202 opposite to each other, wherein the first surface 201 and the second surface 202 are respectively an upper surface and a lower surface, and the substrate 200 includes a plurality of device areas 203, and a plurality of pads 204 are formed on the second surface 202. In the embodiment of the present application, then, a plurality of first devices 210 are mounted on the first surface 201, wherein at least two first devices 210 are arranged on each of the device areas 203.

[0074] Then, if Fig.11 As shown, a first molding process is performed to form a first molding layer 220 covering the first device 210 and the first surface 201. The material of the first molding layer 220 can be, for example, epoxy molding compound (EMC). Further, a grinding process is performed on the first molding layer 220 to thin the first molding layer 220.

[0075] like Fig.12 As shown, then, a plurality of second devices 230 are mounted on the second surface 202, wherein at least one second device 230 is disposed on each of the device regions 203. Fig.12Then, a second molding process is performed to form a second molding layer 240 covering the second device 230 and the second surface 202. The material of the second molding layer 240 can be, for example, epoxy molding compound (EMC). Further, a grinding process is performed on the second molding layer 240 to thin the second molding layer 240.

[0076] like Fig.13 As shown, in the embodiment of the present application, then, a plurality of second openings 241 are formed in the second plastic encapsulation layer 240, and the second openings 241 penetrate the second plastic encapsulation layer 240 and expose the solder pad 204. Further, a second conductive structure 260 is formed in the second opening 241, wherein the second conductive structure 260 is connected to the solder pad 204. A solder ball 270 connected to the second conductive structure 260 is formed.

[0077] Next, please refer to Fig.14 , a plurality of first openings 221 are formed in the first plastic encapsulation layer 220, and the first openings 221 penetrate the first plastic encapsulation layer 220. The first openings 221 are provided between two adjacent first devices 210 in the same device area 203. The first openings 221 can be formed by a laser process, or by using the encapsulation mold of the third embodiment of the present application.

[0078] In the embodiment of the present application, at least one third opening 222 is formed in the first plastic encapsulation layer 220, and the third opening 222 extends into the substrate 200, and the third opening 222 is provided between two adjacent device areas 203. The third opening 222 can facilitate the subsequent cutting of the semiconductor package board to form a semiconductor package unit.

[0079] Please continue to refer to Fig.14 In the embodiment of the present application, a conductive layer 280 is then formed, and the conductive layer 280 covers the first plastic encapsulation layer 220, and also extends to cover the inner wall of the first opening 221 and the inner wall of the third opening 222. Further, the conductive layer 280 also extends to cover the side wall of the substrate 200, and here, also covers the side wall of the first plastic encapsulation layer 220 and the side wall of the second plastic encapsulation layer 240. The conductive layer 280 can be formed, for example, by a sputtering process.

[0080] Please refer to Fig.15 , a first conductive structure 250 is formed in the first opening 221 , wherein the first conductive structure 250 may be, for example, solder paste.

[0081] Thus, a semiconductor package board can be formed, and the semiconductor package board includes: a substrate 200, the substrate 200 has a first surface 201 and a second surface 202 opposite to each other, the substrate 200 includes a plurality of device areas 203, and a plurality of pads 204 are formed on the second surface 202; a plurality of first devices 210 located on the first surface 201, and at least two of the first devices 210 are arranged on each of the device areas 203; a plurality of second devices 230 located on the second surface 202, and at least one of the second devices 230 is arranged on each of the device areas 203; a first plastic sealing layer 220 covering the first devices 210 and the first surface 201, and the first plastic sealing layer 220 has a plurality of penetrating first openings 221 and at least one penetrating third opening 222, A first opening 221 is arranged between two adjacent first devices 210 in the same device area 203, the first opening 221 is filled with a first conductive structure 250, the third opening 222 extends into the substrate 200, and the third opening 222 is arranged between two adjacent device areas 203; a second plastic encapsulation layer 240 covering the second device 230 and the second surface 202, the second plastic encapsulation layer 240 having a plurality of penetrating second openings 241, the second openings 241 exposing the solder pad 204, the second openings 241 being filled with a second conductive structure 260; a conductive layer 280 covering the first plastic encapsulation layer 220 and connected to the first conductive structure 250; and a solder ball 270 connected to the second conductive structure 260.

[0082] The conductive layer 280 also extends to cover the inner wall of the third opening 222 and the side surface of the substrate 200 to simplify the electrical connection of the formed semiconductor package board and the semiconductor package unit, while improving the quality and reliability of the semiconductor package board and the semiconductor package unit.

[0083] Here, conformal electromagnetic shielding can be achieved through the conductive layer 280, and at the same time, cavity electromagnetic shielding can be achieved through the first conductive structure 250, that is, the semiconductor packaging board and semiconductor packaging unit formed thereby can have both conformal electromagnetic shielding and cavity electromagnetic shielding, thereby significantly reducing electromagnetic interference between devices in the packaging structure and improving the performance and reliability of the packaging structure.

[0084] Next, please refer to Fig.16 , the substrate 100 and the first plastic encapsulation layer 220 and the second plastic encapsulation layer 240 are cut along the third opening 222 to form a semiconductor packaging unit.

[0085] The semiconductor packaging unit includes: a substrate 200, wherein the substrate 200 has a first surface 201 and a second surface 202 relative to each other, and a solder pad 204 is formed on the second surface 202; a plurality of first devices 210 located on the first surface 201; a second device 230 located on the second surface 202; a first plastic encapsulation layer 220 covering the first devices 210 and the first surface 201, wherein the first plastic encapsulation layer 220 has a first opening 221 extending therethrough, and the first opening 221 is arranged between two adjacent first devices 210, and the first opening 221 is filled with a first conductive structure 250; a second plastic encapsulation layer 240 covering the second device 230 and the second surface 202, wherein the second plastic encapsulation layer 240 has a second opening 241 extending therethrough, and the second opening 241 exposes the solder pad 204, and the second opening 241 is filled with a second conductive structure 260; a conductive layer 280 covering the first plastic encapsulation layer 220 and connected to the first conductive structure 250; and a solder ball 270 connected to the second conductive structure 260.

[0086] like Fig.16 As shown, the conductive layer 280 extends to cover the sidewall of the first plastic encapsulation layer 220 and also extends to cover at least a portion of the sidewall of the substrate 200. In the embodiment of the present application, the conductive layer 280 exposes a portion of the sidewall of at least one side of the substrate 200.

[0087] [Example 3]

[0088] This embodiment provides a packaging mold that can be used to manufacture the semiconductor packaging board and the semiconductor packaging unit. Figures 17 to 22 As shown, the packaging mold 300 includes: a bottom plate 310; a side plate 320 arranged on the bottom plate 310, the side plate 320 is arranged in a ring shape and forms a accommodating space 330; and a wall structure 340 arranged on the bottom plate 310, the wall structure 340 is located in the accommodating space 330; wherein the height difference between the wall structure 340 and the side plate 320 is within 10% of the height of the wall structure 340.

[0089] The wall structure 340 may be in a dotted, straight, folded or arc shape in a plane parallel to the bottom plate 310. Preferably, the wall structure 340 includes a plurality of sub-walls, which are arranged in a ring shape at intervals; or, the wall structure 340 includes a plurality of sub-walls, which are arranged in a semi-enclosed shape.

[0090] like Fig.17 and Fig.18As shown, in one embodiment of the present application, the wall structure 340 includes a plurality of sub-walls 341, and the plurality of sub-walls 341 are arranged at intervals and in a ring shape. Here, it is schematically shown that each of the wall structures 340 includes twelve sub-walls 341, and the twelve sub-walls 341 are arranged at intervals in a square ring shape. Further, the plurality of wall structures 340 are arranged in an array on the base plate 310, and here, they are arranged in four rows and six columns, that is, twenty-four wall structures 340 are schematically shown here. Among them, each of the sub-walls 341 is in a dot shape in a plane parallel to the base plate 310.

[0091] like Fig.19 and Fig. 20 As shown, in another embodiment of the present application, the wall structure 340 includes a plurality of sub-walls 341, and the plurality of sub-walls 341 are arranged in a semi-enclosed shape. Here, each of the wall structures 340 includes three (in a plane parallel to the bottom plate 310) linear sub-walls 341, and the three sub-walls 341 are connected in sequence to form a square with an opening.

[0092] like Fig.21 and Fig. 22 As shown, in another embodiment of the present application, the wall structure 340 includes a plurality of sub-walls 341, and the plurality of sub-walls 341 are also arranged in a semi-enclosed shape. Fig.19 and Fig. 20 The difference of the wall structure 340 shown is that three linear sub-walls 341 are spaced apart from each other, that is, there is a gap between two adjacent sub-walls 341 .

[0093] In other embodiments of the present application, the wall structure 340 may have other shapes, which are not limited in the present application. Preferably, the wall structure 340 has an opening, which may be as follows: Fig.17 and Fig.18 As shown, the opening is formed by the interval between the sub-walls 341, or it can be as follows Fig.19 and Fig. 20 The opening is formed by arranging in a semi-enclosed shape, and the quality and reliability of the plastic sealing layer can be ensured during the process of forming the first opening.

[0094] Preferably, the dimension of one end of the wall structure 340 close to the base plate 310 is larger than the dimension of the other end away from the base plate 310, thereby facilitating demoulding of the encapsulation mold 300 after the first opening is formed by the encapsulation mold 300, thereby simplifying the process difficulty.

[0095] Please refer to Example 1 and Example 2. In one embodiment of the present application, after mounting the first device on the first surface of the substrate, the encapsulation mold can be set on the first surface of the substrate, wherein the free end of the wall structure 340 is close to the first surface of the substrate. Then, a molding compound is filled between the substrate and the bottom plate 310 to form a first molding layer. In this implementation, the first opening is formed while the first molding layer is formed. After the first molding layer is stable, the encapsulation mold 300 can be removed.

[0096] In another embodiment of the present application, after the first plastic encapsulation layer is formed and the first plastic encapsulation layer has not yet been completely solidified, the encapsulation mold 300 may be inserted into the first plastic encapsulation layer from the free end of the wall structure 340 to form the first opening. After the first plastic encapsulation layer is stable, the encapsulation mold 300 may be removed.

[0097] The packaging mold can be used to conveniently and quickly form the first opening in the first plastic packaging layer, thereby simplifying the process difficulty and reducing the manufacturing cost.

[0098] In the present application, references to "one embodiment" or "some embodiments" mean that features, structures, or characteristics described in conjunction with the embodiment are included in at least one embodiment, at least some embodiments, of the present application. Therefore, the appearance of the phrases "in one embodiment" or "in some embodiments" in various places of the present application does not necessarily refer to the same or the same embodiments. In addition, in one or more embodiments, features, structures, or characteristics may be combined in any suitable combination and / or sub-combination.

[0099] Although some specific embodiments of the present application have been described in detail by way of example, it will be appreciated by those skilled in the art that the above examples are for illustration only and are not intended to limit the scope of the present application. The various embodiments of the present application may be combined in any manner without departing from the spirit and scope of the present application. It will also be appreciated by those skilled in the art that various modifications may be made to the embodiments without departing from the scope and spirit of the present application. The scope of the present application is defined by the appended claims.

Claims

1. A semiconductor package board, characterized in that: The semiconductor package board comprises: A substrate having a first surface and a second surface opposite to each other, the substrate comprising a plurality of device regions, and a plurality of pads formed on the second surface; a plurality of first devices located on the first surface, with at least two first devices being arranged on each device area; a plurality of second devices located on the second surface, with at least one second device being disposed on each of the device regions; a first plastic encapsulation layer covering the first device and the first surface, wherein the first plastic encapsulation layer has a plurality of first openings penetrating therethrough, wherein the first opening is disposed between two adjacent first devices in the same device region, and wherein the first opening is filled with a first conductive structure; a second plastic encapsulation layer covering the second device and the second surface, the second plastic encapsulation layer having a plurality of second openings penetrating therethrough, the second openings exposing the pads, and the second openings being filled with a second conductive structure; a conductive layer covering the first plastic packaging layer and connected to the first conductive structure; and A solder ball connected to the second conductive structure.

2. The semiconductor package board according to claim 1, wherein: The first plastic encapsulation layer also has at least one third opening extending therethrough. The third opening extends into the substrate, and the third opening is disposed between two adjacent device regions.

3. The semiconductor package board according to claim 2, wherein: The conductive layer extends to cover the inner wall of the third opening and the side surface of the substrate.

4. The semiconductor package board according to any one of claims 1 to 3, wherein: The first conductive structure is solder paste, and the second conductive structure is solder paste, silver glue or copper glue.

5. The semiconductor package board according to any one of claims 1 to 3, wherein: Each of the first openings includes a plurality of first sub-openings, and the plurality of first sub-openings are arranged at intervals and in a ring shape; or each of the first openings includes a plurality of first sub-openings, and the plurality of first sub-openings are arranged in a semi-enclosed shape.

6. The semiconductor package board according to claim 1, wherein: The conductive layer covers the first conductive structure; or the first conductive structure covers the conductive layer.

7. A semiconductor packaging unit, characterized in that: The semiconductor packaging unit comprises: A substrate having a first surface and a second surface opposite to each other, wherein a welding pad is formed on the second surface; a plurality of first devices located on the first surface; a second device located on the second surface; a first plastic encapsulation layer covering the first device and the first surface, wherein the first plastic encapsulation layer has a first opening penetrating therethrough, wherein the first opening is disposed between two adjacent first devices, and wherein the first opening is filled with a first conductive structure; a second plastic encapsulation layer covering the second device and the second surface, the second plastic encapsulation layer having a second opening penetrating therein, the second opening exposing the pad, and the second opening being filled with a second conductive structure; a conductive layer covering the first plastic packaging layer and connected to the first conductive structure; and A solder ball connected to the second conductive structure.

8. The semiconductor package unit according to claim 7, wherein: The plurality of first devices include chips and passive components.

9. A packaging mold for manufacturing a semiconductor packaging board as claimed in any one of claims 1 to 6 or a semiconductor packaging unit as claimed in claim 7 or 8, characterized in that: The packaging mold comprises: Base plate; a side plate disposed on the bottom plate, the side plate being arranged in a ring shape and forming a containing space; and, A wall structure disposed on the bottom plate, wherein the wall structure is located in the accommodating space; Wherein, the height difference between the wall structure and the side panels is within 10% of the height of the wall structure.

10. The packaging mold according to claim 9, characterized in that: The wall structure includes a plurality of sub-walls, which are arranged at intervals and in a ring shape; or, the wall structure includes a plurality of sub-walls, which are arranged in a semi-enclosed shape.

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