Trench gate transistor
By setting up a spaced electric field shielding structure in the trench gate transistor, the problem of insulation performance degradation of the gate dielectric layer under high electric fields is solved, and the effect of reducing saturation current and optimizing short circuit performance is achieved.
Patent Information
- Application Number
- CN202421571799.5
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-07-04
- Publication Date
- 2025-04-18
- Estimated Expiration
- 2034-07-04
AI Technical Summary
In the blocked state of the trench gate transistor, the gate dielectric layer is susceptible to high electric fields, resulting in degradation of insulation performance and early breakdown, reducing the long-term operating stability and life of the device.
By providing a first electric field shielding structure and a second electric field shielding structure outside the gate trench, respectively, an electric field shielding structure arranged spaced apart is formed to reduce the electric field distribution of the gate dielectric layer.
It effectively reduces the saturation current of the device, optimizes the short-circuit performance, and enhances the protection effect of the gate dielectric layer, taking into account the specific on-resistance Rsp and the protection effect and short-circuit performance.
Smart Images
Figure CN222776518U_ABST
Abstract
Description
Technical Field
[0001] The present application relates to the field of semiconductor technology, and in particular to a trench gate transistor. Background Art
[0002] Compared with planar gate transistors, trench gate transistors can greatly reduce the cell size, thereby greatly improving the current density. For example, compared with planar gate MOSFET, the performance of trench gate metal-oxide-semiconductor field-effect transistor (MOSFET) has been greatly improved, not only can it obtain higher channel mobility, but also has a higher on-resistance R sp Reduced, the on-state current density and conduction performance of the device are improved.
[0003] However, trench gate transistors face the problem of gate dielectric layer reliability. This is because when the device is in the blocking state, the bottom of the gate trench is exposed to the high electric field region in the drift region, so that the portion of the gate dielectric layer located at the bottom of the gate trench is subjected to a high-intensity electric field, which is prone to insulation degradation or even premature breakdown, reducing the stability and life of the device during long-term operation. Especially for trench gate transistors based on silicon carbide (SiC), since the critical breakdown electric field strength of silicon carbide is much greater than that of silicon, the gate dielectric layer will be subjected to a higher electric field, making it more likely to experience insulation degradation or even premature breakdown.
[0004] In order to protect the gate dielectric layer, an electric field shielding structure is introduced into the trench gate transistor. One way is to inject multiple P pillar structures at intervals in the direction intersecting the gate trench to reduce the electric field distribution in the gate dielectric layer at the bottom of the gate trench. However, the protection effect of this method needs to be improved, and the saturation current of the device is large and the short-circuit performance is poor. Utility Model Content
[0005] In view of this, an embodiment of the present application provides a trench gate transistor to solve at least one problem existing in the background technology.
[0006] In a first aspect, an embodiment of the present application provides a trench gate transistor, comprising:
[0007] a semiconductor material layer;
[0008] A gate trench extending from the upper surface of the semiconductor material layer to the inside, the gate trench comprising a side wall and a bottom wall, the side wall comprising at least two first portions spaced apart along an extension direction and a second portion located between two adjacent first portions, the extension direction referring to an extension direction of the side wall on the plane where the upper surface of the semiconductor material layer is located;
[0009] A first electric field shielding structure, located outside the gate trench and adjacent to the first portion;
[0010] a body region, located outside the gate trench and adjacent to the second portion, wherein a portion of the body region close to the gate trench is used to form a channel region;
[0011] A drift region, located below the channel region;
[0012] The second electric field shielding structure is located below the first electric field shielding structure and at least partially extends below the channel region, so that along the extension direction, the width of the drift region between two adjacent second electric field shielding structures is smaller than the width of the channel region.
[0013] In combination with the first aspect of the present application, in an optional implementation, the bottom of the first electric field shielding structure is further away from the upper surface of the semiconductor material layer than the bottom of the body region, so that there is a gap between the second electric field shielding structure and the body region.
[0014] In combination with the first aspect of the present application, in an optional implementation, along the extension direction, a width of a portion of the drift region located between two adjacent second electric field shielding structures is smaller than a width of a portion of the drift region located between two adjacent first electric field shielding structures.
[0015] In combination with the first aspect of the present application, in an optional implementation manner, the second electric field shielding structure is spaced 0.25 μm to 1.2 μm from the body region.
[0016] In combination with the first aspect of the present application, in an optional implementation manner, the ion doping concentration of the second electric field shielding structure is greater than the ion doping concentration of the first electric field shielding structure.
[0017] In combination with the first aspect of the present application, in an optional implementation, the ion doping concentration of the body region is less than the ion doping concentration of the first electric field shielding structure and less than the ion doping concentration of the second electric field shielding structure.
[0018] In combination with the first aspect of the present application, in an optional implementation, the width of a portion of the drift region located between two adjacent second electric field shielding structures increases from a direction close to the gate trench to a direction away from the gate trench.
[0019] In combination with the first aspect of the present application, in an optional implementation manner, the second electric field shielding structure is adjacent to the bottom of the first electric field shielding structure.
[0020] In combination with the first aspect of the present application, in an optional implementation manner, the second electric field shielding structure and the first electric field shielding structure are both connected to a ground potential.
[0021] In combination with the first aspect of the present application, in an optional implementation, the first electric field shielding structure surrounds both sides and a bottom wall of the gate trench.
[0022] In combination with the first aspect of the present application, in an optional embodiment, it also includes: a third electric field shielding structure, which is located below the gate trench and has an overlapping area with the first electric field shielding structure and / or the second electric field shielding structure, and the third electric field shielding structure is conductively connected to the first electric field shielding structure and / or the second electric field shielding structure through the overlapping area.
[0023] In combination with the first aspect of the present application, in an optional implementation, it further includes: a current diffusion layer, located in the JFET region below the body region, the ion doping concentration of the current diffusion layer is greater than the ion doping concentration of the drift region.
[0024] In conjunction with the first aspect of the present application, in an optional implementation manner, the method further includes:
[0025] a gate dielectric layer, in the gate trench, covering the sidewalls and bottom wall of the gate trench;
[0026] A gate, located in the gate dielectric layer;
[0027] An interlayer dielectric layer, located in the gate trench and above the gate;
[0028] A conductive layer is located on the semiconductor material layer, and the conductive layer is insulated and isolated from the gate by the interlayer dielectric layer.
[0029] The trench gate transistor provided in the embodiment of the present application comprises: a semiconductor material layer; a gate trench extending from the upper surface to the inside of the semiconductor material layer, the gate trench comprising a side wall and a bottom wall, the side wall comprising at least two first parts arranged at intervals along an extension direction and a second part located between the two adjacent first parts, the extension direction refers to the extension direction of the side wall on the plane where the upper surface of the semiconductor material layer is located; a first electric field shielding structure located outside the gate trench and adjacent to the first part; a body region located outside the gate trench and adjacent to the second part, a portion of the body region close to the gate trench is used to form a channel region; a drift region located below the channel region; a second electric field shielding structure located below the first electric field shielding structure and at least partially The structure of the drift region is extended to the bottom of the channel region, so that along the extension direction, the width of the portion of the drift region located between the two adjacent second electric field shielding structures is smaller than the width of the channel region; in this way, the spacing between the two adjacent first electric field shielding structures and the spacing between the two adjacent second electric field shielding structures can be set respectively, so that while ensuring the width of the channel region, the width of the portion of the drift region located between the two adjacent second electric field shielding structures can be set smaller, so that the JFET resistance in the interval where the portion is located can be adjusted without affecting the channel resistance, greatly reducing the saturation current of the device, and optimizing the short-circuit performance of the device; and the second electric field shielding structure enhances the protection effect of the gate dielectric layer at the bottom of the gate trench, thereby taking into account the specific on-resistance R sp With protection effect and short circuit performance.
[0030] Additional aspects and advantages of the present application will be given in part in the description below, and in part will become apparent from the description below, or will be learned through the practice of the present application. BRIEF DESCRIPTION OF THE DRAWINGS
[0031] The drawings described herein are used to provide a further understanding of the present application and constitute a part of the present application. The illustrative embodiments of the present application and their descriptions are used to explain the present application and do not constitute an improper limitation on the present application. In the drawings:
[0032] Figure 1 It is a schematic diagram of the three-dimensional structure of a trench gate transistor in the related art;
[0033] Figure 2 For along Figure 1 A schematic diagram of a projection in the second direction;
[0034] Figure 3 A schematic diagram of the three-dimensional structure of a trench gate transistor provided in an embodiment of the present application;
[0035] Figure 4 For along Figure 3 A schematic diagram of a projection in the second direction;
[0036] Figure 5 for Figure 3Structural diagram of the AA section;
[0037] Figure 6 for Figure 3 Structural diagram of the middle BB section;
[0038] Figure 7 For along Figure 3 A schematic diagram of the three-dimensional structure with the CC section cut away;
[0039] Figure 8 is a schematic diagram of a projection of a trench gate transistor along a second direction in an optional implementation manner;
[0040] Fig. 9 This is a schematic diagram of the three-dimensional structure of a trench gate transistor in another optional implementation manner of the present application;
[0041] Fig.10 This is a schematic projection diagram of a trench gate transistor along a second direction in yet another optional implementation manner of the present application;
[0042] Fig.11 This is a schematic projection diagram of a trench gate transistor along the second direction in another optional implementation manner of the present application;
[0043] Fig.12 This is a schematic diagram of the three-dimensional structure of a trench gate transistor in another optional implementation manner of the present application;
[0044] Fig.13 for Fig.12 Structural diagram of the middle BB section;
[0045] Fig.14 This is a schematic diagram of the three-dimensional structure of a trench gate transistor in another optional implementation manner of the present application;
[0046] Fig.15 for Fig.14 Structural diagram of the AA section;
[0047] Fig.16 for Fig.14 Structural diagram of the middle BB section;
[0048] Fig.17 For along Fig.14 A schematic diagram of the three-dimensional structure with the CC section cut away;
[0049] Fig.18 V is obtained by simulating the trench gate transistor provided in the embodiment of the present application and the trench gate transistor in the related art respectively. ds In the range of 0V-500V, I ds -V ds Curve comparison chart;
[0050] Fig.19 V is obtained by simulating the trench gate transistor provided in the embodiment of the present application and the trench gate transistor in the related art respectively. ds In the range of 0V-1V, I ds -V ds Curve comparison chart.
[0051] Description of reference numerals:
[0052] 100, substrate; 110, semiconductor material layer; 111, upper surface; 112, lower surface; 113, drift region; 114, JFET region; 120, gate trench; 121, side wall; 1211, first part; 1212, second part; 122, bottom wall; 130, gate dielectric layer; 140, gate; 150, first electric field shielding structure; 157, P-pillar structure; 160, body region; 161, channel region; 170, second electric field shielding structure; 180, third electric field shielding structure; 190, first electric field shielding structure contact region; 200, source contact region; 210, interlayer dielectric layer; 220, conductive layer; 230, current diffusion layer. DETAILED DESCRIPTION
[0053] The exemplary embodiments disclosed in the present application will be described in more detail below with reference to the accompanying drawings. Although the exemplary embodiments of the present application are shown in the accompanying drawings, it should be understood that the present application can be implemented in various forms and should not be limited by the specific embodiments described herein. On the contrary, these embodiments are provided to enable a more thorough understanding of the present application and to fully convey the scope disclosed in the present application to those skilled in the art.
[0054] In the following description, a large number of specific details are given in order to provide a more thorough understanding of the present application. However, it is obvious to those skilled in the art that the present application can be implemented without one or more of these details. In other examples, in order to avoid confusion with the present application, some technical features well known in the art are not described; that is, all features of the actual embodiments are not described here, and well-known functions and structures are not described in detail.
[0055] In the drawings, the sizes of layers, regions, elements and their relative sizes may be exaggerated for clarity. Like reference numerals denote like elements throughout.
[0056] It should be understood that when an element or layer is referred to as "on ...", "adjacent to ...", "connected to" or "coupled to" other elements or layers, it can be directly on, adjacent to, connected to or coupled to other elements or layers, or there can be intervening elements or layers. On the contrary, when an element is referred to as "directly on ...", "directly adjacent to ...", "directly connected to" or "directly coupled to" other elements or layers, there is no intervening element or layer. It should be understood that although the terms first, second, third, etc. can be used to describe various elements, components, regions, layers and / or parts, these elements, components, regions, layers and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or part from another element, component, region, layer or part. Therefore, without departing from the teachings of the present application, the first element, component, region, layer or part discussed below can be represented as the second element, component, region, layer or part. And when the second element, component, region, layer or part is discussed, it does not indicate that the present application necessarily has the first element, component, region, layer or part.
[0057] Spatially relative terms such as "under", "beneath", "below", "under", "above", "above", etc., may be used here for convenience of description to describe the relationship between an element or feature shown in the figure and other elements or features. It should be understood that in addition to the orientation shown in the figure, the spatial relationship terms are intended to also include different orientations of the device in use and operation. For example, if the device in the accompanying drawings is turned over, then the elements or features described as "under other elements" or "under it" or "under it" will be oriented as "on" other elements or features. Therefore, the exemplary terms "under" and "under" may include both upper and lower orientations. The device can be oriented otherwise (rotated 90 degrees or other orientations) and the spatial descriptors used herein are interpreted accordingly.
[0058] The purpose of the terms used herein is only to describe specific embodiments and is not intended to be limiting of the present application. When used herein, the singular forms "one", "an" and "said / the" are also intended to include plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "consisting of" and / or "comprising", when used in this specification, determine the presence of the features, integers, steps, operations, elements and / or parts, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or groups. When used herein, the term "and / or" includes any and all combinations of the relevant listed items.
[0059] In order to thoroughly understand the present application, detailed steps and detailed structures will be presented in the following description to illustrate the technical solution of the present application. The preferred embodiments of the present application are described in detail below, but in addition to these detailed descriptions, the present application may also have other implementation methods.
[0060] Figure 1 and Figure 2 A trench gate transistor structure in the related art is shown. As shown in the figure, in order to protect the gate dielectric layer 130, a plurality of P-column structures 157 are arranged at intervals in the direction intersecting the gate trench 120. The presence of the P-column structure 157 occupies the position where the channel region should be formed, and the body region 160 is arranged between two adjacent P-column structures 157. The electric field at the bottom of the gate trench 120 is greatly affected by the spacing of the P-column structures 157. If the spacing is set smaller in order to obtain a better protection effect, the channel region is occupied more, which is more than the on-resistance R sp On the contrary, if the spacing is set larger, the protection effect needs to be improved, and the saturation current of the device is large and the short-circuit performance is poor. Therefore, it is often necessary to face the comparison of on-resistance R sp The problem of difficulty in balancing and taking into account protection effect and short-circuit performance.
[0061] Based on this, the present application embodiment provides a trench gate transistor, please refer to Figures 3 to 7 The trench gate transistor comprises: a semiconductor material layer 110; a gate trench 120 extending from an upper surface 111 of the semiconductor material layer 110 to the inside, the gate trench 120 comprising a sidewall 121 and a bottom wall 122, the sidewall 121 comprising at least two first portions 1211 arranged at intervals along the extension direction and a second portion 1212 located between two adjacent first portions 1211; a first electric field shielding structure 150 located outside the gate trench 120 and adjacent to the first portion 1211; a body region 160 located Outside the gate trench 120 and adjacent to the second portion 1212, a portion of the body region 160 close to the gate trench 120 is used to form a channel region 161; the drift region 113 is located below the channel region 161; the second electric field shielding structure 170 is located below the first electric field shielding structure 150 and at least partially extends to below the channel region 161, so that along the extension direction, the width W1 of the portion of the drift region 113 located between two adjacent second electric field shielding structures 170 is smaller than the width W2 of the channel region 161.
[0062] It can be understood that the embodiment of the present application improves the P-column structure in the related art to include a first electric field shielding structure 150 and a second electric field shielding structure 170 located below the first electric field shielding structure 150, so that the spacing between two adjacent first electric field shielding structures 150 and the spacing between two adjacent second electric field shielding structures 170 can be set respectively, that is, the spacing between two adjacent first electric field shielding structures 150 and the spacing between two adjacent second electric field shielding structures 170 can be adjusted separately; specifically, the spacing between the two adjacent second electric field shielding structures 170 located in the drift region 113 is set to be The width W1 of the portion between the two adjacent second electric field shielding structures 170 is smaller than the width W2 of the channel region 161, so that the width W1 of the portion of the drift region 113 between the two adjacent second electric field shielding structures 170 can be set smaller while ensuring the width W2 of the channel region 161, so that the JFET resistance in the interval where the portion is located can be adjusted without affecting the channel resistance, greatly reducing the saturation current of the device and optimizing the short-circuit performance of the device; and the second electric field shielding structure 170 enhances the protection effect of the gate dielectric layer 130 at the bottom of the gate trench 120, thereby taking into account the specific on-resistance R sp With protection effect and short circuit performance.
[0063] Moreover, since W1 and W2 in the embodiment of the present application are the widths along the extension direction, the adjustment of W1 and W2 will not affect the spacing between adjacent gate trenches 120 , and will not reduce the number of gate trenches 120 arranged per unit area.
[0064] In the embodiment of the present application, the trench gate transistor is specifically, for example, a SiC MOSFET. 4H-SiC has a large bandgap, a high critical breakdown electric field, and a fast saturated electron drift velocity, and is an ideal material for making high-voltage MOSFETs. Of course, the present application does not exclude the possibility that the trench gate transistor is a transistor of other possible types.
[0065] like Figure 3 As shown, the trench gate transistor may further include a substrate 100. The semiconductor material layer 110 may be an epitaxial layer grown on the substrate 100. The substrate 100 may be a base of the transistor and a carrier for adding subsequent material layers.
[0066] The semiconductor material layer 110 may include an upper surface 111 for forming a gate trench 120 and a lower surface 112 opposite to the upper surface 111. Ignoring the flatness of the upper surface 111 and the lower surface 112, the direction perpendicular to the upper surface 111 and the lower surface 112 of the semiconductor material layer 110 is defined as the thickness direction of the semiconductor material layer 110, or the thickness direction of the device. The thickness direction of the device is also the stacking direction of the material layers subsequently deposited on the substrate 100, so it can also be called the height direction or depth direction of the device, which is shown as a "second direction" in the figure. Two mutually intersecting first directions and third directions are defined on the plane where the upper surface 111 of the semiconductor material layer 110 is located; the first direction and the third direction are, for example, two directions perpendicular to each other.
[0067] In some embodiments, semiconductor material layer 110 includes a silicon carbide epitaxial layer.
[0068] The semiconductor material layer 110 has a first conductivity type, which may be an N-type or a P-type.
[0069] In some embodiments, the first conductivity type is N-type. The semiconductor material layer 110 is an N-type semiconductor material layer. The substrate 100 is an N-type semiconductor substrate.
[0070] The gate trench 120 extends from the upper surface 111 of the semiconductor material layer 110 to the interior of the semiconductor material layer 110 . The gate trench 120 includes a sidewall 121 and a bottom wall 122 .
[0071] Exemplarily, the gate trench 120 can be formed by a photolithography process. Specifically, a mask material is first deposited on the semiconductor material layer 110, and then a predetermined formation position of the gate trench 120 is defined in the mask material by a photolithography process, thereby forming a patterned mask layer. Next, the semiconductor material layer 110 is etched using the patterned mask layer as a mask until the gate trench 120 is formed. This process is well known to those skilled in the art and will not be described in detail here.
[0072] The side wall 121 includes at least two first portions 1211 arranged at intervals along the extension direction and a second portion 1212 located between two adjacent first portions 1211. The extension direction refers to the extension direction of the side wall 121 on the plane where the upper surface 111 of the semiconductor material layer 110 is located. Figure 4 As an optional specific implementation, the projection of the gate trench 120 on the upper surface 111 of the semiconductor material layer 110 is a rectangle, wherein the width of the rectangle is the line width of the gate trench 120, and the length of the rectangle is the extension length of the gate trench 120. Furthermore, the sidewall 121 of the gate trench 120 extends along a straight line, Figure 4It is specifically shown in FIG. 1 that the side wall 121 extends along the third direction.
[0073] Of course, the present application is not limited thereto, and the planar shape of the gate trench 120 (i.e., the projection shape on the upper surface 111 of the semiconductor material layer 110) may also be other shapes, such as triangle, square, pentagon, hexagon, circle, etc. In this way, the side wall 121 may not extend along a straight line, so that the extension direction of the side wall 121 may not refer to a fixed direction, but may change continuously as the side wall 121 extends. Figure 8 For example, the planar shape of the gate trench 120 is a hexagon, and the extension direction of the sidewall 121 is along the side of the hexagon. Thus, the figure shows the first part 1211 and the second part 1212.
[0074] In a specific application, the first portion 1211 and the second portion 1212 may be arranged alternately. Specifically, along the above-mentioned extension direction, the side wall 121 includes the first portion 1211, the second portion 1212, the first portion 1211, the second portion 1212, ..., wherein the number of the first dielectric portion 131 and the second dielectric portion 132 is not necessarily equal, for example, one of them may be one more than the other.
[0075] When the planar shape of the gate trench 120 is a symmetrical shape, the sidewall 121 may include two sides opposite to each other with respect to the symmetry axis, and the distribution of the first portion 1211 and the second portion 1212 on the two sides may be the same.
[0076] Please continue to refer to Figure 3 The trench gate transistor may further include: a gate dielectric layer 130 in the gate trench 120 covering the sidewalls 121 and the bottom wall 122 of the gate trench 120 ; and a gate 140 located in the gate dielectric layer 130 .
[0077] Exemplarily, the gate dielectric layer 130 may be an oxide layer, and therefore may also be referred to as a gate oxide layer; specifically, for example, a silicon dioxide layer. In the actual preparation process, the gate oxide layer may be formed by an oxidation process, a deposition process, or a process of oxidation followed by deposition.
[0078] Exemplarily, the material of the gate 140 includes polysilicon, for example.
[0079] The first electric field shielding structure 150 is located outside the gate trench 120 and adjacent to the first portion 1211. The first electric field shielding structure 150 can also play a role in attracting electric fields and alleviating the problem of electric field concentration at the bottom of the gate dielectric layer 130.
[0080] The first electric field shielding structure 150 can be formed by a doping process, such as an ion implantation process. Exemplarily, the first electric field shielding structure 150 can have a second conductivity type, which is different from the first conductivity type. In other words, the first electric field shielding structure 150 is different from the conductivity type of the semiconductor material layer 110; thus, it can play a role in attracting or depleting a part of the electric field. In practical applications, the first electric field shielding structure 150 can be a P-type; the first electric field shielding structure 150 can also be called a P link structure.
[0081] The first electric field shielding structure 150 may surround both sides and the bottom wall of the gate trench 120. On the plane where the upper surface 111 of the semiconductor material layer 110 is located, the projection of the first electric field shielding structure 150 intersects with the projection of the gate trench 120; further, the two may intersect vertically.
[0082] Two adjacent first electric field shielding structures 150 may be parallel or non-parallel. Figure 4 The case where two adjacent first electric field shielding structures 150 are parallel is shown; and further, each first electric field shielding structure 150 is perpendicular to the gate trench 120, or perpendicular to the extension direction of the sidewall 121. In some other embodiments, two adjacent first electric field shielding structures 150 may also be parallel but not perpendicular to the gate trench 120. The embodiment of the present application does not specifically limit this. Figure 8 The case where two adjacent first electric field shielding structures 150 are not parallel is shown; and further, specifically, the case where they intersect. For any two first electric field shielding structures 150 intersecting, the intersection position can be located below the gate trench 120; of course, the present application does not exclude the case where they intersect at other positions. At the sidewall of the gate trench 120, the two adjacent first electric field shielding structures 150 are arranged at intervals.
[0083] The body region 160 is located outside the gate trench 120 and adjacent to the second portion 1212. The portion of the body region 160 close to the gate trench 120 is used to form a channel region 161 (see Figure 6 ). It can be understood that when the first portion 1211 and the second portion 1212 are arranged alternately, along the side wall 121 , the first electric field shielding structure 150 and the body region 160 are arranged alternately.
[0084] The body region 160 may be formed by a doping process, such as an ion implantation process. For example, the body region 160 may have a second conductivity type, which is different from the first conductivity type. In other words, the body region 160 is different from the conductivity type of the semiconductor material layer 110. In practical applications, the body region 160 may be a P-type; the body region 160 may also be referred to as a P body region.
[0085] Specifically, the ion doping concentration of the body region 160 is lower than the ion doping concentration of the first electric field shielding structure 150 .
[0086] The surface layer of the body region 160 may include a source contact region 200 . The source contact region 200 extends from the upper surface 111 of the semiconductor material layer 110 to the inside of the semiconductor material layer 110 .
[0087] The source contact region 200 has a first conductivity type. The source contact region 200 has the same conductivity type as the semiconductor material layer 110, but is opposite to the conductivity type of the body region 160. The ion doping concentration of the source contact region 200 is higher than that of the semiconductor material layer 110. Exemplarily, the source contact region 200 is an N+ doped region; the source contact region 200 is formed, for example, by heavily inverse doping the surface layer of the body region 160.
[0088] Please refer to Figure 4 and Figure 6 When the device is working, the portion of the body region 160 close to the gate trench 120 forms a channel region 161. Figure 4 In order to clearly show the various marks, the channel region 161 is schematically shown only on the left side of the gate trench 120 in the figure, but it should be understood that the channel region 161 is also formed on the right side of the gate trench 120 in the figure (i.e., the side marked as the second part 1212).
[0089] The drift region 113 is located below the channel region 161. In an actual device, the remaining portion of the semiconductor material layer 110 is used to form the drift region of the device.
[0090] The second electric field shielding structure 170 is located below the first electric field shielding structure 150. The second electric field shielding structure 170 can play a role in attracting electric fields and alleviating the problem of electric field concentration at the bottom of the gate dielectric layer 130.
[0091] Specifically, in the semiconductor material layer 110 , the second electric field shielding structure 170 , for example, at least includes a portion whose depth is greater than or equal to the depth of the gate trench bottom wall 122 .
[0092] The second electric field shielding structure 170 can be formed by a doping process, such as an ion implantation process. Exemplarily, the second electric field shielding structure 170 can have a second conductivity type, which is different from the first conductivity type. In other words, the second electric field shielding structure 170 is different from the conductivity type of the semiconductor material layer 110; thus, it can play a role in attracting or depleting a portion of the electric field. The second electric field shielding structure 170 has the same conductivity type as the first electric field shielding structure 150. In practical applications, the second electric field shielding structure 170 can be P-type.
[0093] The second electric field shielding structure 170 and the first electric field shielding structure 150 are formed in different doping processes. In actual preparation, the second electric field shielding structure 170 and the first electric field shielding structure 150 can both be selectively doped; masks are used to define the formation areas of the second electric field shielding structure 170 and the first electric field shielding structure 150 respectively during the formation process. The mask used to form the second electric field shielding structure 170 is different from the mask used to form the first electric field shielding structure 150.
[0094] As an optional specific implementation, the ion doping concentration of the second electric field shielding structure 170 is greater than the ion doping concentration of the first electric field shielding structure 150 ; thus, the second electric field shielding structure 170 plays a role in better protecting the gate dielectric layer 130 .
[0095] As an optional specific implementation, the ion doping concentration of the second electric field shielding structure 170 is greater than the ion doping concentration of the body region 160. Further, the ion doping concentration of the body region 160 is less than the ion doping concentration of the first electric field shielding structure 150 and less than the ion doping concentration of the second electric field shielding structure 170. Thus, the gate dielectric layer 130 is better protected while ensuring the effective operation of the device.
[0096] The projection of the first electric field shielding structure 150 on the upper surface 111 of the semiconductor material layer 110 may fall within the projection range of the second electric field shielding structure 170. The planar shape of the second electric field shielding structure 170 (i.e., the projection shape on the upper surface 111 of the semiconductor material layer 110) may be the same as the planar shape of the first electric field shielding structure 150, except that the boundary of the second electric field shielding structure 170 exceeds the boundary of the first electric field shielding structure 150 in the extension direction along the sidewall 121. In the extension direction along the sidewall 121, the second electric field shielding structure 170 protrudes from the first electric field shielding structure 150. In an actual device, in the extension direction along the sidewall 121, there is a clear gap between the boundary of the portion of the second electric field shielding structure 170 extending to the bottom of the channel region 161 and the boundary of the first electric field shielding structure 150 above it.
[0097] It should be understood that the present application does not exclude the situation that the planar shape of the second electric field shielding structure 170 is different from the planar shape of the first electric field shielding structure 150. In addition, the present application does not exclude the situation that the second electric field shielding structure 170 does not completely cover the bottom of the first electric field shielding structure 150.
[0098] In the embodiment of the present application, the width W1 of the portion of the drift region 113 located between two adjacent second electric field shielding structures 170 is smaller than the width W2 of the channel region 161, thereby taking into account the specific on-resistance R sp and the saturation current of the device.
[0099] Please refer to Fig.18 and Fig.19 , where the solid line corresponds to the embodiment of the present application, and the dotted line corresponds to the related art. Fig.18 As shown, at V gs The simulation test is carried out under the condition that the gate to source voltage is equal to 18V, and V ds (Drain To Source Voltage) in the range of 0V-500V ds -V ds curve; understandably, Fig.18 It mainly characterizes the saturation region of the device. Fig.18 Same V ds I ds It can be seen from the comparison between the drain-to-source current and the trench-gate transistor provided in the embodiment of the present application that the trench-gate transistor I in the related art is ds Significantly reduced. Fig.19 As shown, at V gs The simulation test is carried out under the condition of 18V to obtain V ds In the range of 0V-1V, I ds -V ds curve; understandably, Fig.19 It mainly characterizes the linear region of the device. Fig.19 The inverse of the slope of the curve represents R dson (Drain To Source Resistance, drain-source on-state resistance), due to the ratio of on-resistance R sp =R dson *Chip active area, so when the active area remains unchanged, R sp Can represent R dson By comparing the linear region, it can be seen that the trench gate transistor provided in the embodiment of the present application is compared with the trench gate transistor R in the related art. dson Slightly increase, thus slightly sacrificing R sp In the case of , the saturation current of the device is greatly reduced, thereby optimizing the short-circuit performance. It should be understood that the present application does not necessarily sacrifice R sp In some embodiments, R can be further balanced by adjusting the size of W1. sp With R dson relationship.
[0100] Please combine Figure 3 , Figure 5 and Figure 6As an optional specific implementation, the bottom of the first electric field shielding structure 150 is farther away from the upper surface 111 of the semiconductor material layer 110 than the bottom of the body region 160 , so that a gap D1 exists between the second electric field shielding structure 170 and the body region 160 .
[0101] Further, along the extension direction, the width W1 of the portion of the drift region 113 located between two adjacent second electric field shielding structures 170 is smaller than the width W3 of the portion located between two adjacent first electric field shielding structures 150. It can be understood that, when the boundary of the first electric field shielding structure 150 remains substantially unchanged along the depth direction, W3 is substantially equal to W2, and both are greater than W1. When the boundary of the first electric field shielding structure 150 changes along the depth direction, the upper half of the first electric field shielding structure 150 and the body region 160 are in an either-or relationship, and the spacing between the upper half of the two adjacent first electric field shielding structures 150 is equal to the width W2 of the channel region 161, but the lower half of the first electric field shielding structure 150 can extend to the bottom of the channel region 161, so that W3 can be smaller than W2, and in this case W3 is still greater than W1, so as to ensure that the specific on-resistance R is taken into account. sp and short circuit performance.
[0102] Furthermore, the second electric field shielding structure 170 is spaced 0.25 μm to 1.2 μm from the body region 160, that is, D1 is in the range of 0.25 μm to 1.2 μm. It should be noted that when D1 is less than 0.25 μm, due to longitudinal diffusion, the ions doped in the second electric field shielding structure 170 may invade the body region 160, causing R dson becomes larger; when D1 is greater than 1.2μm, the difficulty of process implementation increases.
[0103] It should be noted that this application does not exclude the case where D1 is equal to 0. Fig. 9 In the semiconductor material layer 110, the depth of the bottom of the first electric field shielding structure 150 can be substantially the same as the depth of the bottom of the body region 160, so that the second electric field shielding structure 170 at least partially extends to the bottom of the channel region 161, specifically, the second electric field shielding structure 170 is at least partially adjacent to the body region 160 below the channel region 161.
[0104] As an optional specific implementation, the second electric field shielding structure 170 is adjacent to the bottom of the first electric field shielding structure 150. The second electric field shielding structure 170 and the first electric field shielding structure 150 are electrically connected by direct contact.
[0105] Furthermore, the second electric field shielding structure 170 and the first electric field shielding structure 150 are both connected to the ground potential, so as to better play the role of shielding and better achieve the role of weakening the electric field strength at the bottom of the gate dielectric layer 130 .
[0106] The surface layer of the first electric field shielding structure 150 may include a first electric field shielding structure contact region 190. The first electric field shielding structure contact region 190 extends from the upper surface 111 of the semiconductor material layer 110 to the inside of the semiconductor material layer 110; the first electric field shielding structure contact region 190 is specifically located above the portion of the first electric field shielding structure 150 distributed on both sides of the gate trench 120.
[0107] The first electric field shielding structure contact region 190 is conductively connected to both the first electric field shielding structure 150 and the source contact region 200 . The first electric field shielding structure 150 is conductively connected to the source contact region 200 via the first electric field shielding structure contact region 190 , thereby being connected to the ground potential.
[0108] The first electric field shielding structure contact region 190 has a second conductivity type, which is different from the first conductivity type. In other words, the first electric field shielding structure contact region 190 has a conductivity type opposite to that of the semiconductor material layer 110, and is the same as that of the first electric field shielding structure 150, but has an ion doping concentration higher than that of the first electric field shielding structure 150. Exemplarily, the first electric field shielding structure contact region 190 is a P+ doped region; and is formed by heavily doping the surface layer of the first electric field shielding structure 150.
[0109] As an optional specific embodiment, the trench gate transistor also includes: a third electric field shielding structure 180, which is located below the gate trench 120 and has an overlapping area with the first electric field shielding structure 150 and / or the second electric field shielding structure 170, and the third electric field shielding structure 180 is conductively connected to the first electric field shielding structure 150 and / or the second electric field shielding structure 170 through the overlapping area.
[0110] The first electric field shielding structure 150 , the second electric field shielding structure 170 , and the third electric field shielding structure 180 are all electric field shielding structures corresponding to the same gate trench 120 .
[0111] The third electric field shielding structure 180 can be formed by a doping process, such as an ion implantation process. Exemplarily, the third electric field shielding structure 180 can have a second conductivity type, which is different from the first conductivity type. In other words, the third electric field shielding structure 180 is different from the conductivity type of the semiconductor material layer 110; thus, it can play a role in attracting or depleting a part of the electric field. In practical applications, the third electric field shielding structure 180 can be a P type; the third electric field shielding structure 180 can also be called a P shield structure.
[0112] The bottom of the gate dielectric layer 130 is protected by the third electric field shielding structure 180 without affecting the formation of the channel region, so the protection effect of the gate dielectric layer 130 can be further enhanced. Further setting the third electric field shielding structure 180 on the basis of setting the first electric field shielding structure 150 and the second electric field shielding structure 170 is more conducive to taking into account the electric field shielding effect at the bottom of the gate dielectric layer 130 and the influence on the on-resistance of the trench gate transistor.
[0113] Furthermore, the third electric field shielding structure 180 is connected to the ground potential through the first electric field shielding structure 150 and / or the second electric field shielding structure 170 ; thus, the shielding effect can be better exerted to better achieve the effect of weakening the electric field strength at the bottom of the gate dielectric layer 130 .
[0114] Next, please refer to Fig.10 and Fig.11 As an optional specific implementation, the width W1 of the portion of the drift region 113 located between two adjacent second electric field shielding structures 170 increases from a direction close to the gate trench 120 to a direction away from the gate trench 120 .
[0115] exist Figure 4 In the illustrated embodiment, the distance between two adjacent second electric field shielding structures 170 is substantially unchanged, so that W1 remains unchanged in the direction from close to the gate trench 120 to far away from the gate trench 120. It can be understood that Fig.10 and Fig.11 The saturation current of the device of the embodiment shown is also reduced compared to the related art. Figure 4 In the embodiment shown, W1 and Fig.10 and Fig.11 In the case where the minimum W1 in the embodiment shown is equal, Fig.10 and Fig.11 The saturation current of the embodiment shown will be greater than Figure 4 The saturation current of the embodiment shown, that is, the effect of reducing the saturation current is not Figure 4 The embodiment shown is good; however, the on-resistance R sp will be better than Figure 4 Thus, by setting W1 to increase from the direction close to the gate trench 120 to the direction away from the gate trench 120, the adjustment of R sp flexibility with short circuit performance.
[0116] For further information, please refer to Fig.10 In some embodiments, the intervals between the portions of two adjacent second electric field shielding structures 170 located below the gate trench 120 are equal.
[0117] For further information, please refer to Fig.11 In some other embodiments, the distance between the portions of two adjacent second electric field shielding structures 170 located below the gate trench 120 decreases in the direction toward the center of the gate trench 120. It can be understood that compared to Fig.10 In the embodiment shown, Fig.11 In the embodiment shown, the minimum distance between two adjacent second electric field shielding structures 170 is equal to Fig.10 In the embodiment shown, the distance between the portions of two adjacent second electric field shielding structures 170 located below the gate trench 120 is Fig.11 The implementation shown can achieve a larger saturation current and a smaller R sp .
[0118] Next, please refer to Fig.12 and Fig.13 As an optional specific implementation, the trench gate transistor further includes: a current diffusion layer 230 located in the JFET region 114 below the body region 160 , and the ion doping concentration of the current diffusion layer 230 is greater than the ion doping concentration of the drift region 113 .
[0119] It can be understood that the electric field shielding structure forms a JFET between the body region 160 while protecting the bottom of the gate dielectric layer 130. The presence of the parasitic JFET will reduce the current density of the device. In this embodiment, by providing a current diffusion layer 230 in the JFET region 114, the parasitic resistance of the parasitic JFET can be reduced, thereby improving the conductivity of the device.
[0120] The current diffusion layer 230 may be formed by a doping process, such as an ion implantation process. For example, the current diffusion layer 230 may have a first conductivity type; in other words, the current diffusion layer 230 has the same conductivity type as the semiconductor material layer 110, but the ion doping concentration of the current diffusion layer 230 is greater than the ion doping concentration of the semiconductor material layer 110.
[0121] Next, please refer to Figures 14 to 17 As an optional specific implementation, the trench gate transistor further includes: an interlayer dielectric layer 210 located in the gate trench 120 and above the gate 140 ; and a conductive layer 220 located on the semiconductor material layer 110 . The conductive layer 220 and the gate 140 are insulated and isolated by the interlayer dielectric layer 210 .
[0122] It can be understood that the conductive layer 220 is used to be conductively connected to the source contact region 200, but needs to be insulated and isolated from the gate 140. Figures 3 to 7If the interlayer dielectric layer 210 is disposed on the semiconductor material layer 110, then in order to ensure that the interlayer dielectric layer 210 can completely cover the gate 140, it is usually necessary to design the interlayer dielectric layer 210 to be slightly larger than the plane size of the gate 140, so that the layout space of the source conductive contact hole is limited. Due to the size limitation of the source conductive contact hole, it is difficult to further reduce the cell size, R sp This embodiment, by placing the interlayer dielectric layer 210 in the gate trench 120, not only eliminates the photolithography process of defining the position of the interlayer dielectric layer 210, realizes a self-aligned structure, but also avoids the source conductive contact hole, thereby further reducing the cell size, which is conducive to reducing R sp .
[0123] The trench gate transistor may further include: a drain (not shown in the figure), located on the side where the lower surface 112 of the semiconductor material layer 110 is located. Specifically, the drain is located on the side of the substrate 100 away from the epitaxial layer (semiconductor material layer 110). In an actual device, the drain may be a metal drain.
[0124] It should be noted that the various technical features in the technical solutions recorded in the embodiments of the present application can be combined arbitrarily without conflict.
[0125] It should be understood that the above embodiments are exemplary and are not intended to include all possible implementations. Various modifications and changes may also be made on the basis of the above embodiments without departing from the scope of the present disclosure. Similarly, the various technical features of the above embodiments may also be combined arbitrarily to form other embodiments of the present application that may not be clearly described. Therefore, the above embodiments only express several implementations of the present application and do not limit the scope of protection of the patent of this application.
Claims
1. A trench gate transistor, characterized in that: include: a semiconductor material layer; A gate trench extending from the upper surface of the semiconductor material layer to the inside, the gate trench comprising a side wall and a bottom wall, the side wall comprising at least two first portions spaced apart along an extension direction and a second portion located between two adjacent first portions, the extension direction referring to an extension direction of the side wall on the plane where the upper surface of the semiconductor material layer is located; A first electric field shielding structure, located outside the gate trench and adjacent to the first portion; a body region, located outside the gate trench and adjacent to the second portion, wherein a portion of the body region close to the gate trench is used to form a channel region; A drift region, located below the channel region; The second electric field shielding structure is located below the first electric field shielding structure and at least partially extends below the channel region, so that along the extension direction, the width of the drift region between two adjacent second electric field shielding structures is smaller than the width of the channel region.
2. The trench gate transistor according to claim 1, characterized in that: The bottom of the first electric field shielding structure is further away from the upper surface of the semiconductor material layer than the bottom of the body region, so that there is a gap between the second electric field shielding structure and the body region; Along the extension direction, the width of the drift region between two adjacent second electric field shielding structures is smaller than the width of the drift region between two adjacent first electric field shielding structures; and / or the second electric field shielding structure is spaced 0.25 μm to 1.2 μm from the body region.
3. The trench gate transistor according to claim 1, characterized in that: The ion doping concentration of the second electric field shielding structure is greater than the ion doping concentration of the first electric field shielding structure.
4. The trench gate transistor according to claim 1 or 3, characterized in that: The ion doping concentration of the body region is less than the ion doping concentration of the first electric field shielding structure and less than the ion doping concentration of the second electric field shielding structure.
5. The trench gate transistor according to claim 1, wherein: The width of a portion of the drift region located between two adjacent second electric field shielding structures increases from a direction close to the gate trench to a direction away from the gate trench.
6. The trench gate transistor according to claim 1, characterized in that: The second electric field shielding structure is adjacent to the bottom of the first electric field shielding structure; The second electric-field shield structure and the first electric-field shield structure are both connected to a ground potential.
7. The trench gate transistor according to claim 1, wherein: The first electric field shielding structure surrounds two sides and a bottom wall of the gate trench.
8. The trench gate transistor according to claim 1, wherein: Also includes: A third electric field shielding structure is located below the gate trench and has an overlapping area with the first electric field shielding structure and / or the second electric field shielding structure, and the third electric field shielding structure is conductively connected to the first electric field shielding structure and / or the second electric field shielding structure through the overlapping area.
9. The trench gate transistor according to claim 1, characterized in that: Also includes: A current diffusion layer is located in the JFET region below the body region, and the ion doping concentration of the current diffusion layer is greater than the ion doping concentration of the drift region.
10. The trench gate transistor according to claim 1, wherein: Also includes: a gate dielectric layer, in the gate trench, covering the sidewalls and bottom wall of the gate trench; A gate, located in the gate dielectric layer; An interlayer dielectric layer, located in the gate trench and above the gate; A conductive layer is located on the semiconductor material layer, and the conductive layer is insulated and isolated from the gate by the interlayer dielectric layer.