Semiconductor device
The challenges in integration density and performance are solved by designing multi-layered internal connection structures and vertical metal-insulator-metal capacitors in semiconductor devices, and efficient capacitor integration is achieved.
Patent Information
- Application Number
- CN202421366418.X
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Priority Date
- 2023-07-14
- Filing Date
- 2024-06-14
- Publication Date
- 2025-04-18
- Estimated Expiration
- 2034-06-14
AI Technical Summary
With the reduction of the minimum feature size of semiconductor devices, metal-insulator-metal capacitors have challenges in integration density and performance, which are difficult to effectively solve.
A semiconductor device including a multi-layer internal connection structure and a vertical metal-insulator-metal capacitor is designed. The capacitor has a high K gap wall and a vertically extended side wall, and the integrated density and performance of the capacitor are improved by forming a first electrode, a high K gap wall and a second electrode in a multi-layer internal connection structure, and connecting the electrodes with conductive features.
Through this design, the effect of improving the integration density and performance of metal-insulator-metal capacitors in semiconductor devices is achieved, solving the challenges of capacitors in integration density and performance after the minimum feature size is reduced.
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Figure CN222776522U_ABST
Abstract
Description
Technical Field
[0001] The present disclosure relates to a semiconductor device, and more particularly to a semiconductor device including a metal-insulator-metal capacitor. Background Art
[0002] Semiconductor devices are used in a variety of electronic applications, such as personal computers, mobile phones, digital cameras, and other electronic products. Semiconductor devices are generally made by sequentially depositing insulating or dielectric layers, conductive layers, and semiconductor layers of materials on a semiconductor substrate, and using lithography to pattern the various material layers to form circuit components and elements thereon.
[0003] The semiconductor industry continues to optimize the integration density of various electronic components (e.g., transistors, diodes, resistors, capacitors, etc.) by continuously reducing feature sizes to fit more devices into a given area. However, as the minimum feature size decreases, additional problems arise and must be solved.
[0004] One type of capacitor is a metal-insulator-metal (MIM) capacitor, which is used in mixed-signal devices and logic devices, such as embedded memory and radio frequency devices. Metal-insulator-metal capacitors are used to store charge in various semiconductor devices. However, there are still many challenges with metal-insulator-metal capacitors. Utility Model Content
[0005] One aspect of the present disclosure is to provide a semiconductor device. The semiconductor device includes: a substrate; a transistor on the substrate, wherein the transistor includes a source, a drain and a gate; a multi-layer interconnect structure, wherein the multi-layer interconnect structure is configured to provide electrical connection between the source, the drain and the gate, and the multi-layer interconnect structure has multiple interconnect layers; and a metal-insulator-metal capacitor in the multi-layer interconnect structure, wherein the metal-insulator-metal capacitor includes a first electrode, a high-K spacer and a second electrode, the high-K spacer has a first vertically extending sidewall and a second vertically extending sidewall, the first vertically extending sidewall and the first electrode have a vertically extending interface, and the second vertically extending sidewall and the second electrode have a vertically extending interface.
[0006] Another aspect of the present disclosure is to provide a semiconductor device, which includes: a transistor on a substrate, wherein the transistor includes a source, a drain and a gate; a multi-layer interconnect structure on the substrate, wherein the multi-layer interconnect structure is configured to provide electrical connection between the source, the drain and the gate, and the multi-layer interconnect structure has multiple interconnect layers; a metal-insulator-metal capacitor in the multi-layer interconnect structure, wherein the metal-insulator-metal capacitor includes a first electrode, a high-K spacer and a second electrode, and the first electrode, the high-K spacer and the second electrode are all formed in the same layer of the multi-layer interconnect structure; a first conductive feature connected to the first electrode; and a second conductive feature connected to the second electrode.
[0007] Another aspect of the present disclosure is to provide a semiconductor device. The semiconductor device includes: a multi-layer interconnect structure, wherein the multi-layer interconnect structure has a first intermetallic dielectric layer and a second intermetallic dielectric layer; a metal-insulator-metal capacitor in the first intermetallic dielectric layer, wherein the metal-insulator-metal capacitor includes: an insulating layer having a first vertically extending sidewall and a second vertically extending sidewall; a first capacitor electrode adjacent to the first vertically extending sidewall of the insulating layer; and a second capacitor electrode adjacent to the second vertically extending sidewall of the insulating layer, wherein the insulating layer is located between the first capacitor electrode and the second capacitor electrode, and each of the interfaces of the first capacitor electrode and the insulating layer and the interfaces of the second capacitor electrode and the insulating layer extend in a vertical direction; a first conductive feature located in the multi-layer interconnect structure, wherein the first conductive feature is connected to the first capacitor electrode; and a second conductive feature located in the multi-layer interconnect structure, wherein the second conductive feature is connected to the second capacitor electrode. BRIEF DESCRIPTION OF THE DRAWINGS
[0008] The present disclosure is better understood by reading the following detailed description in conjunction with the accompanying drawings. It should be noted that, as is standard practice in the industry, many features are not drawn to scale. In fact, for the sake of clarity of discussion, the dimensions of many features may be arbitrarily scaled.
[0009] Figure 1 is a cross-sectional view of a portion of an exemplary semiconductor device illustrating a stage of an integrated circuit process according to various embodiments;
[0010] Figure 2 is a process flow diagram illustrating an exemplary process for forming a vertical metal-insulator-metal capacitor according to various embodiments;
[0011] Figure 3A , Figure 4A , Figure 5A , Fig. 6A , Fig. 7A , Fig. 8A and Figure 8Bis a plan view (or top view) of an exemplary semiconductor structure at various stages in the fabrication of a vertical metal-insulator-metal capacitor according to various embodiments;
[0012] Figure 3B , Figure 4B , Figure 5B , Figure 6B , Figure 7B and Figure 7C is a cross-sectional view of an exemplary semiconductor structure at various stages in the fabrication of a vertical metal-insulator-metal capacitor according to various embodiments;
[0013] Fig. 9 is a flow chart illustrating an exemplary process of forming a semiconductor device having a vertical metal-insulator-metal capacitor according to various embodiments.
[0014]
Explanation of symbols
[0015] 100:Semiconductor device
[0016] 102: Base material
[0017] 103: Device elements
[0018] 104: Inner connection structure
[0019] 106: first insulating layer
[0020] 108: Second insulation layer
[0021] 110: The third insulating layer
[0022] 112: first intermetallic dielectric layer
[0023] 114: Second intermetallic dielectric layer
[0024] 116: third intermetallic dielectric layer
[0025] 118:Metal Wire
[0026] 120: Via
[0027] 120a: first conductive feature
[0028] 120b: second conductive feature
[0029] 122: Metal-Insulator-Metal Capacitor
[0030] 123: Intermediate etching stop layer
[0031] 124: Insulation layer
[0032] 125: Bottom etching stop layer
[0033] 126: first capacitor metal layer
[0034] 127: first vertically extending side wall
[0035] 128: Second capacitor metal layer
[0036] 129: Second vertically extending side wall
[0037] 200: Craftsmanship
[0038] 202,204,206,208,210,212,214: Blocks
[0039] 302: first intermetallic dielectric layer
[0040] 304: Second intermetallic dielectric layer
[0041] 306,308: vias
[0042] 402: Opening
[0043] 403: Top
[0044] 404: Patterned part
[0045] 405: Bottom etching stop layer
[0046] 407: Main body
[0047] 409: Toothed part
[0048] 502: High K spacer layer
[0049] 602: barrier seed layer
[0050] 604: Ditch
[0051] 702: first capacitor electrode
[0052] 704: second capacitor electrode
[0053] 732: Via
[0054] 734:Metal layer
[0055] 736: Via
[0056] 800,820:Semiconductor structure
[0057] 802, 822: first capacitor electrode
[0058] 804,824: second capacitor electrode
[0059] 806,826: High K spacer layer
[0060] 808: Main part
[0061] 810: Toothed part
[0062] 900: Craftsmanship
[0063] 910,920,930,940,950: Steps DETAILED DESCRIPTION
[0064] The following disclosure provides many different embodiments or illustrations to implement different features of the novel invention. The specific illustrations of components and configurations described below are intended to simplify the disclosure. These are of course only for illustration and are not intended to be limiting.
[0065] For the purpose of brevity, conventional techniques related to the processes of conventional semiconductor devices are not described in detail herein. Furthermore, the various tasks and processes described in the present disclosure may be included in a broader process or a process with additional functions, which are not described in detail herein. In particular, the various processes of semiconductor devices are well known, so for the sake of brevity, many conventional processes are only briefly and or completely omitted in the present disclosure without providing details of the conventional processes. A person with ordinary knowledge in the art can understand after reading the present disclosure in detail that the structure disclosed herein can be used by various technologies and can be included in various semiconductor devices and products. Furthermore, it should be noted that the semiconductor device structure includes a large number of components, and a single component shown in the accompanying drawings can represent multiple components.
[0066] It should be understood that although the terms "first", "second", "third", etc. are used in the present disclosure to describe various components, elements, regions, layers, parts and / or components, these components, elements, regions, layers, parts and / or components are not limited by these terms. The aforementioned terms are only used to distinguish one component, element, region, layer, part or component from another component, element, region, layer, part or component. Therefore, the first component, first element, first region, first layer, first part or first component described below can be represented as a second component, second element, second region, second layer, second part or second component without departing from the teachings of the present disclosure.
[0067] Furthermore, spatially relative terms, such as "over," "overlying," "above," "upper," "top," "under," "underlying," "below," "lower," "bottom," etc., are used to facilitate description of the relationship of parts or features illustrated in the drawings to other parts or features. Spatially relative terms encompass different orientations of the elements in use or operation in addition to the orientation depicted in the drawings. The device may be otherwise oriented (rotated 90 degrees or at other orientations), and the spatially relative descriptors used in the disclosure may be interpreted so.
[0068] In addition, the disclosure repeats reference numerals and / or letters in various embodiments. This repetition is for simplicity and clarity of description and does not represent a relationship between the various discussed embodiments and / or configurations.
[0069] It should be noted that references to "one embodiment", "an embodiment", "an example embodiment", "exemplary", "example", etc. in the specification indicate that the embodiment described may include particular features, structures or characteristics, but not every embodiment may include particular features, structures or characteristics. Furthermore, such phrases do not necessarily refer to the same embodiment. Furthermore, when particular features, structures or characteristics are described in connection with an embodiment, whether or not explicitly stated, a person with ordinary knowledge in the art should understand that such features, structures or characteristics may be connected to another embodiment.
[0070] In certain embodiments of the present disclosure, a "material layer" is a layer comprising at least 50 wt.% of a specified material, such as at least 60 wt.% of a specified material, at least 75 wt.% of a specified material, at least 90 wt.% of a specified material, at least 95 wt.% of a specified material, at least 99 wt.% of a specified material; and a layer of "material" comprising at least 50 wt.% of a specified material, such as at least 60 wt.% of a specified material, at least 75 wt.% of a specified material, at least 90 wt.% of a specified material, at least 95 wt.% of a specified material, at least 99 wt.% of a specified material. For example, in certain embodiments, each aluminum layer and a layer of aluminum is a layer, such as at least 50 wt.%, at least 60 wt.%, at least 75 wt.%, at least 90 wt.%, at least 95 wt.%, or at least 99 wt.% of aluminum.
[0071] It should be understood that the phrases or terms of the present disclosure are for the purpose of description rather than limitation, so that the phrases or terms of the present disclosure specification can be understood by those with ordinary knowledge in the relevant field according to the teachings of the present disclosure.
[0072] The following disclosure provides many different embodiments or examples to implement different features of the novel invention. The specific examples of components and configurations described below are intended to simplify the disclosure. These are of course only examples and are not intended to be limiting. For example, a description of a first feature formed on or above a second feature includes embodiments in which the first feature and the second feature are in direct contact, and also includes embodiments in which other features are formed between the first feature and the second feature so that the first feature and the second feature are not in direct contact. Throughout the specification, unless otherwise specified, the same element symbols in different drawings represent the same or similar elements formed by the same or similar methods using the same or similar materials.
[0073] Additional operations may be provided before, during, and / or after the stages described in these embodiments. In different embodiments, some of the stages described may be replaced or eliminated. Additional features may be added to the semiconductor device structure. For different embodiments, some of the features described below may be replaced or eliminated. Although some embodiments are described as performing operations in a specific order, the operations may be performed in other logical orders.
[0074] As used herein, a "layer" is a region, such as a region including arbitrary boundaries, and not necessarily of uniform thickness. For example, a layer may be a region having at least some varying thickness.
[0075] Figure 1 FIG. 1 is a cross-sectional view of a portion of an exemplary semiconductor device 100 at a stage in an integrated circuit process according to various embodiments. The semiconductor device 100 includes a substrate 102 and an interconnect structure 104 .
[0076] The substrate 102 may include any number of conductive features and device elements 103 formed in and / or over a semiconductor substrate. For example, the conductive features may include plugs, interconnects, wires, etc. For example, the device elements 103 may include transistors, diodes, capacitors, etc. For example, the transistors may be metal oxide semiconductor field effect transistors (MOSFETs), complementary metal oxide semiconductor (CMOS) transistors, bipolar junction transistors (BJTs), high voltage transistors, high frequency transistors, p-channel field effect transistors (PFETs) and / or n-channel field effect transistors (PFETs), diodes, or other suitable elements. In various embodiments, the transistors include a source, a drain, a gate electrode, a gate dielectric, and a channel. The substrate 102 may further include isolation features (not shown), such as shallow trench isolation (STI) features or local oxidation of silicon (LOCOS) features. Isolation features can define and isolate various device elements.
[0077] The interconnect structure 104 provides wiring and electrical connections between device elements 103 formed in and / or on the substrate 102. The interconnect structure 104 may include a plurality of insulating layers (a first insulating layer 106, a second insulating layer 108, and a third insulating layer 110 are shown in FIG. Figure 1 ). The illustrated first insulating layer 106, the second insulating layer 108, and the third insulating layer 110 include a first inter-metal dielectric (IMD) layer 112, a second inter-metal dielectric layer 114, and a third inter-metal dielectric layer 116, respectively, and may include one or more conductive features. In this embodiment, the conductive features include metal lines 118 and / or vias 120 formed in the metallization layer. The conductive features may be electrically connected to active components and / or passive components of the substrate 102 via contacts (not shown in the drawings).
[0078] In various embodiments, the interconnect structure 104 electrically connects a source, a drain, a gate electrode, a gate dielectric and / or a channel of a transistor, and other features of a substrate or other features or devices on the substrate or in the interconnect structure 104 .
[0079] In some embodiments, the interconnect structure 104 may be formed using a single damascene process and / or a dual damascene process, a via-first process, or a metal-first process. In one embodiment, an insulating layer and an opening (not shown) may be formed therein using appropriate photolithography and etching techniques. For example, the first intermetallic dielectric layer 112, the second intermetallic dielectric layer 114, and the third intermetallic dielectric layer 116 may be or may include an oxide film, such as silicon oxide, undoped silicon glass (USG), fluorinated silica glass (FSG), boron doped silicon glass (BSG), phosphosilicate glass (PSG), boron phosphorous-doped silicate glass (BPSG), polyethylene oxide (PEOX), thermal oxide, silicon dioxide (SiO2), or other suitable dielectric materials. One or more of the first intermetal dielectric layer 112, the second intermetal dielectric layer 114, and the third intermetal dielectric layer 116 may be composed of a low dielectric constant (low-k) material, such as a dielectric constant less than about 3.0, or less than about 2.5. One or more of the first intermetal dielectric layer 112, the second intermetal dielectric layer 114, and the third intermetal dielectric layer 116 may include an intermediate etch stop layer 123 and / or a bottom etch stop layer 125.
[0080] The conductive material of the metal line 118 and / or the via 120 may be formed in the openings in the intermetal dielectric layer, wherein the conductive material may be, for example, copper (Cu), aluminum (Al), tungsten (W), nickel (Ni), cobalt (Co), silver (Ag), titanium (Ti), titanium nitride (TiN), gallium (Ga), zinc (Zn), ruthenium (Ru), molybdenum (Mo), indium tix oxide (ITO), combinations thereof, or other suitable materials, and may be formed in the openings using electrochemical plating processes, chemical vapor deposition (CVD), atomic layer deposition (ALD), physical vapor deposition (PVD), or combinations thereof. After the conductive material is formed, a planarization process such as chemical mechanical polishing (CMP) may be used to remove excess conductive material, thereby leaving conductive features in the openings of the insulating layer. The process may then be repeated to form additional insulating layers and conductive features therein. Figure 1 The interconnect structure 104 is shown for illustration purposes only. The interconnect structure 104 may include other configurations and may include one or more metal lines and intermetallic dielectric layers.
[0081] The exemplary interconnect structure 104 also includes a metal-insulator-metal (MIM) capacitor 122 formed in an opening in an intermetal dielectric layer (e.g., third intermetal dielectric layer 116) and on the substrate 102. The exemplary metal-insulator-metal capacitor 122 has a vertical sandwich structure, wherein an insulating layer 124 is formed between a first capacitor metal layer 126 and a second capacitor metal layer 128. Each of an interface between the first capacitor metal layer 126 and the insulating layer 124 and an interface between the second capacitor metal layer 128 and the insulating layer 124 substantially extends in a vertical (e.g., z-axis) direction. In various embodiments, a vertical metal-insulator-metal capacitor having the same surface area may provide a higher capacitance than a horizontal metal-insulator-metal capacitor.
[0082] In various embodiments, the first capacitor metal layer 126 and the second capacitor metal layer 128 are composed of a metal such as copper (Cu), and the insulating layer 124 is composed of a high permittivity (high-K) dielectric material (e.g., a relative permittivity greater than about 3). The high-K dielectric material used and described in the present disclosure includes a dielectric material having a high dielectric constant (e.g., greater than that of thermal silicon oxide (~3.9)). The insulating layer 124 having the high-K dielectric material can be formed by atomic layer deposition, physical vapor deposition, chemical vapor deposition, chemical oxidation, thermal oxidation, and / or other suitable methods.
[0083] In various embodiments, the metal-insulator-metal capacitor 122 includes a first electrode (e.g., a first capacitor metal layer 126), a high-K spacer (e.g., an insulating layer 124) having a first vertically extending sidewall 127 and a second vertically extending sidewall 129, and a second electrode (e.g., a second capacitor metal layer 128), wherein the first vertically extending sidewall 127 and the first electrode (e.g., the first capacitor metal layer 126) have a vertically extending interface, and the second vertically extending sidewall 129 and the second electrode (e.g., the second capacitor metal layer 128) have a vertically extending interface. In various embodiments, the high-K spacer includes silicon (Si), oxygen (O), nitrogen (N), copper (Cu), manganese (Mn), carbon (C), aluminum (Al), titanium (Ti), tantalum (Ta), hafnium oxide (HfO), hafnium dioxide (HfO2), silicon dioxide (SiO2), tantalum oxide (TaO), tantalum pentoxide (Ta2O5), aluminum oxide (AlO), aluminum oxide (Al2O3), silicon nitride (SiN), zirconium oxide (ZrO), zirconium dioxide (ZrO2) or titanium oxide (TiO). In various embodiments, the high-K spacer (e.g., insulating layer 124) includes a multi-layer structure. In various embodiments, the high-K spacer (e.g., insulating layer 124) has a thickness of about 1 nm to about 100 nm.
[0084] In various embodiments, the first conductive feature 120a (e.g., via) is connected to the first electrode (e.g., the first capacitor metal layer 126), and the second conductive feature 120b (e.g., via) is connected to the second electrode (e.g., the second capacitor metal layer 128). In this specific example, the first conductive feature 120a and the second conductive feature 120b are formed in the same interconnect layer of the interconnect structure 104. In various embodiments, the first conductive feature and the second conductive feature are formed in different interconnect layers of the interconnect structure.
[0085] Figure 2 is a process flow diagram illustrating an exemplary process 200 of forming a vertical metal-insulator-metal capacitor according to various embodiments. Figure 2 It is a combination FIG. 3A to FIG. 8B Provide explanation. Figure 3A , Figure 4A , Figure 5A , Fig. 6A , Fig. 7A , Fig. 8A and Figure 8B is a plan view (or top view) of an exemplary semiconductor structure during various stages of fabricating a vertical metal-insulator-metal capacitor according to various embodiments of an exemplary process 200 of the present disclosure, and Figure 3B , Figure 4B , Figure 5B , Figure 6B , Figure 7B and Figure 7C 2 is a cross-sectional view of an exemplary semiconductor structure during various stages of manufacturing a vertical metal-insulator-metal capacitor according to various embodiments of an exemplary process 200 disclosed herein. In some of the drawings, the element numbers of some of the illustrated elements or features are omitted to avoid obscuring other elements or features; this is for the convenience of illustrating the drawings.
[0086] The process 200 is provided for illustration only and is not intended to limit the scope of the claims expressly set forth in the present disclosure. Additional steps may be provided before, during, and after the illustrated process 200, and some of the steps described may be moved, replaced, or eliminated for other embodiments of the illustrated process 200. Additional features may be added to the semiconductor devices illustrated in the accompanying drawings, and some of the features described below may be replaced, modified, or eliminated in other embodiments of the semiconductor devices.
[0087] It should be understood that portions of the semiconductor device may be manufactured by conventional semiconductor technology process flows, and therefore some processes are only briefly described herein. Furthermore, the exemplary semiconductor device may include various other components and features, such as other types of components (e.g., additional transistors, bipolar junction transistors, resistors, capacitors, conductors, diodes, fuses, and / or other logic elements, etc.), but have been simplified for easier understanding of the concepts disclosed herein. In some embodiments, the exemplary device includes a plurality of interconnected semiconductor components (e.g., transistors) (including p-channel field effect transistors, n-channel field effect transistors, etc.). Furthermore, it should be noted that the operations of process 200, including any description with reference to the accompanying drawings, are for illustration only and are not intended to limit the scope of the claims expressly set forth below.
[0088] At block 202, the exemplary process 200 includes providing a substrate, wherein a first intermetallic dielectric layer is disposed on the substrate. Figure 3A and Figure 3B As a specific example, in an embodiment after completing block 202, a substrate is provided, which has a first intermetallic dielectric layer 302 and a second intermetallic dielectric layer 304 disposed on the substrate, and has a conductive line (such as via 306 and via 308) disposed between the substrate and the first intermetallic dielectric layer 302.
[0089] At block 204, the exemplary process 200 includes patterning the first IMD layer to expose a patterned portion of the first IMD layer surrounded by an opening in the first IMD layer. The opening extends from a top of the first IMD layer to a bottom of the first IMD layer and defines a first region where a first metal-insulator-metal capacitor terminal is formed. In various embodiments, the opening exposes a conductive element (e.g., a via) in a second IMD layer below the first IMD layer. Various layouts may be applied to the patterned portion of the first IMD layer, such as a single comb shape, a double comb shape, or a spiral shape.
[0090] See also Figure 4A and Figure 4B As a specific example, in one embodiment after block 204 is completed, the first intermetal dielectric layer 302 has an opening 402 surrounding a patterned portion 404 of the first intermetal dielectric layer 302. The opening 402 extends from a top 403 of the first intermetal dielectric layer 302 to an etch stop layer 405 at the bottom of the first intermetal dielectric layer 302, and defines a first region (patterned portion 404) of a terminal of a first metal-insulator-metal capacitor to be formed subsequently. In various embodiments, the opening 402 exposes a conductive element (e.g., via 306) in the second intermetal dielectric layer 304 below the first intermetal dielectric layer 302. Various different layout forms may be applied to the patterned portion 404 of the first intermetal dielectric layer 302, such as a single comb shape, a double comb shape, or a spiral shape. The single comb shape layout form includes a main body portion 407 and a plurality of tooth portions 409 extending parallel (or nearly parallel) toward the main body portion 407.
[0091] In various embodiments, the step of forming the opening 402 includes defining the pattern of the patterned portion 404 using a photolithography technique, and removing the material of the first IMD layer 302 around the patterned portion 404 using an isotropic etching technique to form the opening 402. In various embodiments, the photolithography technique includes forming a first patterned photoresist (PR) layer on the first IMD layer 302, patterning the first IMD layer 302 by an isotropic etching operation using the patterned photoresist layer as a mask to form the patterned portion 404, and removing the patterned photoresist layer.
[0092] At block 206, the exemplary process 200 includes forming a high-k spacer layer in the opening on the sidewalls of the first intermetallic dielectric layer facing the opening. The high-k spacer can be formed on the sidewalls using various deposition techniques, such as chemical vapor deposition techniques or physical vapor deposition techniques (e.g., sputtering). In various embodiments, the high-k spacer is composed of a high-k dielectric material, such as silicon (Si), oxygen (O), nitrogen (N), copper (Cu), manganese (Mn), carbon (C), aluminum (Al), titanium (Ti), tantalum (Ta), hafnium oxide (HfO), hafnium dioxide (HfO2), silicon dioxide (SiO2), tantalum oxide (TaO), tantalum pentoxide (Ta2O5), aluminum oxide (AlO), aluminum oxide (Al2O3), silicon nitride (SiN), zirconium oxide (ZrO), zirconium dioxide (ZrO2), or titanium oxide (TiO). In various embodiments, the high-k spacer is formed to have a thickness of 1 nm to 100 nm. In various embodiments, the relative permittivity of the high-K spacer layer is greater than about 3. Figure 5A and Figure 5B For example, in one embodiment after block 206 is completed, a high-K spacer layer 502 is formed around the sidewall of the first IMD layer 302 facing the opening 402 .
[0093] At block 208, the exemplary process 200 includes removing the inner portion of the patterned portion, leaving the high-K spacer layer. The inner portion of the patterned portion may be removed using a suitable etching technique, such as an isotropic etching and / or a dry etching technique.
[0094] At block 210, the exemplary process 200 includes forming a barrier seed layer on the high-k spacer layer and the second IMD layer. In various embodiments, the barrier seed layer is formed by an atomic layer deposition process followed by a planarization operation such as chemical mechanical polishing to remove the barrier seed layer from the surface of the first IMD layer. In various embodiments, the barrier seed layer is composed of a suitable barrier seed material, such as titanium nitride (TiN), tantalum nitride (TaN), or others.
[0095] See also Fig. 6A and Figure 6B In one embodiment, after blocks 208 and 210 are completed, the high-k spacer layer 502 is retained, and the inner portion of the patterned portion is removed. A barrier seed layer 602 is formed on the top surface of the high-k spacer layer 502 and the second intermetallic dielectric layer 304 to define a trench 604.
[0096] At block 212, an exemplary process includes filling trenches with a conductive material to form a first capacitor electrode and a second capacitor electrode. In various embodiments, the trenches are filled by depositing a metal material (e.g., copper) into the trenches. In various embodiments, the metal material is deposited by chemical vapor deposition, physical vapor deposition, and / or sputtering followed by a planarization operation such as chemical mechanical polishing.
[0097] See also Fig. 7A and Figure 7B In one embodiment after block 212 is completed, a first capacitor electrode 702 and a second capacitor electrode 704 are formed. The first capacitor electrode 702 and the second capacitor electrode 704 are separated by a thin high-K spacer layer 502. In this embodiment, the first capacitor electrode 702 is formed on a conductive feature (e.g., the first via 306), and the second capacitor electrode 704 is formed on a second conductive feature (e.g., the second via 308).
[0098] In the above embodiment, the first capacitor electrode 702 is formed on the first via 306, and the second capacitor electrode 704 is formed on the second via 308. In other embodiments, one or more of the first capacitor electrode 702 or the second capacitor electrode 704 may not be formed on a conductive feature (e.g., the first via 306 or the second via 308). In other embodiments, one or more of the first capacitor electrode 702 or the second capacitor electrode 704 may have a conductive feature formed in an intermetallic dielectric layer above the first intermetallic dielectric layer 302.
[0099] exist Figure 7C In the specific example, the first capacitor electrode 702 is not formed on the conductive feature. In this specific example, the conductive feature (such as via 732) is formed in the intermetallic dielectric layer above the first capacitor electrode 702 and connects other conductive features (such as metal layer 734 and via 736) of the interconnect structure.
[0100] Various layouts can be applied to the second capacitor electrode of the vertical MIM capacitor. Fig. 8A and Figure 8BThe semiconductor structure 800 and the semiconductor structure 820 having a vertical metal-insulator-metal capacitor according to various embodiments are illustrated, wherein the vertical metal-insulator-metal capacitor has a first capacitor electrode (first capacitor electrode 802, first capacitor electrode 822), a second capacitor electrode (second capacitor electrode 804, second capacitor electrode 824), and a high-K spacer layer (high-K spacer layer 806, high-K spacer layer 826) separating the first capacitor electrode (first capacitor electrode 802, first capacitor electrode 822) and the second capacitor electrode (second capacitor electrode 804, second capacitor electrode 824) at a vertically extending interface. The high-K spacer layer (e.g., high-K spacer layer 502, high-K spacer layer 806, high-K spacer layer 826) has a vertically extending interface with the first capacitor electrode (e.g., first capacitor electrode 702, first capacitor electrode 802, first capacitor electrode 822), and has a vertically extending interface with the second capacitor electrode (e.g., second capacitor electrode 704, second capacitor electrode 804, second capacitor electrode 824). Fig. 7A In the specific example, the second capacitor electrode 704 has a single comb shape. Fig. 8A In the specific example, the second capacitor electrode 804 has a double comb shape. The double comb shape layout includes a main body portion 808 and a plurality of tooth portions 810 extending parallel (or almost parallel) toward the main body portion 808. Figure 8B In the specific example, the second capacitor electrode 824 has a spiral shape. In other specific examples, other shapes of the second capacitor electrode can be considered.
[0101] In block 214, the exemplary process 200 includes performing further process operations. The semiconductor device may be further processed to form various features and regions known in the art. For example, subsequent processes may form various contacts / vias / lines and multi-layer interconnect features (such as metal layers and interlayer dielectrics) on the substrate, configured to connect various features to form functional circuits. In further embodiments, the multi-layer interconnects may be vertical interconnects (such as vias or contacts) and horizontal interconnects (such as metal lines). Various conductive materials may be used for the various interconnect features, such as copper, tungsten and / or silicide. In one embodiment, damascene and / or dual damascene processes are used to form copper-related multi-layer interconnect structures. Furthermore, additional process steps may be performed before, during, and after the process 200, and some of the above process steps may be replaced or eliminated according to various embodiments of the process 200.
[0102] Fig. 9is a flow chart illustrating an exemplary process 900 for forming a semiconductor device having a vertical metal-insulator-metal capacitor according to various embodiments. The process 900 is provided for illustration only and is not intended to limit the scope of the claims expressly set forth herein. Additional steps may be provided before, during, and after the exemplary process 900, and some of the steps described may be moved, replaced, or eliminated for other embodiments of the exemplary process 900. Additional features may be added to the semiconductor devices illustrated in the accompanying drawings, and some of the features described below may be replaced, modified, or eliminated in other embodiments of the semiconductor device.
[0103] It should be understood that portions of the semiconductor device may be manufactured using conventional semiconductor technology process flows, and therefore some processes are only briefly described herein. Furthermore, the exemplary semiconductor device may include various other components and features, such as other types of components (e.g., additional transistors, bipolar junction transistors, resistors, capacitors, conductors, diodes, fuses, and / or other logic elements, etc.), but have been simplified for easier understanding of the concepts disclosed herein. In some embodiments, the exemplary device includes a plurality of interconnected semiconductor components (e.g., transistors) (including p-channel field effect transistors, n-channel field effect transistors, etc.). Furthermore, it should be noted that the operations of process 900, including any description with reference to the accompanying drawings, are intended to be illustrative only and are not intended to limit the scope of the claims expressly set forth below.
[0104] In step 910, the exemplary process 900 includes forming a device including a source, a drain, and a gate on a substrate. In various embodiments, the device includes a fin field-effect transistor (FinFET), a gate-all-around (GAA) device, a nanosheet device, a 2D material device, a planar device, a back-end of line (BEOL) device, a NAND flash memory, a 3D NAND flash memory, an N-type metal oxide semiconductor, a P-type metal oxide semiconductor, and / or a complementary field effect transistor (CFET). In various embodiments, the device is electrically connected to an amplifier, a filter, or a memory device.
[0105] In step 920, the exemplary process 900 includes forming a multi-layer interconnect structure configured to provide source, drain and gate electrical connections, wherein the multi-layer interconnect structure has multiple layers of different heights. In various embodiments, the gate dielectric material of the gate includes hafnium oxide (HfO), hafnium dioxide (HfO2), silicon dioxide (SiO2), tantalum oxide (TaO), tantalum pentoxide (Ta2O5), aluminum oxide (AlO), aluminum oxide (Al2O3), silicon nitride (SiN), zirconium oxide (ZrO), zirconium dioxide (ZrO2) or titanium oxide (TiO). In various embodiments, the interconnect structure includes one or more trenches. In various embodiments, the conductive features fill the trenches of the interconnect structure. In various embodiments, the conductive features include cobalt (Co), titanium (Ti), titanium nitride (TiN), tungsten (W), copper (Cu), aluminum (Al), gallium (Ga), zinc (Zn), ruthenium (Ru), molybdenum (Mo), indium tix oxide (ITO) and / or metal compounds.
[0106] In step 930, the exemplary process 900 includes forming a metal-insulator-metal capacitor in an interconnect structure, the metal-insulator-metal capacitor including a first electrode, a high-k spacer having a first vertically extending sidewall and a second vertically extending sidewall, and a second electrode, wherein the first vertically extending sidewall has a vertically extending interface with the first electrode, and the second vertically extending sidewall has a vertically extending interface with the second electrode. In various embodiments, the high-k spacer includes silicon (Si), oxygen (O), nitrogen (N), copper (Cu), manganese (Mn), carbon (C), aluminum (Al), titanium (Ti), tantalum (Ta), hafnium oxide (HfO), hafnium dioxide (HfO2), silicon dioxide (SiO2), tantalum oxide (TaO), tantalum pentoxide (Ta2O5), aluminum oxide (AlO), aluminum oxide (Al2O3), silicon nitride (SiN), zirconium oxide (ZrO), zirconium dioxide (ZrO2), or titanium oxide (TiO). In various embodiments, the high-k spacer includes a multilayer structure. In various embodiments, the high-K spacer has a thickness of about 1 nm to about 100 nm.
[0107] In step 940, exemplary process 900 includes forming a first conductive feature connecting the first electrode, and in step 950, exemplary process 900 includes forming a second conductive feature connecting the second electrode. In various embodiments, the first conductive feature and the second conductive feature are formed in different layers in the interconnect structure.
[0108] In some embodiments, the technology described in the present disclosure is related to a manufacturing method, which includes: forming a transistor on a substrate, wherein the transistor includes a source, a drain and a gate; forming a multi-layer interconnect structure, wherein the multi-layer interconnect structure is configured to provide electrical connection between the source, the drain and the gate, and the multi-layer interconnect structure has multiple interconnect layers; and forming a metal-insulator-metal capacitor in the multi-layer interconnect structure, wherein the metal-insulator-metal capacitor includes a first electrode, a high-K spacer and a second electrode, the high-K spacer has a first vertically extending sidewall and a second vertically extending sidewall, the first vertically extending sidewall has a vertically extending interface with the first electrode, and the second vertically extending sidewall has a vertically extending interface with the second electrode.
[0109] In some embodiments, the technology described in the present disclosure relates to a manufacturing method, which further includes: forming a first conductive feature, wherein the first conductive feature is connected to a first electrode; and forming a second conductive feature, wherein the second conductive feature is connected to a second electrode, and the steps of forming the first conductive feature and the second conductive feature include forming the first conductive feature and the second conductive feature in different internal connection layers in a multi-layer internal connection structure.
[0110] In some embodiments, the technology described in the present disclosure relates to a manufacturing method, which further includes: forming a first conductive feature, wherein the first conductive feature is connected to a first electrode; and forming a second conductive feature, wherein the second conductive feature is connected to a second electrode, and the steps of forming the first conductive feature and the second conductive feature include forming the first conductive feature and the second conductive feature in the same internal connection layer in a multi-layer internal connection structure.
[0111] In some aspects, the technology described herein is directed to a method of forming a metal-insulator-metal capacitor, wherein forming a first electrode, a high-K spacer, and a second electrode in a same interconnect layer in a multi-layer interconnect structure.
[0112] In some embodiments, the technology described in the present disclosure is related to a manufacturing method, wherein forming a metal-insulator-metal capacitor includes: patterning a first intermetallic dielectric layer of a multi-layer interconnect structure to define a patterned portion of the first intermetallic dielectric layer surrounded by an opening in the first intermetallic dielectric layer; forming a high-K spacer in the opening on the sidewall of the first intermetallic dielectric layer facing the opening; removing an inner portion of the patterned portion while retaining the high-K spacer; forming a barrier seed layer on the high-K spacer and an exposed portion of a second intermetallic dielectric layer, wherein the second intermetallic dielectric layer is below the first intermetallic dielectric layer; and forming a first electrode and a second electrode in the first intermetallic dielectric layer on the exposed portion of the second intermetallic dielectric layer.
[0113] In some aspects, the technology described herein is directed to a manufacturing method, wherein the second electrode has a similar shape to the patterned portion of the first IMD layer.
[0114] In some embodiments, the technology described in the present disclosure is related to a semiconductor device, which includes: a transistor on a substrate, wherein the transistor includes a source, a drain and a gate; a multi-layer interconnect structure on the substrate, wherein the multi-layer interconnect structure is configured to provide electrical connections between the source, the drain and the gate, and the multi-layer interconnect structure has multiple interconnect layers; a metal-insulator-metal capacitor in the multi-layer interconnect structure, wherein the metal-insulator-metal capacitor includes a first electrode, a high-K spacer and a second electrode, and the first electrode, the high-K spacer and the second electrode are all formed in the same layer of the multi-layer interconnect structure; a first conductive feature connected to the first electrode; and a second conductive feature connected to the second electrode.
[0115] In some aspects, the technology described in the present disclosure is related to a semiconductor device, wherein the high-K spacer has a first vertically extending sidewall and a second vertically extending sidewall, the first vertically extending sidewall and the first electrode have a vertically extending interface, and the second vertically extending sidewall and the second electrode have a vertically extending interface.
[0116] In some aspects, the technology described herein is directed to a semiconductor device, wherein a first conductive feature and a second conductive feature are formed in different interconnect layers in a multi-layer interconnect structure.
[0117] In some aspects, the technology described herein is directed to a semiconductor device wherein a first conductive feature and a second conductive feature are formed in a same interconnect layer in a multi-layer interconnect structure.
[0118] In some aspects, the technology described in the present disclosure is related to a semiconductor device, wherein the second electrode has a single comb-shaped appearance, the single comb-shaped appearance has a main body portion and a plurality of tooth portions, and the tooth portions extend outward from the main body portion in parallel on one side of the main body portion.
[0119] In some aspects, the technology described in the present disclosure is related to a semiconductor device, wherein the second electrode has a double-comb shape, the double-comb shape has a main body portion and a plurality of tooth portions, and the tooth portions extend outward from the main body portion in parallel on both sides of the main body portion.
[0120] In some aspects, the technology described herein is directed to a semiconductor device, wherein the second electrode has a spiral shape.
[0121] In some embodiments, the technology disclosed herein is related to a manufacturing method, which includes: providing a substrate, wherein the substrate has a multi-layer interconnect structure, and the multi-layer interconnect structure is provided with a first intermetallic dielectric layer and a second intermetallic dielectric layer; patterning the first intermetallic dielectric layer of the multi-layer interconnect structure to define a patterned portion of the first intermetallic dielectric layer, wherein the patterned portion is surrounded by an opening in the first intermetallic dielectric layer; forming a high-K spacer in the opening on the sidewall of the first intermetallic dielectric layer facing the opening; removing an inner portion of the patterned portion while retaining the high-K spacer; forming a barrier seed layer on the high-K spacer and an exposed portion of the second intermetallic dielectric layer, wherein the second intermetallic dielectric layer is below the first intermetallic dielectric layer; and forming a first electrode and a second electrode in the first intermetallic dielectric layer on the exposed portion of the second intermetallic dielectric layer.
[0122] In some embodiments, the technology described in the present disclosure relates to a manufacturing method, which further includes: forming a first conductive feature, wherein the first conductive feature is connected to a first electrode; and forming a second conductive feature, wherein the second conductive feature is connected to a second electrode, and the first conductive feature and the second conductive feature are formed in different layers in a multi-layer interconnect structure.
[0123] In some embodiments, the technology described in the present disclosure relates to a manufacturing method, which further includes: forming a first conductive feature, wherein the first conductive feature is connected to a first electrode; and forming a second conductive feature, wherein the second conductive feature is connected to a second electrode, and the first conductive feature and the second conductive feature are formed in the same layer in a multi-layer interconnect structure.
[0124] In some aspects, the technology described herein is directed to a manufacturing method, wherein the second electrode has a similar shape to the patterned portion of the first IMD layer.
[0125] In some aspects, the technology described in the present disclosure is related to a manufacturing method, wherein the second electrode has a single comb-shaped appearance, the single comb-shaped appearance has a main body portion and a plurality of tooth portions, and the tooth portions extend outward from the main body portion in parallel on one side of the main body portion.
[0126] In some aspects, the technology described in the present disclosure is related to a manufacturing method, wherein the second electrode has a double-comb shape, the double-comb shape has a main body portion and a plurality of tooth portions, and the tooth portions extend outward from the main body portion in parallel on both sides of the main body portion.
[0127] In some aspects, the technology described herein is directed to a manufacturing method, wherein the second electrode has a spiral shape.
[0128] In some embodiments, the technology described in the present disclosure is related to a manufacturing method, which includes: forming a transistor on a substrate, wherein the transistor includes a source, a drain and a gate; forming a multi-layer interconnect structure, wherein the multi-layer interconnect structure is configured to provide electrical connections between the source, the drain and the gate, and the multi-layer interconnect structure has multiple layers with different heights; forming a comb-like feature in the interconnect structure; forming a high-K insulating feature on the sidewall of the comb-like feature; removing an inner portion of the comb-like feature while retaining the high-K insulating feature; forming a barrier seed layer on the high-K insulating feature; filling a conductive feature on the barrier seed layer; performing a chemical mechanical polishing operation on the conductive feature to form a first conductive feature, a high-K insulating feature and a second conductive feature.
[0129] In some embodiments, the technology disclosed herein is related to a manufacturing method, which includes: forming a transistor on a substrate, wherein the transistor includes a source, a drain and a gate; forming a multi-layer interconnect structure, wherein the multi-layer interconnect structure is configured to provide electrical connection between the source, the drain and the gate, and the multi-layer interconnect structure has multiple interconnect layers; forming a metal-insulator-metal capacitor in the multi-layer interconnect structure, wherein the metal-insulator-metal capacitor includes a first electrode, a high-K spacer and a second electrode, the high-K spacer has a first vertically extending sidewall and a second vertically extending sidewall, the first vertically extending sidewall has a vertically extending interface with the first electrode, and the second vertically extending sidewall has a vertically extending interface with the second electrode; forming a first conductive feature connected to the first electrode; and forming a second conductive feature connected to the second electrode, and the first conductive feature and the second conductive feature are in the same interconnect layer.
[0130] In some aspects, the technology disclosed herein relates to a semiconductor device comprising: a substrate; a transistor on the substrate, wherein the transistor comprises a source, a drain and a gate; a multi-layer interconnect structure, wherein the multi-layer interconnect structure is configured to provide electrical connection between the source, the drain and the gate, and the multi-layer interconnect structure has multiple interconnect layers; and a metal-insulator-metal capacitor in the multi-layer interconnect structure, wherein the metal-insulator-metal capacitor comprises a first electrode, a high-K spacer and a second electrode, the high-K spacer having a first vertically extending sidewall and a second vertically extending sidewall, the first vertically extending sidewall having a vertically extending interface with the first electrode, and the second vertically extending sidewall having a vertically extending interface with the second electrode.
[0131] In some embodiments, the technology described in the present disclosure relates to a semiconductor device, which further includes: a first conductive feature, wherein the first conductive feature is connected to a first electrode; and a second conductive feature, wherein the second conductive feature is connected to a second electrode, and the first conductive feature and the second conductive feature are in different ones of the interconnect layers in the multi-layer interconnect structure.
[0132] In some embodiments, the technology described in the present disclosure relates to a semiconductor device, which further includes: a first conductive feature, wherein the first conductive feature is connected to a first electrode; and a second conductive feature, wherein the second conductive feature is connected to a second electrode, and the first conductive feature and the second conductive feature are in the same interconnect layer in a multi-layer interconnect structure.
[0133] In some aspects, the technology disclosed herein is directed to a semiconductor device comprising: a multi-layer interconnect structure, wherein the multi-layer interconnect structure has a first inter-metal dielectric layer and a second inter-metal dielectric layer; a metal-insulator-metal capacitor in the first inter-metal dielectric layer, wherein the metal-insulator-metal capacitor comprises: an insulating layer having a first vertically extending sidewall and a second vertically extending sidewall; a first capacitor electrode adjacent to the first vertically extending sidewall of the insulating layer; and a second capacitor electrode adjacent to the second vertically extending sidewall of the insulating layer, wherein the insulating layer is located between the first capacitor electrode and the second capacitor electrode, and each of an interface between the first capacitor electrode and the insulating layer and an interface between the second capacitor electrode and the insulating layer extends in a vertical direction; a first conductive feature located in the multi-layer interconnect structure, wherein the first conductive feature is connected to the first capacitor electrode; and a second conductive feature located in the multi-layer interconnect structure, wherein the second conductive feature is connected to the second capacitor electrode.
[0134] In some aspects, the technology described in the present disclosure is directed to a semiconductor device, wherein the second capacitor electrode has a single comb shape, a double comb shape, or a spiral shape.
[0135] At least one exemplary embodiment has been presented in the above detailed description of the present disclosure, and it should be understood that there are many variations. It should also be understood that the one or more embodiments described are merely illustrative and are not intended to limit the scope, applicability, or configuration of the present disclosure in any way. Instead, the above detailed description provides instructions for implementing the exemplary embodiments of the present disclosure by one of ordinary skill in the art. It should be understood that various changes to the functions and configurations of the elements of the exemplary embodiments described do not depart from the scope of the claims attached to the present disclosure.
Claims
1. A semiconductor device, characterized in that: Include: a substrate; a transistor on the substrate, wherein the transistor comprises a source, a drain and a gate; a multi-layer interconnect structure, wherein the multi-layer interconnect structure is configured to provide electrical connection between the source, the drain and the gate, and the multi-layer interconnect structure has a plurality of interconnect layers; as well as A metal-insulator-metal (MIM) capacitor, in the multi-layer interconnect structure, wherein the metal-insulator-metal capacitor includes a first electrode, a high-K spacer and a second electrode, the high-K spacer has a first vertically extending sidewall and a second vertically extending sidewall, the first vertically extending sidewall and the first electrode have a vertically extending interface, and the second vertically extending sidewall and the second electrode have a vertically extending interface.
2. The semiconductor device according to claim 1, wherein Also includes: a first conductive feature, wherein the first conductive feature is connected to the first electrode; and a second conductive feature, wherein the second conductive feature is connected to the second electrode, and the first conductive feature and the second conductive feature are in different ones of the plurality of interconnect layers in the multi-layer interconnect structure.
3. The semiconductor device according to claim 1, wherein: Also includes: a first conductive feature, wherein the first conductive feature is connected to the first electrode; and a second conductive feature, wherein the second conductive feature is connected to the second electrode, and the first conductive feature and the second conductive feature are in a same one of the plurality of interconnect layers in the multi-layer interconnect structure.
4. A semiconductor device, characterized in that: Include: A transistor on a substrate, wherein the transistor comprises a source, a drain and a gate; a multi-layer interconnect structure on the substrate, wherein the multi-layer interconnect structure is configured to provide electrical connection between the source, the drain and the gate, and the multi-layer interconnect structure has a plurality of interconnect layers; a metal-insulator-metal capacitor in the multi-layer interconnect structure, wherein the metal-insulator-metal capacitor comprises a first electrode, a high-K spacer and a second electrode, and the first electrode, the high-K spacer and the second electrode are all formed in a same layer of the multi-layer interconnect structure; a first conductive feature connected to the first electrode; and A second conductive feature is connected to the second electrode.
5. The semiconductor device according to claim 4, wherein: The high-K spacer has a first vertically extending sidewall and a second vertically extending sidewall. The first vertically extending sidewall and the first electrode have a vertically extending interface, and the second vertically extending sidewall and the second electrode have a vertically extending interface.
6. The semiconductor device according to claim 4 or 5, characterized in that The second electrode has a single comb shape, which has a main body and a plurality of tooth-shaped parts, and the plurality of tooth-shaped parts extend outwards in parallel from the main body on one side of the main body.
7. The semiconductor device according to claim 4 or 5, characterized in that The second electrode has a double comb shape, which has a main body and a plurality of tooth parts, and the plurality of tooth parts extend outwards in parallel from the main body on both sides of the main body.
8. The semiconductor device according to claim 4 or 5, wherein: The second electrode has a spiral shape.
9. A semiconductor device, characterized in that: Include: A multi-layer interconnect structure, wherein the multi-layer interconnect structure comprises a first inter-metal dielectric layer and a second inter-metal dielectric layer; a metal-insulator-metal capacitor in the first intermetal dielectric layer, wherein the metal-insulator-metal capacitor comprises: An insulating layer having a first vertically extending sidewall and a second vertically extending sidewall; a first capacitor electrode adjacent to the first vertically extending sidewall of the insulating layer; and a second capacitor electrode adjacent to the second vertically extending sidewall of the insulating layer, wherein the insulating layer is located between the first capacitor electrode and the second capacitor electrode, and each of an interface between the first capacitor electrode and the insulating layer and an interface between the second capacitor electrode and the insulating layer extends in a vertical direction; a first conductive feature located in the multi-layer interconnect structure, wherein the first conductive feature is connected to the first capacitor electrode; and A second conductive feature is located in the multi-layer interconnect structure, wherein the second conductive feature is connected to the second capacitor electrode.
10. The semiconductor device according to claim 9, wherein: The second capacitor electrode has a single comb shape, a double comb shape or a spiral shape.