Low stress deformation power device with thick weldable metal layer

Abstract

The utility model discloses a low-stress deformation power device with a thick weldable metal layer, relates to a power semiconductor device, and aims to reduce deformation caused by stress by optimizing the arrangement mode, materials and the like of the weldable metal layer and / or a semiconductor groove so as to eliminate or release the stress and eliminate the occurrence of poor warping. The technical scheme provided by the utility model is beneficial to reducing the surface stress of the weldable metal layer and relieving wafer warping caused by the weldable metal layer of thick metal, thereby avoiding the process problem caused by wafer warping and being beneficial to the reliability of a device.

Description

Technical Field

[0001] The utility model relates to a power semiconductor device, in particular to a low stress deformation power device with a weldable metal layer. Background Art

[0002] In high current and high power applications, power devices are required to have good heat dissipation performance and reliability. In order to further reduce the size of the device, enhance the heat dissipation performance of the device and reduce the package resistance, an existing surface mount (SMT) package using copper sheet bonding is Figure 1 1A is shown in the cross-sectional view. The upper end of the power device chip 130 has an upper copper sheet 133, which is connected together by solder 131 and connected to the pin 135. The lower end of the power device chip 130 is connected to the bottom copper frame 134 by solder 131. When the device is working, a large current passes through the upper copper sheet 133, the power device chip 130 and the bottom copper frame 134. The upper copper sheet 133 and the bottom copper frame 134 can provide good heat dissipation and low on-resistance for the chip.

[0003] The structure of the power device chip 130 is as follows: Figure 1 As shown in the cross-sectional view in Figure 1B, it includes a bottom metal layer 101 located at the bottom, a semiconductor layer 100 above the bottom metal layer, an upper surface metal layer 106 on the semiconductor layer 100, and a traditional solderable metal layer 102 above the upper surface metal layer 106. In addition, it also includes a passivation layer 104 located at the periphery of the device, surrounding or separating the upper surface metal layer 106. In this structure, usually, the upper surface metal layer 106 is composed of an aluminum alloy or an aluminum-copper alloy, and the traditional solderable metal layer 102 is usually an alloy layer of titanium, nickel, palladium, gold, silver, copper, etc. In some existing device chip structures, a thicker metal layer, such as electroplated copper alloy, copper-nickel alloy, copper-tantalum alloy, etc., is preferably used as the traditional solderable metal layer 102. The solderable metal layer formed by the thick metal is conducive to heat dissipation, reducing on-resistance and improving the reliability of the device.

[0004] However, in the above structure, the solderable metal layer formed by thick metal (greater than 3um) will generate greater stress on the upper surface. In order to increase the welding area, the traditional solderable metal layer 102 occupies a larger area of ​​the power device chip 130 (the large area on the left side of the figure is used for source metal, and the right side is used for gate metal. Large current generally passes through the bottom drain to the source), usually more than 50%. Therefore, the area of ​​the traditional solderable metal layer 102 on the entire wafer 140 accounts for a large proportion, as shown in the schematic diagram 1C. In the device manufacturing process after the traditional solderable metal layer 102 is formed, the wafer 140 will produce more serious warping during the thermal process due to the stress of the traditional solderable metal layer 102, such as Figure 1As shown in Figure 1D, wafer warpage will affect subsequent thinning, slicing and other process steps. Large stress on the upper surface is also not conducive to device reliability.

[0005] In addition, common power devices such as MOSFET, IGBT, etc. may have a periodically arranged semiconductor trench structure 143 above the semiconductor layer in the chip. The semiconductor trench structure 143 may be filled with materials such as oxides, nitrides, metals, polysilicon, etc. Due to the difference in thermal expansion coefficients between the above materials and the semiconductor, the semiconductor trench located on the upper surface of the semiconductor generates horizontal contraction or expansion stress on the semiconductor, thereby causing the entire wafer 140 to warp.

[0006] The above-mentioned wafer warping direction depends on the material and structure in the semiconductor groove. Generally, the wafer warping direction at room temperature is perpendicular to the extension direction of the periodic semiconductor groove 143. An example is shown in 2A and 2B, in which the wafer 140 has dense periodic semiconductor grooves 143 arranged along the Y direction, thereby causing the wafer to warp in the X direction. Utility Model Content

[0007] In order to solve the above-mentioned warping problem, the utility model provides a low stress deformation power device with a weldable metal layer, the power device includes a bottom metal layer, a semiconductor layer is arranged above the bottom metal layer, an upper surface metal layer is arranged above the semiconductor layer, the semiconductor layer has a semiconductor device structure, the semiconductor device structure has periodically arranged semiconductor grooves, and more than two weldable metal units are arranged on the upper surface metal layer, wherein an insulating layer is arranged between the weldable metal units for welding gate metal and source metal, the weldable metal unit is composed of one or more patterned weldable metal layers, and a stress release layer for releasing the surface stress of adjacent weldable metal units is arranged between the weldable metal units.

[0008] Among them, the insulating stress release layer is lower than the solderable metal layer and is covered by the solderable metal layer; or the metal stress release layer is lower than the solderable metal layer; or the metal stress release layer is lower than the solderable metal layer and is covered by the solderable metal layer.

[0009] Wherein, a stress release layer for absorbing the adjacent solderable metal layers is also provided between the solderable metal layers.

[0010] Wherein, the weldable metal unit is composed of a plurality of weldable metal layers, the weldable metal layers constituting each weldable metal unit have the same shape and the spacing between adjacent weldable metal layers is equal.

[0011] Furthermore, the weldable metal unit and the semiconductor groove are both uniformly arranged in a direction, the weldable metal unit generates a first directional stress, and the semiconductor groove generates a second directional stress, and the directions of the first stress and the second stress are perpendicular.

[0012] Furthermore, the weldable metal layer constituting the weldable metal unit is polygonal, circular, elliptical or a combination of the above shapes, and the magnitude of the first stress is adjusted by combining different shapes so that it is equivalent to the magnitude of the second stress.

[0013] Furthermore, the semiconductor trenches and the solderable metal units are arranged in different directions in different regions within the semiconductor, and the solderable metal units and the semiconductor trenches in the same region are arranged in directions perpendicular to each other.

[0014] Furthermore, a bottom solderable metal layer is provided below the bottom metal layer, and the bottom solderable metal layer and the solderable metal layer are made of the same material.

[0015] The beneficial effect of the utility model is that the utility model proposes a power device structure with a thick metal solderable metal layer (greater than 3um), which is beneficial to reducing the surface stress of the solderable metal layer, alleviating the wafer warping caused by the thick metal solderable metal layer, thereby avoiding process problems caused by wafer warping, and is beneficial to the reliability of the device. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figure 1 The present invention is a schematic diagram of an existing power device structure with a thick solderable metal layer and its wafer warping.

[0017] Figure 2 The figure is a schematic diagram of an existing semiconductor trench structure of a power device and its wafer warping.

[0018] Figure 3 3A is a schematic diagram of the structure of the device structure of the first embodiment of the utility model, wherein 3A is a top view and 3B is a cross-sectional view.

[0019] Figure 4 Schematic diagram of groove arrangement and solderable metal layer arrangement in another embodiment, wherein 4A is a schematic diagram of the semiconductor groove direction of the wafer; 4B is a schematic diagram of the structure of the solderable metal layer on the chip in the embodiment in 4A.

[0020] Figure 5 These are some other exemplary patterns of different patterned solderable metal layers of the present invention.

[0021] Figure 66A is a schematic diagram of the structure of the semiconductor trench and the first solderable metal layer in another embodiment, wherein 6A is a schematic diagram of the structure of the semiconductor trench 143 in the chip, and 6B is a schematic diagram of the structure of the patterned first solderable metal layer 202 on the upper surface of the chip of the embodiment shown in 6A.

[0022] Figure 7 Schematic diagram of chip cross-section according to different implementation modes of the present invention.

[0023] Figure 8 8A is a schematic diagram of another embodiment of the present invention, wherein 8A is a top view of the chip, and 8B and 8C are schematic cross-sectional views of the chip in different embodiments corresponding to 8A.

[0024] Fig. 9 This is a top view of a chip structure according to another embodiment of the present invention. DETAILED DESCRIPTION

[0025] The relevant technical background is explained below. First, it should be pointed out that the corresponding position words described in this document, such as "upper", "lower", "left", "right", "front", "back", "vertical", "horizontal", and "vertical" correspond to the relative positions of the reference diagrams. In the specific implementation, there is no restriction on the fixed direction. Second, it should be pointed out that the devices in the drawings are not necessarily drawn to a specific scale. The straight lines shown as the boundaries of the doped regions, grooves, and material layers in the drawings, as well as the sharp angles formed by the boundaries, are generally not straight lines and precise angles in actual applications.

[0026] The present invention is described in detail below in conjunction with the accompanying drawings and embodiments.

[0027] The device structure of the first embodiment of the utility model is as follows: Figure 3 As shown, 3A is a top view of an exemplary structure of a power semiconductor device chip, and 3B is a cross-sectional schematic diagram of the structure. The structure includes:

[0028] An upper surface metal layer 106 located on the semiconductor layer 100;

[0029] A plurality of (more than 4) patterned solderable metal layers are located above the upper surface metal layer 106, and the solderable metal layers respectively include a first solderable metal layer 202 and a second solderable metal layer 203 that are insulated from each other; taking 3A as an example, the first solderable metal layer 202 for soldering the source metal and the second solderable metal layer 203 for soldering the gate metal are insulated from each other.

[0030] The embodiment of the present case takes the first solderable metal layer 202 as the research object. If necessary, the second solderable metal layer 203 can also adopt the same method to reduce the occurrence of warpage.

[0031] A plurality of insulating stress relief layers 204 are disposed between the plurality of patterned solderable metal layers.

[0032] Furthermore, a bottom metal layer 101 at the bottom of the semiconductor layer 100 may be included.

[0033] The upper surface of the semiconductor layer 100 has a semiconductor device structure, such as MOSFET, IGBT, HEMT, diode, etc. The semiconductor layer 100 may be composed of a single semiconductor material, such as silicon, silicon carbide, gallium nitride, gallium oxide, etc., or may be composed of multiple materials, such as gallium nitride on the top and silicon on the bottom. Typically, the thickness of the semiconductor layer 100 is between 20-300um.

[0034] The material of the upper surface metal layer 106 is usually made of aluminum, and may also include titanium, nickel, tungsten, copper, etc., and its thickness is usually 3-5um. In one embodiment, the upper surface metal layer 106 is an aluminum-copper alloy with a thickness of 4um.

[0035] The material of the patterned first solderable metal layer 202 may be pure copper, copper-titanium alloy, copper-nickel alloy, copper-tantalum alloy, and its thickness may be between 2um-30um. In one embodiment, the patterned first solderable metal layer 202 is composed of pure copper and has a thickness of 5um. In another embodiment, the patterned first solderable metal layer 202 is composed of copper-titanium and has a thickness of 20um. Typically, the formation step of the patterned first solderable metal layer 202 includes a one-step electroplating process. Typically, the minimum line width of the pattern of the patterned first solderable metal layer 202 is between 50um and 1500um.

[0036] The insulating stress release layer 204 serves to release the stress generated by the adjacent patterned first solderable metal layer 202. The insulating stress release layer 204 is composed of a low hardness material, and its constituent material may be an organic polymer, such as benzocyclobutene (BCB), polyimide, epoxy, etc. The thickness of the insulating stress release layer 204 is usually between 3-20um, and the width is usually greater than 10um. In one embodiment, the insulating stress release layer 204 is composed of polyimide and has a thickness of 5-10um. In one embodiment, the insulating stress release layer 204 is composed of benzocyclobutene and has a thickness of 5-30um.

[0037] The insulating stress release layer 204 can absorb the surface stress between adjacent patterned first solderable metal layers 202, thus facilitating reduction of wafer warpage.

[0038] On the basis of the above embodiment, further, the features of another embodiment of the utility model are as follows:

[0039] The patterned first solderable metal layer 202 has a directional pattern and generates directional stress on the horizontal plane of the solderable metal layer, and the direction of the stress is perpendicular to the horizontal stress direction generated by the trench structure in the semiconductor 100 below.

[0040] An exemplary practical embodiment is shown in the figure, where 4A is a schematic diagram of the structure of a semiconductor trench in a wafer, and 4B is a schematic diagram of the structure of a solderable metal layer on a chip in the wafer.

[0041] Generally, the stress direction generated in the horizontal direction of the periodically arranged semiconductor trench structure in the semiconductor 100 is perpendicular to the trench direction, and causes the entire wafer to warp in this direction. As shown in 4A, the semiconductor trenches 143 are uniformly arranged along the Y direction. During the thermal process, the structure generates a large horizontal stress in the X direction, so the wafer tends to warp in the X direction.

[0042] As shown in 4B, since the patterned first solderable metal layer 202 is in the shape of a long strip and is evenly arranged in the X direction, in the X direction, there is an insulating stress release layer 204 between each patterned first solderable metal layer 202, so the surface stress in this direction is less, and a large horizontal stress is mainly generated in the Y direction. Therefore, during the wafer processing process, the wafer tends to form a warp in the Y direction.

[0043] The directions of the above two horizontal stresses (X and Y) are perpendicular to each other. Due to the rigidity of the material, the wafer warpage can be minimized. At the same time, it can also alleviate the delamination caused by the opposite warping of the two material layers in the wafer in the same direction during the thermal process.

[0044] In the above exemplary embodiment, the stress direction (X direction) generated by the semiconductor groove 143 in the wafer is perpendicular to the direction of the groove (Y direction). In fact, the stress direction depends on multiple factors such as the groove structure, the filling material in the groove, and the thermal process. The stress direction generated by the semiconductor groove 143 may also be along the direction of the semiconductor groove 143 (Y direction), causing the wafer to tend to warp in the Y direction. Therefore, in practical applications, those skilled in the art can adjust the structure and pattern of the patterned first solderable metal layer 202 according to the corresponding designed stress direction and the actual wafer warping situation, increase stress in the appropriate direction, and achieve the purpose of reducing wafer warping.

[0045] In addition to the patterned first solderable metal layer 202 structure shown in 4B, other directional patterns can be used to change the stress direction of the first solderable metal layer 202 to achieve the purpose of the present invention. Some exemplary patterns of the patterned first solderable metal layer 202 are as follows: Figure 5 As shown in the implementation method.

[0046] An embodiment is shown in Figure 5A, in which the patterned first solderable metal layer 202 is a plurality of rectangles of different lengths and widths, and different rectangles form a solderable metal unit (depicted by a dotted frame), the length (X direction) of the rectangle in the solderable metal unit is longer than the width (Y direction), and the spacing between the rectangles in the solderable metal unit is equal in the X direction and the Y direction, and the stress generated between the solderable metal units and the stress generated by the groove are perpendicular to each other.

[0047] Another embodiment is shown in 5B, in which the patterned first solderable metal layer 202 is a plurality of irregular polygons, and different irregular polygons form a solderable metal unit (depicted by a dotted box). The total side length of the series of polygons in the X direction is longer than the total side length in the Y direction, and the spacing between the polygons in the solderable metal unit is equal in both the X direction and the Y direction.

[0048] Another embodiment is shown in 5C, in which the patterned first solderable metal layer 202 is a series of identical circles, ellipses or regular polygons, and different irregular polygons form a solderable metal unit (depicted by the dotted box), and the spacing between the series of shapes in the X direction is shorter than the spacing in the Y direction.

[0049] The above exemplary embodiment patterns can make the stress of the patterned first solderable metal layer 202 in the X direction greater than that in the Y direction, and make the wafer tend to produce directional warping, so that the purpose of the utility model can be achieved with appropriate groove direction design.

[0050] In order to further reduce the wafer warpage, in some embodiments, grooves in different directions may be arranged in different areas on the wafer or chip to disperse the stress direction of the grooves in the horizontal direction of the wafer. Accordingly, those skilled in the art can achieve the purpose of the utility model by changing the graphic layout of the graphic first solderable metal layer 202. An exemplary embodiment is as follows: Figure 6 As shown, 6A is a schematic diagram of the structure of a semiconductor trench 143 in a chip, and 6B is a schematic diagram of the structure of a patterned first solderable metal layer 202 on the upper surface of the chip.

[0051] The semiconductor trench 143 in the chip is divided into a plurality of X-direction trench regions and Y-direction trench regions according to the trench direction. Among them, stresses in two directions, the Y direction and the X direction, are generated in the two different regions. According to the semiconductor trench structure, correspondingly, above the trench direction region along the X direction, there is a patterned first solderable metal layer 202 with long strips arranged parallel to each other along the Y direction, and stress is generated in the X direction; above the trench direction region along the Y direction, there is a patterned first solderable metal layer 202 with long strips arranged parallel to each other along the X direction, and stress is generated in the Y direction.

[0052] In the chip, the stress directions generated in the multiple semiconductor grooves 143 regions are perpendicular to the stress directions generated in the corresponding patterned first solderable metal layer 202, which is beneficial to the release of horizontal stress in different regions, can alleviate the risk of material delamination during the thermal process, increase the reliability of the device, and help reduce wafer warping.

[0053] A variation of the present invention is as follows: Figure 7 As shown in the cross-sectional schematic diagram of 7A, the difference from the above embodiment is that an additional bottom solderable metal layer 302 is provided below the bottom metal layer 101.

[0054] Typically, the bottom solderable metal layer 302 is made of the same material as the patterned first solderable metal layer 202 on the upper surface, has the same thickness, and is formed in the same process step. In a practical embodiment, the bottom solderable metal layer 302 is made of the same copper alloy as the patterned first solderable metal layer 202 on the upper surface, has a thickness of 5-20 um, and is formed by the same electroplating process. The patterned first solderable metal layer 202 on the upper surface and the bottom solderable metal layer 302 formed at the same time are conducive to reducing wafer warpage.

[0055] Another variation of the embodiment of the utility model is shown in the cross-sectional schematic diagram in 7B, which is different from the above-mentioned embodiment in that the height of the patterned first solderable metal layer 202 is higher than the insulating stress release layer 204, and a portion of the patterned first solderable metal layer 202 is interconnected above the adjacent insulating stress release layer 204.

[0056] This structure is beneficial to increase the welding area between the chip and the upper copper plate 133 of the surface mount package above it, making the on-current distribution on the chip surface more uniform, which is beneficial to reduce the on-resistance and enhance the chip's ability to withstand overshoot current, and can enhance the chip's heat dissipation effect.

[0057] In the above-described embodiment, the insulating stress release layer 204 located between the patterned first solderable metal layers 202 is used to relieve the stress of the first solderable metal layer 202. One disadvantage is that the insulating stress release layer 204 is an insulating material, so the soldering area between the chip and the upper copper sheet 133 of the surface mount package above it is small and the current conduction area of ​​the device is small. Further, a modified embodiment of the utility model for increasing the soldering area and the conduction area is as follows.

[0058] A variation of the present invention is implemented as follows: Figure 88A shows a top view of the solderable metal layer, and a schematic cross-sectional view is shown in 8B. The difference from the above embodiment is that a metal stress release layer 205 is provided between the patterned first solderable metal layers 202, wherein the metal stress release layer 205 located above the source metal layer and the metal stress release layer 205 located above the gate metal layer are insulated and isolated. The first solderable metal layers 202 and the metal stress release layer 205 together constitute the soldering surface on the chip, and an insulating stress release layer 204 is located on the periphery of the soldering surface.

[0059] The metal stress release layer 205 may be a metal or alloy such as platinum, gold, silver, nickel, aluminum, indium, tin, etc. The metal stress release layer 205 serves to relieve the stress in the adjacent solderable metal layer. As shown in FIG8B , generally, the thickness of the metal stress release layer 205 is thinner than the patterned first solderable metal layer 202, and the width of the metal stress release layer 205 is narrower than the adjacent patterned first solderable metal layer 202.

[0060] In some variant embodiments, the height of the patterned first solderable metal layer 202 is higher than the metal stress release layer 205, and a portion of the patterned first solderable metal layer 202 is interconnected above the adjacent insulating stress release layer 204, as shown in FIG8C. This structure is conducive to the flatness of the soldering surface on the chip.

[0061] The patterned first solderable metal layer 202 and the metal stress release layer 205 can adjust the stress direction according to the pattern direction. Preferably, the stress direction is perpendicular to the stress direction generated by the semiconductor groove below in the horizontal plane, which can reduce the warping of the wafer. The patterned first solderable metal layer 202 and the metal stress release layer 205 may have different pattern directions in different areas of the chip in response to the groove structure in the chip, such as Fig. 9 shown.

[0062] Those skilled in the art should know that the above manufacturing steps only list key steps and do not show the complete steps of forming a device. Specific detailed manufacturing steps can be obtained based on common manufacturing process steps and common sense knowledge in the field and can be appropriately increased, decreased or changed.

[0063] In addition, those skilled in the art should know that the structural features and process steps mentioned in the above-mentioned embodiments of the present invention can be combined with each other to form more device structures and manufacturing processes of embodiments of the present invention.

Claims

1. A low stress deformation power device with a thick weldable metal layer, the power device comprising a bottom metal layer, a semiconductor layer disposed above the bottom metal layer, an upper surface metal layer disposed above the semiconductor layer, a semiconductor device structure disposed within the semiconductor layer, and periodically arranged semiconductor grooves disposed within the semiconductor device structure, characterized in that: More than two weldable metal units are arranged on the upper surface metal layer, wherein an insulating layer is arranged between the weldable metal units for welding the gate metal and the source metal, the weldable metal units are composed of one or more patterned weldable metal layers, and a stress release layer for releasing the surface stress of adjacent weldable metal units is arranged between the weldable metal units.

2. The low stress deformation power device with thick solderable metal layer as claimed in claim 1, characterized in that: The insulating stress release layer is lower than the solderable metal layer and is covered by the solderable metal layer; or The metal stress release layer is lower than the solderable metal layer; or The metal stress release layer is lower than the solderable metal layer and is covered by the solderable metal layer.

3. The low stress deformation power device with thick solderable metal layer as claimed in claim 1, characterized in that: A stress release layer for absorbing the stress of adjacent solderable metal layers is also provided between the solderable metal layers.

4. The low stress deformation power device with thick solderable metal layer as claimed in claim 1, characterized in that: The weldable metal unit is composed of a plurality of weldable metal layers. The weldable metal layers constituting each weldable metal unit have the same shape and the spacing between adjacent weldable metal layers is equal.

5. The low stress deformation power device with a thick solderable metal layer according to any one of claims 1 to 4, characterized in that: The weldable metal unit and the semiconductor groove are both uniformly arranged in a direction, the weldable metal unit generates a first directional stress, and the semiconductor groove generates a second directional stress, and the directions of the first stress and the second stress are perpendicular.

6. The low stress deformation power device with thick solderable metal layer as claimed in claim 5, characterized in that: The weldable metal layer constituting the weldable metal unit is polygonal, circular, elliptical or a combination of the above shapes.

7. The low stress deformation power device with thick solderable metal layer as claimed in claim 5, characterized in that: The semiconductor trenches and the weldable metal units are arranged in different directions in different regions within the semiconductor, and the arrangement directions of the weldable metal units and the semiconductor trenches in the same region are perpendicular to each other.

8. The low stress deformation power device with thick solderable metal layer as claimed in claim 1, characterized in that: A bottom solderable metal layer made of the same material as the solderable metal layer is also provided below the bottom metal layer.

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